JPH08130376A - Manufacture of multilayer printed wiring board - Google Patents
Manufacture of multilayer printed wiring boardInfo
- Publication number
- JPH08130376A JPH08130376A JP6265900A JP26590094A JPH08130376A JP H08130376 A JPH08130376 A JP H08130376A JP 6265900 A JP6265900 A JP 6265900A JP 26590094 A JP26590094 A JP 26590094A JP H08130376 A JPH08130376 A JP H08130376A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- plating
- lid
- opening
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、例えば、電子機器、電
気機器、コンピュータ及び通信機器等に用いられるPG
A、BGA、チップキャリアのような半導体チップやチ
ップ部品を搭載するために用いられる多層プリント配線
板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a PG used in, for example, electronic equipment, electric equipment, computers and communication equipment.
The present invention relates to a method for manufacturing a multilayer printed wiring board used for mounting semiconductor chips and chip components such as A, BGA and chip carriers.
【0002】[0002]
【従来の技術】近年、半導体チップやチップ部品等の電
子部品は軽薄短小化が進み、それに伴い電子部品の搭載
基板も高密度化の要求が強くなってきている。また、半
導体パッケージは放熱性の良いものを使用する必要があ
るため、従来はセラミック素材のものが用いられていた
が、セラミック素材は高価なことから、高密度化が可能
で低価格化を実現できる多層プリント配線板が用いられ
るようになってきた。PGAに代表される開口部を有す
るこのような多層プリント配線板の製造方法は、大きく
分けて2種類の方法がある。すなわち、第一の方法は、
最上層に開口部を有さない積層体にスルーホールを形成
し、スルーホールに化学メッキを施した後に、開口部を
形成する多層プリント配線板の製造方法であり、第二の
方法は、開口部を有する積層体にスルーホールを形成
し、スルーホールに化学メッキを施した後に、絶縁部に
ついた不要な化学メッキ部を取り除く多層プリント配線
板の製造方法である。2. Description of the Related Art In recent years, electronic parts such as semiconductor chips and chip parts have become lighter, thinner, shorter, and smaller, and accordingly, there has been an increasing demand for higher density mounting boards for electronic parts. In addition, since it is necessary to use a semiconductor package with good heat dissipation, a ceramic material has been used in the past, but since the ceramic material is expensive, it is possible to increase the density and reduce the cost. Multilayer printed wiring boards that can be used have come to be used. There are roughly two types of methods for manufacturing such a multilayer printed wiring board having an opening represented by PGA. That is, the first method is
The second method is a method for manufacturing a multilayer printed wiring board in which a through hole is formed in a laminated body having no opening in the uppermost layer, the through hole is subjected to chemical plating, and then the opening is formed. This is a method for manufacturing a multilayer printed wiring board in which a through hole is formed in a laminated body having a portion, the through hole is subjected to chemical plating, and then the unnecessary chemical plated portion attached to the insulating portion is removed.
【0003】前記第一の方法は、例えば、特公平2−5
014号公報や特開平4−369252号公報等で開示
されている。The first method is, for example, Japanese Patent Publication No. 2-5.
It is disclosed in Japanese Patent Application No. 014, Japanese Patent Application Laid-Open No. 4-369252, and the like.
【0004】特公平2−5014号公報では、積層され
た複数枚の板体に半導体素子収納穴、スルーホールなら
びに配線パターンが形成され、スルーホールにはメッキ
が施されているプリント基板型PGAパッケージの製造
方法において、前記積層された複数枚の板体は、両外側
の板体には半導体素子収納穴を形成するための開口が形
成されておらず、両外側の板体の外面を除く配線パター
ンは、両外側の板体によって密閉されるように積層され
ており、該積層された複数枚の板体にスルーホールを形
成するとともにスルーホールにメッキを施し、その後両
外側の板体の少なくとも一方に半導体素子収納穴を形成
するための開口を形成するようにしたことを特徴とする
プリント基板型PGAパッケージの製造方法が開示され
ている。以上が特公平2−5014号公報に開示された
プリント基板型PGAパッケージの製造方法である。し
かしながら、この製造方法では以下に示すようないくつ
かの欠点を有してる。すなわち、開口部を覆う蓋が板体
であるため、蓋の厚みが厚くなってしまう。さらに、最
外層の開口部に前記板体の加工時の屑が回路パターンの
上やスルーホール内部に付着するという問題があった。In Japanese Patent Publication No. 2-5014, a printed circuit board type PGA package in which semiconductor element accommodating holes, through holes and wiring patterns are formed in a plurality of laminated plates, and the through holes are plated. In the manufacturing method, the laminated plurality of plate bodies are not formed with openings for forming semiconductor element storage holes in the outer plate bodies, and the wiring except the outer surface of the outer plate bodies is provided. The patterns are laminated so as to be sealed by the plate bodies on both outer sides. Through holes are formed in the laminated plate bodies and the through holes are plated, and then at least the plate bodies on both outer sides are plated. A method for manufacturing a printed circuit board type PGA package is disclosed in which an opening for forming a semiconductor element accommodation hole is formed on one side. The above is the method of manufacturing a printed circuit board type PGA package disclosed in Japanese Patent Publication No. 2-5014. However, this manufacturing method has some drawbacks as described below. That is, since the lid that covers the opening is a plate, the thickness of the lid increases. Further, there is a problem that the scraps during the processing of the plate adhere to the opening of the outermost layer on the circuit pattern or inside the through hole.
【0005】一方、特開平4−369252号公報で
は、配線を形成した複数枚の有機系基板を、中央部に底
面が平坦な凹部を形成しながら積層して段付部を有する
多層配線板を形成し、かつ、凹部以外の任意の個所にス
ルーホールを形成し、スルーホールにメッキを施して半
導体素子搭載用装置を製造する方法において、有機系基
板を積層後、最外側に銅箔を接着し、ついでスルーホー
ルを形成し、表面及びスルーホールにメッキ被膜を形成
した後、前記凹部に対応する部分のメッキ被膜及び銅箔
をエッチングにより取り除いて開口状態にすることを特
徴とする半導体素子搭載用装置の製造法が開示されてい
る。以上が特開平4−369252号公報に開示された
多層プリント配線板の製造方法である。しかしながら、
この製造方法でも以下に示すような欠点を有している。
すなわち、凹部の蓋となっている銅箔を除去し開口状態
とするエッチングの際に、開口部内部の回路まで侵され
る。これを防止するため、実施例に示されているよう
に、回路層各層にはんだメッキとオーバーコート樹脂の
印刷、硬化を行うプロセスが必要であり、非常に手間が
かかり、はんだメッキ部の除去工程も手間がかかる上、
エッチングが不十分でピンホール等にはんだが残存する
と、その後にメッキされるメッキ層との密着が不十分に
なるという問題があった。On the other hand, in Japanese Unexamined Patent Publication (Kokai) No. 4-369252, a multilayer wiring board having a stepped portion is formed by stacking a plurality of organic substrates on which wiring is formed while forming a concave portion having a flat bottom surface in the central portion. In the method of forming a through hole at any place other than the recess and plating the through hole to manufacture a semiconductor element mounting device, after stacking organic substrates, copper foil is bonded to the outermost side Then, a through hole is formed, a plating film is formed on the surface and the through hole, and then the plating film and the copper foil in the portion corresponding to the recess are removed by etching to form an open state. A method of manufacturing a device is disclosed. The above is the method for manufacturing a multilayer printed wiring board disclosed in Japanese Patent Laid-Open No. 4-369252. However,
This manufacturing method also has the following drawbacks.
That is, even when the copper foil forming the lid of the recess is removed to form an open state, the circuit inside the opening is also attacked. In order to prevent this, as shown in the example, it is necessary to perform a process of solder plating and printing of the overcoat resin on each layer of the circuit layer, and curing, which is very time-consuming and requires a step of removing the solder plating part. It also takes time,
When the etching is insufficient and the solder remains in the pinholes or the like, there is a problem that the adhesion with the plating layer to be plated thereafter becomes insufficient.
【0006】前記第二の方法は、例えば、特願平6−1
0123で本発明者が提案している。すなわち、第1
の回路パターンと開口部を有する第1のプリント配線板
及び第2の回路パターンを有する第2のプリント配線板
とを接着用シートを介在して被圧体とし、この被圧体を
加熱加圧成形して上記開口部内に第2の回路パターンを
露出した積層体を得る工程;積層体に、スルーホール
を穿設した後、核付けを行い、第1及び第2の回路パタ
ーン、絶縁回路パターン及びスルーホールに化学メッキ
を施す工程;上記スルーホールの開孔部をカバーで閉
塞した後にソフトエッチングを行って上記化学メッキを
除去し、上記の核を除去する工程;上記カバーを取り
除いた後、第1及び第2の回路パターンおよびスルーホ
ールに電気メッキを施す工程;前記積層体の最外層と
なる第1のプリント配線板の表面及び第2のプリント配
線板の裏面にレジストをコーティングする工程;前記
積層体のレジストから露出している回路パターンおよび
スルーホールに金メッキを施す工程からなる開口部を有
する多層プリント配線板の製造方法である。ところが、
開口部を有している多層板に直接、化学メッキを行うこ
とから開口部の露出導体以外の絶縁部にもメッキされる
ことになる。したがって、エッチング工程において絶縁
部分に化学メッキされた不要部分を取り除くことになる
が、その際、過激なエッチングを行うと、回路部までも
エッチングされ、ついには完全に除去されることにな
る。一方、マイルドな条件でエッチングを行うと、今度
は逆に化学メッキの核として用いられているパラジウム
等が十分に取り除けないことになる。その結果エッチン
グ後の電気メッキ(ニッケルメッキ+金メッキ)等で、
絶縁部に残されたパラジウム核周辺もメッキされること
になり、回路部と回路部との間が短絡したようなメッキ
が施されることになる。したがって、エッチングには細
心の工程管理条件が必要となり、ファインパターンにな
ればなるほどその管理は困難になる。The second method is, for example, Japanese Patent Application No. 6-1.
The present inventor proposed in 0123. That is, the first
Of the circuit pattern and the first printed wiring board having the opening and the second printed wiring board having the second circuit pattern as an object to be pressured through an adhesive sheet, and the object to be heated is heated and pressed. A step of molding to obtain a laminated body in which the second circuit pattern is exposed in the opening; through holes are formed in the laminated body, and then nucleation is performed to form the first and second circuit patterns and the insulating circuit pattern. And a step of subjecting the through hole to chemical plating; a step of closing the opening of the through hole with a cover and then performing soft etching to remove the chemical plating to remove the nucleus; and after removing the cover, A step of electroplating the first and second circuit patterns and the through holes; a resist is coated on the front surface of the first printed wiring board and the back surface of the second printed wiring board which are the outermost layers of the laminate. A step of coating; a method for manufacturing a multilayer printed wiring board having the opening portion comprising a step of resist plated with gold on the circuit pattern and the through holes are exposed from the laminate. However,
Since the multilayer plate having the opening is directly subjected to the chemical plating, the insulating portion other than the exposed conductor of the opening is also plated. Therefore, in the etching process, the unnecessary portion chemically plated on the insulating portion is removed. However, if radical etching is performed at this time, the circuit portion is also etched and finally completely removed. On the other hand, if the etching is performed under mild conditions, the palladium and the like, which are used as nuclei for chemical plating, cannot be sufficiently removed this time. As a result, by electroplating (nickel plating + gold plating) after etching,
The periphery of the palladium nucleus remaining in the insulating portion will also be plated, and plating will be performed as if the circuit portions were short-circuited. Therefore, etching requires strict process control conditions, and the finer the pattern, the more difficult the control becomes.
【0007】[0007]
【発明が解決しようとする課題】本発明は前記の事情に
鑑みてなされたもので、その目的とするところは、多層
プリント配線板のトータル厚みを薄くし、信頼性の高い
回路が得られ、生産効率の向上が図れ、省工程になる多
層プリント配線板の製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the total thickness of a multilayer printed wiring board to obtain a highly reliable circuit. An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board, which can improve the production efficiency and save the process.
【0008】[0008]
【課題を解決するための手段】本発明の請求項1に係る
多層プリント配線板の製造方法は、積層された複数枚の
絶縁基板1に電子部品搭載用の収納穴2、スルーホール
3及び導体回路4が形成され、スルーホール3にはメッ
キが施されている多層プリント配線板の製造方法におい
て、電子部品搭載部5及び導体回路4を有する最下部絶
縁基板1dと、この最下部絶縁基板1dの上方に配置さ
れる前記収納穴2に対応する開口部6を備える最上部絶
縁基板1uと、この最上部絶縁基板1uと前記最下部絶
縁基板1dとの間に配置される、前記開口部6及び導体
回路4を有する内層回路基板1nの所定枚数とを、それ
ぞれ前記収納穴2に対応する開口部6を備える接着シー
ト7を介して加圧接着し、さらに、最上部絶縁基板1u
の上に銅箔8を前記加圧接着同時に又はその後に接着し
て前記収納穴2の開口部6が銅箔8の蓋9で覆われた積
層体10とし、この積層体10にスルーホール3を形成
し、このスルーホール3にメッキを施し、次いで、積層
体10の最外層回路を形成するとともに、前記収納穴2
の開口部6が銅箔8の蓋9で覆われた状態で、この蓋9
を電気的に孤立させた後、前記収納穴2の開口部6に対
応する部分の前記蓋9を機械的加工により所定の開口よ
り小さく粗切り除去して開口し、蓋9の残存部9aが形
成されている状態で、露出している前記導体回路4の露
出面に銅よりエッチング溶解性の小さい金属被膜を電気
メッキにより導体保護層28として形成した後に、前記
残存部9aをエッチングにより除去して、前記収納穴2
を開口することを特徴とする。According to a first aspect of the present invention, there is provided a method for manufacturing a multilayer printed wiring board, comprising: a plurality of laminated insulating substrates 1 for accommodating electronic parts, a through hole 3, a through hole 3 and a conductor. In a method for manufacturing a multilayer printed wiring board in which a circuit 4 is formed and through holes 3 are plated, a lowermost insulating substrate 1d having an electronic component mounting portion 5 and a conductor circuit 4, and a lowermost insulating substrate 1d. An uppermost insulating substrate 1u having an opening 6 corresponding to the accommodation hole 2 arranged above the opening 6, and the opening 6 arranged between the uppermost insulating substrate 1u and the lowermost insulating substrate 1d. And a predetermined number of inner layer circuit boards 1n having conductor circuits 4 are pressure-bonded via an adhesive sheet 7 having openings 6 corresponding to the storage holes 2, respectively, and further, the uppermost insulating substrate 1u.
A copper foil 8 is adhered to the top of the container at the same time as or after the pressure bonding to form a laminated body 10 in which the opening 6 of the storage hole 2 is covered with a lid 9 of the copper foil 8. And through-holes 3 are plated, then the outermost layer circuit of the laminated body 10 is formed and the through holes 3 are formed.
With the opening 6 of the lid 6 covered with the lid 9 of the copper foil 8,
Are electrically isolated, and then the lid 9 in the portion corresponding to the opening 6 of the storage hole 2 is mechanically machined to be coarsely cut to a size smaller than a predetermined opening to open the remaining portion 9a of the lid 9. In the formed state, a metal coating having a smaller etching solubility than copper is formed on the exposed exposed surface of the conductor circuit 4 as a conductor protective layer 28 by electroplating, and then the remaining portion 9a is removed by etching. The storage hole 2
It is characterized by opening.
【0009】本発明の請求項2に係る多層プリント配線
板の製造方法は、前記金属被膜がはんだメッキ、ニッケ
ルメッキ、ニッケル燐メッキ、ニッケルスズメッキ、ク
ロムメッキ、パラジウムメッキ及びこれらの合金メッキ
からなる群から選択される少なくとも一種類のメッキで
あることを特徴とする請求項1記載の多層プリント配線
板の製造方法。In the method for manufacturing a multilayer printed wiring board according to a second aspect of the present invention, the metal coating is a group consisting of solder plating, nickel plating, nickel phosphorus plating, nickel tin plating, chromium plating, palladium plating and alloy plating thereof. 2. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the plating is at least one kind selected from the group consisting of:
【0010】本発明の請求項3に係る多層プリント配線
板の製造方法は、前記銅箔8の厚みが9〜70μmであ
ることを特徴とする。A method for manufacturing a multilayer printed wiring board according to a third aspect of the present invention is characterized in that the copper foil 8 has a thickness of 9 to 70 μm.
【0011】[0011]
【作用】本発明の請求項1乃至請求項3に係る多層プリ
ント配線板の製造方法では、収納穴2の開口部6の蓋9
が銅箔8から成り基板を含まないため、厚みを薄くで
き、機械的加工による粗切り除去が簡単である。しか
も、蓋9の残存部9aは、銅箔8のみからなり、電気的
に孤立しているので、各層の露出している前記導体回路
4の露出面に銅よりエッチング溶解性の小さい金属被膜
を電気メッキにより導体保護層28として一括して形成
するときに、前記残存部9aには、金属被膜が形成され
ない。したがって、前記残存部9aをエッチングによ
り、容易に精度よく除去して、前記収納穴2を開口する
ことができる。In the method for manufacturing a multilayer printed wiring board according to claims 1 to 3 of the present invention, the lid 9 of the opening 6 of the storage hole 2 is covered.
Since it is made of the copper foil 8 and does not include the substrate, the thickness can be reduced and the rough cutting removal by mechanical processing is easy. Moreover, since the remaining portion 9a of the lid 9 is made of only the copper foil 8 and is electrically isolated, the exposed exposed surface of the conductor circuit 4 of each layer is coated with a metal film having a smaller etching solubility than copper. When the conductor protection layer 28 is collectively formed by electroplating, no metal coating is formed on the remaining portion 9a. Therefore, the remaining portion 9a can be easily and accurately removed by etching to open the storage hole 2.
【0012】[0012]
【実施例】以下本発明を一実施例によって説明する。EXAMPLES The present invention will be described below with reference to examples.
【0013】図1(a)に示すように、電子部品搭載部
5及び導体回路4を有する最下部絶縁基板1dの上に、
電子部品搭載用の収納穴2に対応する開口部6及び導体
回路4を有する内層回路基板1nの所定枚数、例えば、
2枚をそれぞれ、プリプレグ等の接着シート7を介して
載置する。この内層回路基板1nの上に、開口部6を備
える最上部絶縁基板1uをプリプレグ等の接着シート7
を介して載置し、被圧体14とする。この被圧体14を
加圧接着した後、図1(b)に示すように、最上部絶縁
基板1uの上に前記収納穴2に対応する開口部6を備え
るプリプレグ11を介して銅箔8を前記加圧接着と同時
に又はその後に接着して、前記収納穴2の開口部6が蓋
9で覆われた積層体10とする。前記蓋9は、銅箔8の
みから成るものである。上記銅箔8の厚みは9〜70μ
mが好ましい。すなわち、銅箔8の厚みが9μm未満の
場合には、スルーホールメッキ工程や外層回路形成のエ
ッチング工程中に破損し易く、収納穴2の内部の導体回
路4が侵される危険がある。銅箔8の厚みが70μmを
越える場合には、この銅箔8の回路形成が困難で、精度
が悪くなる。As shown in FIG. 1A, on the lowermost insulating substrate 1d having the electronic component mounting portion 5 and the conductor circuit 4,
A predetermined number of inner layer circuit boards 1n each having an opening 6 corresponding to a housing hole 2 for mounting an electronic component and a conductor circuit 4, for example,
Each of the two sheets is placed via an adhesive sheet 7 such as a prepreg. On this inner layer circuit board 1n, an uppermost insulating substrate 1u having an opening 6 is attached to an adhesive sheet 7 such as a prepreg.
Then, the pressure-sensitive body 14 is mounted via After pressure-bonding the pressed body 14, as shown in FIG. 1B, the copper foil 8 is provided on the uppermost insulating substrate 1u via the prepreg 11 having the opening 6 corresponding to the storage hole 2. Is bonded at the same time as or after the pressure bonding to form the laminated body 10 in which the opening 6 of the storage hole 2 is covered with the lid 9. The lid 9 is made of only the copper foil 8. The copper foil 8 has a thickness of 9 to 70 μm.
m is preferred. That is, when the thickness of the copper foil 8 is less than 9 μm, the copper foil 8 is easily damaged during the through-hole plating process or the etching process for forming the outer layer circuit, and there is a risk that the conductor circuit 4 inside the housing hole 2 is damaged. If the thickness of the copper foil 8 exceeds 70 μm, it is difficult to form a circuit for the copper foil 8 and the accuracy deteriorates.
【0014】図1(c)に示すように、この積層体10
の上下に連通するスルーホール3を形成し、核付けを行
い、このスルーホール3の内面及び最外層に化学メッキ
及び電気メッキ等のメッキを施す。As shown in FIG. 1C, this laminated body 10
The through holes 3 communicating with the upper and lower sides of the through hole 3 are formed and nucleated, and plating such as chemical plating and electroplating is applied to the inner surface and the outermost layer of the through holes 3.
【0015】図1(d)に示すように、前記スルーホー
ル3の上下面と前記収納穴2を覆う銅箔8と積層体10
の下面の最外層の必要部分とをエッチングレジストで覆
い、露光、現像エッチングを行うことにより積層体10
の最外層の導体回路4を形成して、同時に、開口部6の
外周に連続する絶縁部(銅箔を除去した部分)を設け
て、前記収納穴2の開口部6が銅箔8の蓋9で覆われた
状態で、この蓋9を電気的に孤立させる。すなわち、電
気的に孤立させることにより、次工程で金属被膜を電気
メッキで導体保護層28として形成する際に、蓋9に金
属被膜が被着しないようになる。次いで、図1(e)に
示すように、前記収納穴2の開口部6に対応する部分の
前記蓋9を機械的加工により所定の開口より小さく粗切
り除去して開口することにより、蓋9の銅箔8のみから
なる残存部9aが形成されている状態になる。この蓋9
の粗切り除去方法としては、スリッティングカッタ−、
ル−タ−その他の刃物切断、圧切、高圧水流切断等の機
械的な切断により行う。また簡易的な手作業やピールに
よるひきはがしであってもよいことは言うまでもない。
上記銅箔8の厚みは9〜70μmが好ましい。すなわ
ち、銅箔8の厚みが9μm未満の場合には、スルーホー
ルメッキ工程や外層回路形成のエッチング工程中に破損
し易く、収納穴2の内部の導体回路4が侵される危険が
ある。As shown in FIG. 1D, a copper foil 8 covering the upper and lower surfaces of the through hole 3 and the storage hole 2 and a laminated body 10 are provided.
The necessary portion of the outermost layer on the lower surface of the laminate 10 is covered with an etching resist, and exposure and development etching are performed to form a laminate 10.
The outermost conductor circuit 4 is formed, and at the same time, a continuous insulating portion (the portion from which the copper foil is removed) is provided on the outer periphery of the opening 6, and the opening 6 of the storage hole 2 covers the copper foil 8. In the state of being covered with 9, the lid 9 is electrically isolated. That is, the electrical isolation prevents the lid 9 from being coated with the metal coating when the conductor coating layer 28 is formed by electroplating in the next step. Then, as shown in FIG. 1 (e), the lid 9 at a portion corresponding to the opening 6 of the storage hole 2 is mechanically machined to be roughly cut into smaller portions than a predetermined opening, and the lid 9 is opened. The remaining portion 9a consisting of the copper foil 8 is formed. This lid 9
Rough cutting removal method, slitting cutter,
It is carried out by mechanical cutting such as router cutting, blade cutting, pressure cutting, high pressure water stream cutting and the like. Needless to say, simple manual work or peeling off by peeling may be used.
The thickness of the copper foil 8 is preferably 9 to 70 μm. That is, when the thickness of the copper foil 8 is less than 9 μm, the copper foil 8 is easily damaged during the through-hole plating process or the etching process for forming the outer layer circuit, and there is a risk that the conductor circuit 4 inside the housing hole 2 is damaged.
【0016】次に、図1(f)に示すように、蓋9の銅
箔8のみからなる残存部9aが形成されている状態で、
露出している前記導体回路4の露出面に、例えば、電気
はんだメッキ等により、銅よりエッチング溶解性の小さ
い金属被膜を電気メッキにより導体保護層28として形
成する。前記金属被膜としては、はんだメッキ以外に、
ニッケルメッキ、ニッケル燐メッキ、ニッケルスズメッ
キ、クロムメッキ、パラジウムメッキ及びこれらの合金
メッキからなる群から選択される少なくとも一種類のメ
ッキが例示できる。電気メッキにより金属被膜を導体保
護層28として形成する際、前記残存部9aは、電気的
に孤立しているので、この残存部9aには、金属被膜が
形成されない。Next, as shown in FIG. 1 (f), with the remaining portion 9a of the lid 9 made of only the copper foil 8 being formed,
On the exposed surface of the exposed conductor circuit 4, a metal coating having a smaller etching solubility than copper is formed as a conductor protection layer 28 by electroplating, for example, by electrosolder plating. As the metal coating, other than solder plating,
At least one kind of plating selected from the group consisting of nickel plating, nickel phosphorus plating, nickel tin plating, chromium plating, palladium plating and alloy platings thereof can be exemplified. When the metal coating is formed as the conductor protection layer 28 by electroplating, the remaining portion 9a is electrically isolated, so that no metal coating is formed on the remaining portion 9a.
【0017】したがって、図1(g)に示すように、前
記残存部9aをエッチングにより除去して、前記収納穴
2を精度よく開口することができる。Therefore, as shown in FIG. 1 (g), the remaining portion 9a can be removed by etching to accurately open the storage hole 2.
【0018】次いで、図1(h)に示すように、前記は
んだメッキをエッチングにより除去する。ただし、ニッ
ケルメッキ、ニッケル燐メッキ、ニッケルスズメッキ、
クロムメッキ、パラジウムメッキ及びこれらの合金メッ
キからなる群から選択される少なくとも一種類のメッキ
が導体保護層28として形成されている場合には、導体
保護層28を除去せずに、導体保護層28が形成されて
いる状態のままで、次工程に進んでもよい。Next, as shown in FIG. 1H, the solder plating is removed by etching. However, nickel plating, nickel phosphorus plating, nickel tin plating,
When at least one kind of plating selected from the group consisting of chrome plating, palladium plating and alloy platings thereof is formed as the conductor protective layer 28, the conductor protective layer 28 is not removed and the conductor protective layer 28 is not removed. It is possible to proceed to the next step with the state of being formed.
【0019】図1(i)に示すように、積層体10の両
外面及び収納穴2の内部を必要に応じてソルダーレジス
ト17で覆った後、ニッケルメッキ(図示せず)及び金
メッキ18を施すことにより、配線パターンを形成す
る。As shown in FIG. 1 (i), both outer surfaces of the laminated body 10 and the inside of the housing hole 2 are covered with a solder resist 17 if necessary, and then nickel plating (not shown) and gold plating 18 are applied. Thereby, the wiring pattern is formed.
【0020】このように、プリント基板型PGAパッケ
ージ等の本発明に係る多層プリント配線板の製造方法で
は、最上部絶縁基板1uの上に銅箔8を前記加圧接着同
時に又はその後に接着して前記収納穴2の開口部6が銅
箔8を含む蓋9で覆われた積層体10とするので、スル
ーホール3にメッキを施す際に、収納穴2内の導体回路
4にメッキが被着するのを防ぐことができるとともに、
最上部絶縁基板1uのルーター加工部にはザグリを入れ
る必要がない。すなわち、従来ではザグリ加工の必要性
から最上部絶縁基板1uの厚みをあらかじめ厚くする必
要性があったが、本発明に係る多層プリント配線板の製
造方法では、このような必要はなく、多層プリント配線
板のトータル厚みを薄くすることが可能である。As described above, in the method of manufacturing a multilayer printed wiring board according to the present invention such as a printed circuit board type PGA package, the copper foil 8 is bonded onto the uppermost insulating substrate 1u at the same time as the pressure bonding or after that. Since the opening 6 of the accommodation hole 2 is the laminated body 10 covered with the lid 9 including the copper foil 8, when the through hole 3 is plated, the conductor circuit 4 in the accommodation hole 2 is plated. It is possible to prevent
It is not necessary to insert a counterbore in the router processing part of the uppermost insulating substrate 1u. That is, conventionally, it was necessary to increase the thickness of the uppermost insulating substrate 1u in advance due to the need for counterboring. However, in the method for manufacturing a multilayer printed wiring board according to the present invention, such a need is eliminated, and the multilayer printing is not necessary. It is possible to reduce the total thickness of the wiring board.
【0021】従来例のようなエッチングのみで銅箔の開
口部を形成する方法では、各回路層ごとにはんだメッキ
とオーバーコート樹脂の印刷、硬化をそれぞれ別々に行
った後、成形を行うことから工程が多くなる。これに対
して本発明に係る多層プリント配線板の製造方法では、
前記積層体10にスルーホール3を形成し、このスルー
ホール3にメッキを施し、積層体10の最外層回路を形
成して、前記蓋9を電気的に孤立させた後、前記収納穴
2の開口部6に対応する部分の前記蓋9を機械的加工に
より所定の開口より小さく粗切り除去して開口し、蓋9
の銅箔8のみからなる残存部9aが形成されている状態
で、露出している前記導体回路4の露出面に銅よりエッ
チング溶解性の小さい金属被膜を電気メッキにより導体
保護層28として形成した後に、前記残存部9aをエッ
チングにより除去して、前記収納穴2を開口するので、
一括で各層にはんだメッキを行うことが可能となり工程
の簡略化と低コスト化を図ることが可能となる。すなわ
ち、多層プリント配線板のトータル厚みを薄くし、信頼
性の高い回路が得られ、生産効率の向上が図れ、省工程
になる多層プリント配線板の製造方法である。In the method of forming the opening of the copper foil only by etching as in the conventional example, the solder plating and the overcoat resin are printed and cured separately for each circuit layer, and then the molding is performed. There are many steps. On the other hand, in the method for manufacturing a multilayer printed wiring board according to the present invention,
After forming the through hole 3 in the laminated body 10, plating the through hole 3 to form the outermost layer circuit of the laminated body 10, and electrically isolating the lid 9, the housing hole 2 The lid 9 at the portion corresponding to the opening 6 is mechanically machined to be coarsely cut into smaller pieces than a predetermined opening to open the lid 9.
In the state where the remaining portion 9a consisting only of the copper foil 8 is formed, a metal coating film having a smaller etching solubility than copper is formed as the conductor protective layer 28 on the exposed exposed surface of the conductor circuit 4 by electroplating. After that, the remaining portion 9a is removed by etching to open the storage hole 2,
Since it is possible to perform solder plating on each layer in a lump, it becomes possible to simplify the process and reduce the cost. That is, it is a method for manufacturing a multilayer printed wiring board, in which the total thickness of the multilayer printed wiring board is reduced, a highly reliable circuit is obtained, production efficiency is improved, and the number of steps is reduced.
【0022】[0022]
【発明の効果】本発明の請求項1乃至請求項3に係るの
多層プリント配線板の製造方法によると、多層プリント
配線板のトータル厚みを薄くでき、信頼性の高い回路が
得られ、生産効率の向上が図れ、省工程になる。According to the method for manufacturing a multilayer printed wiring board according to the first to third aspects of the present invention, the total thickness of the multilayer printed wiring board can be reduced, a highly reliable circuit can be obtained, and the production efficiency can be improved. Can be improved and the number of steps can be reduced.
【図1】本発明の実施例に係る多層プリント配線板の製
造方法の断面図であり、(a)は被圧体の断面図、
(b)は最上部絶縁基板の上に銅箔を配置した断面図、
(c)はスルーホールを形成した積層体の断面図、
(d)は積層体の外層部の回路形成を行った断面図、
(e)は最外層の蓋を粗切り除去して収納穴を開口した
状態の断面図、(f)は露出している導体回路の露出面
に導体保護層を形成した断面図、(g)は蓋の残存部を
エッチングにより除去して収納穴を開口した断面図、
(h)は導体保護層を除去した断面図、(i)はニッケ
ルメッキ及び金メッキを施すことにより、配線パターン
を形成した多層プリント配線板の断面図である。FIG. 1 is a cross-sectional view of a method for manufacturing a multilayer printed wiring board according to an embodiment of the present invention, in which (a) is a cross-sectional view of a body to be pressed,
(B) is a cross-sectional view in which a copper foil is arranged on the uppermost insulating substrate,
(C) is a cross-sectional view of a laminated body in which through holes are formed,
(D) is a cross-sectional view of a circuit formed on the outer layer portion of the laminate,
(E) is a cross-sectional view showing a state in which a storage hole is opened by roughly removing the outermost layer lid, (f) is a cross-sectional view in which a conductor protective layer is formed on the exposed surface of the exposed conductor circuit, (g) Is a cross-sectional view in which the remaining portion of the lid is removed by etching to open the storage hole,
(H) is a cross-sectional view with the conductor protection layer removed, and (i) is a cross-sectional view of a multilayer printed wiring board on which a wiring pattern is formed by performing nickel plating and gold plating.
1 絶縁基板 1d 最下部絶縁基板 1n 内層回路基板 1u 最上部絶縁基板 2 収納穴 3 スルーホール 4 導体回路 5 電子部品搭載部 6 開口部 7 接着シート 8 銅箔 9 蓋 9a 残存部 10 積層体 28 導体保護層 1 Insulating Substrate 1d Lowermost Insulating Substrate 1n Inner Layer Circuit Substrate 1u Uppermost Insulating Substrate 2 Storage Hole 3 Through Hole 4 Conductor Circuit 5 Electronic Component Mounting Part 6 Opening 7 Adhesive Sheet 8 Copper Foil 9 Lid 9a Remaining Part 10 Laminate 28 Conductor Protective layer
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/06 K 3/24 A 7511−4E 3/42 A 7511−4E (72)発明者 樋口 徹 大阪府門真市大字門真1048番地松下電工株 式会社内Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI Technical indication location H05K 3/06 K 3/24 A 7511-4E 3/42 A 7511-4E (72) Inventor Toru Higuchi Osaka Prefecture 1048, Kadoma, Kadoma-shi, Matsushita Electric Works Co., Ltd.
Claims (3)
子部品搭載用の収納穴(2)、スルーホール(3)及び
導体回路(4)が形成され、スルーホール(3)にはメ
ッキが施されている多層プリント配線板の製造方法にお
いて、電子部品搭載部(5)及び導体回路(4)を有す
る最下部絶縁基板(1d)と、この最下部絶縁基板(1
d)の上方に配置される前記収納穴(2)に対応する開
口部(6)を備える最上部絶縁基板(1u)と、この最
上部絶縁基板(1u)と前記最下部絶縁基板(1d)と
の間に配置される、前記開口部(6)及び導体回路
(4)を有する内層回路基板(1n)の所定枚数とを、
それぞれ前記収納穴(2)に対応する開口部(6)を備
える接着シート(7)を介して加圧接着し、さらに、最
上部絶縁基板(1u)の上に銅箔(8)を前記加圧接着
同時に又はその後に接着して前記収納穴(2)の開口部
(6)が銅箔(8)の蓋(9)で覆われた積層体(1
0)とし、この積層体(10)にスルーホール(3)を
形成し、このスルーホール(3)にメッキを施し、次い
で、積層体(10)の最外層回路を形成するとともに、
前記収納穴(2)の開口部(6)が銅箔(8)の蓋
(9)で覆われた状態で、この蓋(9)を電気的に孤立
させた後、前記収納穴(2)の開口部(6)に対応する
部分の前記蓋(9)を機械的加工により所定の開口より
小さく粗切り除去して開口し、蓋(9)の残存部(9
a)が形成されている状態で、露出している前記導体回
路(4)の露出面に銅よりエッチング溶解性の小さい金
属被膜を電気メッキにより導体保護層(28)として形
成した後に、前記残存部(9a)をエッチングにより除
去して、前記収納穴(2)を開口することを特徴とする
多層プリント配線板の製造方法。1. A storage hole (2) for mounting an electronic component, a through hole (3) and a conductor circuit (4) are formed in a plurality of laminated insulating substrates (1), and the through hole (3) is formed in the through hole (3). In a method of manufacturing a plated multilayer printed wiring board, a lowermost insulating substrate (1d) having an electronic component mounting portion (5) and a conductor circuit (4), and a lowermost insulating substrate (1).
d), an uppermost insulating substrate (1u) having an opening (6) corresponding to the accommodation hole (2), the uppermost insulating substrate (1u) and the lowermost insulating substrate (1d) A predetermined number of inner layer circuit boards (1n) having the opening (6) and the conductor circuit (4), which are arranged between
Each of them is pressure-bonded through an adhesive sheet (7) having an opening (6) corresponding to the storage hole (2), and further, a copper foil (8) is added on the uppermost insulating substrate (1u). A laminate (1) in which the opening portion (6) of the storage hole (2) is covered with a lid (9) of a copper foil (8) by pressure-bonding simultaneously or afterwards.
0), a through hole (3) is formed in the laminated body (10), the through hole (3) is plated, and then the outermost layer circuit of the laminated body (10) is formed.
After the opening (6) of the storage hole (2) is covered with the lid (9) of the copper foil (8), the lid (9) is electrically isolated, and then the storage hole (2). Of the lid (9) corresponding to the opening (6) of the lid (9) is mechanically machined to be coarsely cut to a size smaller than a predetermined opening to open the lid (9), and the remaining portion (9)
In the state where a) is formed, a metal coating having a smaller etching solubility than copper is formed as a conductor protective layer (28) on the exposed exposed surface of the conductor circuit (4) by electroplating, and then the remaining. A method for manufacturing a multilayer printed wiring board, characterized in that the portion (9a) is removed by etching to open the storage hole (2).
メッキ、ニッケル燐メッキ、ニッケルスズメッキ、クロ
ムメッキ、パラジウムメッキ及びこれらの合金メッキか
らなる群から選択される少なくとも一種類のメッキであ
ることを特徴とする請求項1記載の多層プリント配線板
の製造方法。2. The metal coating is at least one type of plating selected from the group consisting of solder plating, nickel plating, nickel phosphorus plating, nickel tin plating, chromium plating, palladium plating and alloy platings thereof. The method for manufacturing a multilayer printed wiring board according to claim 1.
あることを特徴とする請求項1から請求項3までのいず
れかに記載の多層プリント配線板の製造方法。3. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the copper foil (8) has a thickness of 9 to 70 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6265900A JPH08130376A (en) | 1994-10-31 | 1994-10-31 | Manufacture of multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6265900A JPH08130376A (en) | 1994-10-31 | 1994-10-31 | Manufacture of multilayer printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08130376A true JPH08130376A (en) | 1996-05-21 |
Family
ID=17423668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6265900A Withdrawn JPH08130376A (en) | 1994-10-31 | 1994-10-31 | Manufacture of multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08130376A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG80603A1 (en) * | 1998-10-30 | 2001-05-22 | Gul Technologies Singapore Ltd | Printed circuit boards with cavity and method of producing the same |
WO2009155808A1 (en) * | 2008-06-24 | 2009-12-30 | 华为技术有限公司 | Printed circuit board, its making method and relative equipment |
WO2010017746A1 (en) * | 2008-08-12 | 2010-02-18 | 华为技术有限公司 | Printed circuit board, method for making the same and equipment with rf power amplifier |
JP2012104815A (en) * | 2010-11-05 | 2012-05-31 | Raytheon Co | Disposable bond gap control structures |
CN104602464A (en) * | 2015-01-23 | 2015-05-06 | 江门崇达电路技术有限公司 | Manufacturing method of copper-cladded ladder hole of circuit board ladder surface and application of manufacturing method |
-
1994
- 1994-10-31 JP JP6265900A patent/JPH08130376A/en not_active Withdrawn
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG80603A1 (en) * | 1998-10-30 | 2001-05-22 | Gul Technologies Singapore Ltd | Printed circuit boards with cavity and method of producing the same |
WO2009155808A1 (en) * | 2008-06-24 | 2009-12-30 | 华为技术有限公司 | Printed circuit board, its making method and relative equipment |
WO2010017746A1 (en) * | 2008-08-12 | 2010-02-18 | 华为技术有限公司 | Printed circuit board, method for making the same and equipment with rf power amplifier |
JP2012104815A (en) * | 2010-11-05 | 2012-05-31 | Raytheon Co | Disposable bond gap control structures |
US9073298B2 (en) | 2010-11-05 | 2015-07-07 | Raytheon Company | Disposable bond gap control structures |
CN104602464A (en) * | 2015-01-23 | 2015-05-06 | 江门崇达电路技术有限公司 | Manufacturing method of copper-cladded ladder hole of circuit board ladder surface and application of manufacturing method |
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