JPS62242343A - Manufacture of semiconductor chip carrier - Google Patents
Manufacture of semiconductor chip carrierInfo
- Publication number
- JPS62242343A JPS62242343A JP61085418A JP8541886A JPS62242343A JP S62242343 A JPS62242343 A JP S62242343A JP 61085418 A JP61085418 A JP 61085418A JP 8541886 A JP8541886 A JP 8541886A JP S62242343 A JPS62242343 A JP S62242343A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- layer
- semiconductor chip
- inner layer
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000463 material Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 15
- 239000007779 soft material Substances 0.000 claims abstract description 10
- 238000012545 processing Methods 0.000 claims abstract description 5
- 239000002390 adhesive tape Substances 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 238000000465 moulding Methods 0.000 claims description 3
- 239000002648 laminated material Substances 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明はビングリッドアレイ（ＰＧ＾）とかリードレス
チップキャリア（ＬＣＣ）等の半導体チップキャリアの
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a semiconductor chip carrier such as a bin grid array (PG^) or a leadless chip carrier (LCC).
［背景技術１
従来上り、プリント配線板をチップキャリアとして半導
体チップが実装されている。この場合多層プリント配線
板にあっては、ｐＩＩＪ３図に示すように表面に内層回
路が形成され、実装用凹部３形成用の凹部３ａ乃至貫通
孔３ｂが形成された複数枚の内層用絶縁基板１からなる
内層材４と実装用凹部形成用の貫通孔３ｃを有する外層
用絶縁基板５を接着剤、接着シート又はローフロープリ
プレグなどのボンディングシート層８を介在させて多層
成形し、次いで孔１３明は加工、スルーホールめっ外及
び外層エツチングなどを施して表面側に実装用凹部３が
形成された多層プリント配線板７′が製造されるが、実
装用凹部３にもめっき層が形成されてしまい、このめっ
き層により汚染されて、半導体チップを実装するには、
めっき層を除去しなければならないという問題があった
。[Background Art 1 Conventionally, semiconductor chips have been mounted using printed wiring boards as chip carriers. In this case, the multilayer printed wiring board includes a plurality of inner layer insulating substrates 1 on which inner layer circuits are formed on the surface and recesses 3a to through holes 3b for forming mounting recesses 3, as shown in Figure pIIJ3. An inner layer material 4 and an outer layer insulating substrate 5 having through holes 3c for forming recesses for mounting are multilayer-molded with a bonding sheet layer 8 such as an adhesive, an adhesive sheet, or a low flow prepreg interposed therebetween. A multilayer printed wiring board 7' is manufactured in which mounting recesses 3 are formed on the surface side by processing, through-hole plating, outer layer etching, etc., but a plating layer is also formed in the mounting recesses 3. However, when mounting a semiconductor chip with contamination from this plating layer,
There was a problem in that the plating layer had to be removed.
このため、本発明者らは、７１４図に示すように表面に
内層回路が形成され、複数枚の内層用絶縁基板１をボン
ディングシート層８を介在させて積層して表面側に実装
用凹部３を有する内層材４を形成し、次いで外層用絶縁
基板５を内層材４の表面に積層し、この後孔１３明は加
工、スルーホールめっき、外層形成を行い、次いで最外
層の外層用絶縁基板５の実装用凹部３に対応する箇所５
ａを切削して実装用凹部３を露出させて形成した多層プ
リント配線板７″に半導体チップを実装する方法を開発
したが、この方法では実装用凹部３がめっきにより汚染
されることはないものの、外層用絶縁基板５の切削加工
に際して内層材４のワイヤーボンディング部９を傷付け
てしまうことがあった。Therefore, as shown in FIG. 714, an inner layer circuit is formed on the surface, and a plurality of inner layer insulating substrates 1 are laminated with a bonding sheet layer 8 interposed therebetween, and a mounting recess 3 is formed on the surface side. Next, an insulating substrate 5 for the outer layer is laminated on the surface of the inner layer material 4, and after this, the holes 13 are processed, through-hole plating is performed, and the outer layer is formed. Location 5 corresponding to the mounting recess 3 of No. 5
We have developed a method for mounting semiconductor chips on a multilayer printed wiring board 7'' formed by cutting a to expose mounting recesses 3. Although this method does not cause the mounting recesses 3 to be contaminated by plating, When cutting the outer layer insulating substrate 5, the wire bonding portion 9 of the inner layer material 4 may be damaged.
［発明の目的１
本発明は上記事情に霞みて為されたものであり、その目
的とするところは、最外層の回路パターンの形成に際し
て実装用凹部がめつ外で汚染されることがなく、又、内
層材のワイヤーボンディング部が傷付くこともない半導
体チップキャリアの製造方法を提供することにある。[Objective of the Invention 1 The present invention has been made in consideration of the above circumstances, and its object is to prevent the mounting recess from being contaminated outside the eye when forming the outermost layer circuit pattern, To provide a method for manufacturing a semiconductor chip carrier in which a wire bonding part of an inner layer material is not damaged.
［発明の開示］
本発明の半導体チップキャリアの製造方法は、内層回路
が形成された複数枚の内層用絶縁基板１を積層して表面
側に半導体チップ２の実装用凹部３を有する内層材４を
形成し、次いで最外層となる外層用絶縁基板５の裏面側
で内層材４の実装用凹部３内のワイヤボンディング部９
に対応する暗所５ｂに粘着テープのような軟質材６を被
覆し、この外層用絶縁基板５を内層材４の表面に積層し
て多層成形し、この後順次化１３明は加工、スルーホー
ルめっき、外層形成を行なって多層プリント配線板７を
形成し、次いで最外層の表面側から外層用絶縁基材５の
内層材４の実装用凹部３に対応する部分５ａを切削して
実装用凹部３を露出させ、この後実装用凹部３に半導体
チップ２を実装することを特徴とするものであり、この
構成により上記目的を達成できたものである。[Disclosure of the Invention] The method for manufacturing a semiconductor chip carrier of the present invention includes laminating a plurality of inner layer insulating substrates 1 on which inner layer circuits are formed, and forming an inner layer material 4 having a recess 3 for mounting a semiconductor chip 2 on the front surface side. , and then a wire bonding portion 9 in the mounting recess 3 of the inner layer material 4 on the back side of the outer layer insulating substrate 5 which is the outermost layer.
A soft material 6 such as an adhesive tape is coated on a dark area 5b corresponding to the inner layer material 4, and this outer layer insulating substrate 5 is laminated on the surface of the inner layer material 4 to perform multilayer molding. A multilayer printed wiring board 7 is formed by plating and forming an outer layer, and then a portion 5a corresponding to the mounting recess 3 of the inner layer material 4 of the outer layer insulating base material 5 is cut from the surface side of the outermost layer to form a mounting recess. 3 is exposed, and then the semiconductor chip 2 is mounted in the mounting recess 3. With this configuration, the above object can be achieved.
以下、本発明を添付の図面を参照して説明する。The present invention will now be described with reference to the accompanying drawings.
多層プリント配線板７は周知のマスラミネート方式又は
ピンラミネート方式により製造される。この実施例は三
層プリント配線板である。内層用絶縁基板１は、銅箔な
どの金属箔を張った紙フエノール樹脂積層板、紙エポキ
シ樹脂積層板などの金属箔張り積層板に順次、孔明け、
無電解めっき、パターン形成、パターンめっき、レジス
トめっき、レジスト除去、エツチング、外形仕上げ、シ
ンボルマーク印刷といった常法の工程でその表面に内層
回路が形成される。内層回路を形成する前に、まず、二
枚の内層用絶縁基板１ａ、１ｂにそれぞれ実装用凹部形
成用の凹部３ａ及び貫通孔３ｂを機械的切削加工により
形成する。次いで、この二枚の内層用絶縁基板１ａ、１
ｂを接着剤、接着シートあるいはローフ０−プリブレグ
のようなボンディングシート層８を介して加熱加圧して
積層成形して表面側に半導体チップ２の実装用凹部３を
有する内層材４を形成する。−力量外層となる外層用絶
縁基板５は銅箔プリプレグのようなものであり、この外
層用絶縁基板５の裏面側で実装用凹部３の表面側のワイ
ヤボンディング部９に対応する箇所５ｂを粘着テープで
ある軟質材６で被着する。次いで、この外層用絶縁基板
５を内層材４の表面にボンディングシート層８を介して
加熱加圧して多層成形する。この後孔１３明は加工、ス
ルーホールめっ外のスルーホール工程、次いで外層エツ
チング等の外層形成工程により多層プリント配線板７を
形成する。この後最外層の表面側から機械的切削加工に
より外層用絶縁基材５の内層材４の実装用凹部３に対応
する部分５ａを切削して実装用凹部３を露出させる。こ
の場合、例えばドリルなどによる座ぐり中において外層
用絶縁基板５と軟質材６のドリルへの抵抗がかなり違う
ことから、この抵抗差を感知することにより、ワイヤボ
ンディング部９を傷付けることなく座ぐりを行うことが
できる。この後軟質材６を剥離除去する。残存した場合
は薬品で溶解除去する。この実装用凹部３には半導体チ
ップ２を搭載し、ワイヤボンディング部９にワイヤ１０
によりボンディングして内層回路と電気的に接続し、エ
ポキシ樹脂などにより樹脂封止したり、セラミック製の
カバーを被着して絶縁処理を施し、パッケージとしての
実装を完了して実用に供する。尚、この半導体チップキ
ャリアＡは、ｆＪＳ２図に示すようにスルーホール１１
に端子ビン１２を保持させることによりビングリッドア
レイとして、又スルーホール１１を接続孔として機能さ
せることによりリードレスチップキャリアとして使用で
きるものである。The multilayer printed wiring board 7 is manufactured by a well-known mass lamination method or pin lamination method. This example is a three-layer printed wiring board. The inner layer insulating substrate 1 is made by sequentially drilling holes in a metal foil-covered laminate such as a paper phenol resin laminate or a paper epoxy resin laminate covered with a metal foil such as copper foil.
Inner layer circuits are formed on the surface through conventional processes such as electroless plating, pattern formation, pattern plating, resist plating, resist removal, etching, external finishing, and symbol mark printing. Before forming the inner layer circuit, first, a recess 3a and a through hole 3b for forming a recess for mounting are respectively formed in the two inner layer insulating substrates 1a and 1b by mechanical cutting. Next, these two inner layer insulating substrates 1a, 1
The inner layer material 4 having a concave portion 3 for mounting the semiconductor chip 2 on the front side is formed by heating and pressurizing and laminating the materials b through an adhesive, an adhesive sheet, or a bonding sheet layer 8 such as a loaf 0-prereg. - Competence The outer layer insulating substrate 5, which will be the outer layer, is something like a copper foil prepreg, and on the back side of the outer layer insulating substrate 5, the portion 5b corresponding to the wire bonding part 9 on the front side of the mounting recess 3 is attached with adhesive. It is covered with a soft material 6 that is tape. Next, the outer layer insulating substrate 5 is heated and pressed onto the surface of the inner layer material 4 via the bonding sheet layer 8 to form a multilayer structure. The multilayer printed wiring board 7 is formed by processing the rear holes 13, performing a through-hole process of plating the through-holes, and then performing an outer layer forming process such as outer layer etching. Thereafter, a portion 5a corresponding to the mounting recess 3 of the inner layer material 4 of the outer layer insulating base material 5 is cut off from the surface side of the outermost layer by mechanical cutting to expose the mounting recess 3. In this case, for example, during spot boring with a drill, the resistance of the outer layer insulating substrate 5 and the soft material 6 to the drill is quite different, so by sensing this resistance difference, the spot boring can be performed without damaging the wire bonding part 9. It can be performed. After this, the soft material 6 is peeled off and removed. If any remains, dissolve and remove with chemicals. The semiconductor chip 2 is mounted in the mounting recess 3, and the wire 10 is mounted in the wire bonding part 9.
The package is then electrically connected to the inner layer circuit by bonding, and then sealed with epoxy resin or covered with a ceramic cover for insulation, completing the packaging and putting it into practical use. Note that this semiconductor chip carrier A has through holes 11 as shown in Figure fJS2.
It can be used as a bin grid array by holding the terminal bins 12, and as a leadless chip carrier by allowing the through holes 11 to function as connection holes.
［発明の効果１
本発明にあっては、半導体チップの実装用凹部を有する
内層材を形成し、次いで最外層となる外層用絶縁基板の
裏面側で内層材の実装用凹部内のワイヤボンディング部
に対応する箇所に粘着テープのような軟質材を被着し、
この外層用絶縁基板を内層材の表面に積層して多層成形
し、この後順次孔明は加工、スルーホールめっき、外層
形成を行なって多層プリント配線板を形成するので、最
外層の回路パターン形成に際して、大装用凹部が最外層
の外層用絶縁基板により保護されてめっきに汚染される
ことがなく、しがも多層プリント配線板の最外層の表面
側から外層用絶縁基材の内層材の実装用凹部に対応する
部分を切削して実装用凹部を露出させ、この後実装用凹
部に半導体チップを実装するので、切削加工に際してワ
イヤボンディング部を軟質材により保護して傷付けるこ
とがなく、半導体チップと内層材の内層回路との電気的
接続を確実なものにできる。[Effect of the invention 1 In the present invention, an inner layer material having a recess for mounting a semiconductor chip is formed, and then a wire bonding portion in the recess for mounting of the inner layer material is formed on the back side of an outer layer insulating substrate which is the outermost layer. A soft material such as adhesive tape is applied to the corresponding area,
This insulating substrate for the outer layer is laminated on the surface of the inner layer material to perform multilayer molding, and after that, the multilayer printed wiring board is formed by sequentially processing, through-hole plating, and forming the outer layer, so when forming the circuit pattern on the outermost layer, , the large mounting concave part is protected by the outermost insulating substrate for the outer layer and is not contaminated by plating, and it is possible to mount the inner layer material of the outer insulating substrate from the surface side of the outermost layer of the multilayer printed wiring board. The part corresponding to the recess is cut to expose the recess for mounting, and then the semiconductor chip is mounted in the recess for mounting, so the wire bonding part is protected by a soft material during the cutting process and is not damaged. Electrical connection between the inner layer material and the inner layer circuit can be ensured.
第１図は本発明の一実施例の工程を示す断面図、第２図
は同上への半導体チップの実装を示す断面図、第３図は
従来例を示す断面図、＄４図は本発明の完成過程で開発
された方法を示す断面図であって、Ａは半導体チップキ
ャリア、１は内層用絶縁基板、２は半導体チップ、３は
実装用凹部、４は内層材、５は外層用絶縁基板、６は軟
質材、７は多層プリント配線板、１３は孔である。Fig. 1 is a sectional view showing the process of an embodiment of the present invention, Fig. 2 is a sectional view showing mounting of a semiconductor chip on the same, Fig. 3 is a sectional view showing the conventional example, and Fig. 4 is a sectional view showing the process of the present invention. 1 is a cross-sectional view showing a method developed in the process of completing a semiconductor chip carrier, 1 is an insulating substrate for an inner layer, 2 is a semiconductor chip, 3 is a recess for mounting, 4 is an inner layer material, and 5 is an insulating layer for an outer layer. The board includes a soft material 6, a multilayer printed wiring board 7, and a hole 13.
Claims (1)
積層して表面側に半導体チップの実装用凹部を有する内
層材を形成し、次いで最外層となる外層用絶縁基板の裏
面側で内層材の実装用凹部内のワイヤボンディング部に
対応する箇所に粘着テープのような軟質材を被覆し、こ
の外層用絶縁基板を内層材の表面に積層して多層成形し
、この後順次孔明け加工、スルーホールめっき、外層形
成を行なって多層プリント配線板を形成し、次いで最外
層の表面側から外層用絶縁基材の内層材の実装用凹部に
対応する部分を切削して実装用凹部を露出させ、この後
実装用凹部に半導体チップを実装することを特徴とする
半導体チップキャリアの製造方法。(1) A plurality of inner layer insulating substrates on which inner layer circuits are formed are laminated to form an inner layer material having a recess for mounting a semiconductor chip on the front side, and then an inner layer material is formed on the back side of the outermost layer insulating substrate, which is the outermost layer. The part corresponding to the wire bonding part in the mounting recess of the inner layer material is covered with a soft material such as adhesive tape, and this insulating substrate for the outer layer is laminated on the surface of the inner layer material to perform multilayer molding. After this, holes are sequentially drilled. Processing, through-hole plating, and outer layer formation are performed to form a multilayer printed wiring board. Next, from the surface side of the outermost layer, a portion of the insulating base material for the outer layer corresponding to the mounting recess of the inner layer material is cut to form a mounting recess. A method for manufacturing a semiconductor chip carrier, comprising exposing the semiconductor chip and then mounting the semiconductor chip in a mounting recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61085418A JPS62242343A (en) | 1986-04-14 | 1986-04-14 | Manufacture of semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61085418A JPS62242343A (en) | 1986-04-14 | 1986-04-14 | Manufacture of semiconductor chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242343A true JPS62242343A (en) | 1987-10-22 |
Family
ID=13858262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61085418A Pending JPS62242343A (en) | 1986-04-14 | 1986-04-14 | Manufacture of semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242343A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255996A (en) * | 1987-04-14 | 1988-10-24 | シチズン時計株式会社 | Multilayer board for semiconductor chip mounting |
| JPH0322588A (en) * | 1989-06-20 | 1991-01-30 | Mitsubishi Materials Corp | Pinless grid array type multilayered hybrid integrated circuit |
-
1986
- 1986-04-14 JP JP61085418A patent/JPS62242343A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63255996A (en) * | 1987-04-14 | 1988-10-24 | シチズン時計株式会社 | Multilayer board for semiconductor chip mounting |
| JPH0322588A (en) * | 1989-06-20 | 1991-01-30 | Mitsubishi Materials Corp | Pinless grid array type multilayered hybrid integrated circuit |
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