JPH09321437A - Manufacture of multialyr printed wiring board - Google Patents
Manufacture of multialyr printed wiring boardInfo
- Publication number
- JPH09321437A JPH09321437A JP8129796A JP12979696A JPH09321437A JP H09321437 A JPH09321437 A JP H09321437A JP 8129796 A JP8129796 A JP 8129796A JP 12979696 A JP12979696 A JP 12979696A JP H09321437 A JPH09321437 A JP H09321437A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- lid
- hole
- conductor circuit
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体チップ等の
電子部品を搭載するための、ピングリッドアレイ(PG
A)、ボールグリッドアレイ(BGA)、チップキャリ
ア等の電子部品搭載用装置に使用される多層プリント配
線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pin grid array (PG) for mounting electronic parts such as semiconductor chips.
A), a method of manufacturing a multilayer printed wiring board used for a device for mounting electronic components such as a ball grid array (BGA) and a chip carrier.
【0002】[0002]
【従来の技術】近年、半導体チップやチップ部品等の電
子部品は軽薄短小化が進んでいる。それに伴い、電子部
品を搭載するための多層プリント配線板も高密度化され
てきている。また、半導体チップを搭載する基板として
は従来セラミック素材のものが用いられていたが、樹脂
素材のものでも銅コアを用いることにより高放熱性を実
現でき、信号速度の面からも優れていることから、樹脂
素材である有機系基板を使用した多層プリント配線板が
用いられるようになってきた。なお、半導体チップを搭
載する基板では、半導体チップを搭載するための平坦な
搭載部と、搭載する半導体チップとの接合、あるいは結
線(ボンディング)のために表面に金皮膜を有する導体
回路を備えるのが一般的である。2. Description of the Related Art In recent years, electronic parts such as semiconductor chips and chip parts have been reduced in size and weight. Along with this, the density of multilayer printed wiring boards for mounting electronic components has been increasing. Conventionally, a ceramic material was used as the substrate for mounting the semiconductor chip, but even if it is a resin material, high heat dissipation can be achieved by using a copper core, and it is also excellent in terms of signal speed. Therefore, a multilayer printed wiring board using an organic substrate which is a resin material has come to be used. The substrate on which the semiconductor chip is mounted is provided with a flat mounting portion for mounting the semiconductor chip and a conductor circuit having a gold film on the surface for joining or bonding (bonding) with the mounted semiconductor chip. Is common.
【0003】従来の、半導体チップを搭載するための多
層プリント配線板の製造方法としては、例えば特公平5
−41039号に示されるものがある。この方法を図5
及び図6を参照して説明する。電子部品搭載部3及び導
体回路5を有した最下部に使用する基板1と、この基板
1の上に配置されて上部の最外層となる基板1と、これ
ら両基板間に必要に応じて介装されて前記搭載部3に対
応する開口部13及び導体回路5を有した少なくとも1
つの中間基板1とを、接着部材4を介して加圧接着して
(図5(a)→図5(b))、上部の最外層となる基板
1を用いて電子部品搭載部3が存在する電子部品収納穴
2を保護している状態にある多層板11を得る。次い
で、加圧接着した各基板を同時に貫通するスルーホール
8を形成する(図6(c))。その後、このスルーホー
ル8にメッキを施した後、最外層となる基板1の表面に
外層回路9を形成する(図6(d))。次いで、上部の
最外層に位置する基板1に、電子部品収納穴2を外部に
通じさせる開口部13を形成する(図6(e))。As a conventional method of manufacturing a multilayer printed wiring board for mounting a semiconductor chip, for example, Japanese Patent Publication No.
There is one shown in No. 41039. This method is illustrated in FIG.
And FIG. 6 will be described. The board 1 used at the lowermost part having the electronic component mounting portion 3 and the conductor circuit 5, the board 1 which is arranged on the board 1 and serves as the outermost layer on the upper side, and an interposing between these boards as necessary. At least one that is mounted and has an opening 13 corresponding to the mounting portion 3 and a conductor circuit 5
The two intermediate substrates 1 are pressure-bonded to each other via the adhesive member 4 (FIG. 5 (a) → FIG. 5 (b)), and the electronic component mounting portion 3 is present using the substrate 1 serving as the uppermost outer layer. The multilayer board 11 in a state where the electronic component storage hole 2 is protected is obtained. Next, a through hole 8 is formed so as to simultaneously penetrate the pressure-bonded substrates (FIG. 6C). Then, after plating the through hole 8, an outer layer circuit 9 is formed on the surface of the substrate 1, which is the outermost layer (FIG. 6D). Next, the opening 13 for communicating the electronic component storage hole 2 to the outside is formed in the substrate 1 located in the uppermost outermost layer (FIG. 6E).
【0004】以上が特公平5−41039号に示されて
いる製造方法の概要である。しかし、この製造方法で
は、最外層となる基板1を用いて電子部品収納穴2を保
護していることから、電子部品収納穴2を外部に通じさ
せる開口部13を形成するためには、ルータ等で最外層
の基板1を切削加工する必要がある。この切削加工に伴
って、発生した樹脂屑等が電子部品収納穴2の内部に付
着する。電子部品収納穴2内に露出した導体回路5はワ
イヤーボンディングを行う部位であることから、導体回
路5の上にニッケルメッキや金メッキが施されるのが一
般的であり、この導体回路5上に樹脂屑等が付着する
と、製品の品質に重大な影響を与える。なお、樹脂屑等
の除去を高圧水洗等を用いて行っても、完全に除去する
ことは困難である。また、ルータ等で最外層の基板1を
切削加工する際に、下方にある導体回路5を切断するの
を防止するために、最外層の基板1の切削加工を施す位
置にザグリ加工により溝14を形成しておくことが行わ
れるが(図5(a)参照)、この溝14を形成するに
は、最外層の基板1の厚みを厚くする必要があり、その
ため多層板全体の厚みが厚くなるという問題もあった。The above is the outline of the manufacturing method disclosed in Japanese Patent Publication No. 5-41039. However, in this manufacturing method, since the electronic component storage hole 2 is protected by using the substrate 1 which is the outermost layer, in order to form the opening 13 for communicating the electronic component storage hole 2 to the outside, the router is required. It is necessary to cut the outermost substrate 1 by using the above method. Along with this cutting process, resin scraps and the like generated adhere to the inside of the electronic component housing hole 2. Since the conductor circuit 5 exposed in the electronic component housing hole 2 is a portion for wire bonding, it is common that the conductor circuit 5 is nickel-plated or gold-plated. Adhesion of resin scraps or the like seriously affects the quality of the product. It should be noted that it is difficult to completely remove the resin debris even if the resin debris or the like is removed using high-pressure water washing or the like. Further, when the outermost substrate 1 is cut by a router or the like, in order to prevent the conductor circuit 5 located therebelow from being cut, a groove 14 is formed at the position where the outermost substrate 1 is cut by a counterbore process. However, it is necessary to increase the thickness of the outermost substrate 1 in order to form the groove 14, and therefore the total thickness of the multilayer board is increased. There was also the problem of becoming.
【0005】[0005]
【発明が解決しようとする課題】本発明は上記のような
事情に鑑みてなされたものであって、その目的とすると
ころは、導体回路が露出している電子部品収納穴と、こ
の電子部品収納部以外の箇所にメッキが施されたスルー
ホールを有する多層プリント配線板の製造方法であっ
て、電子部品収納穴を開口する際に、樹脂屑等の発生が
なく、電子部品収納穴内の導体回路が汚染されることの
ない多層プリント配線板の製造方法を提供することにあ
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic component housing hole in which a conductor circuit is exposed, and this electronic component. A method for manufacturing a multilayer printed wiring board having a plated through hole in a place other than a storage part, wherein no resin scraps are generated when the electronic part storage hole is opened, and a conductor in the electronic part storage hole It is an object of the present invention to provide a method for manufacturing a multilayer printed wiring board in which a circuit is not contaminated.
【0006】[0006]
【課題を解決するための手段】請求項1に係る発明の多
層プリント配線板の製造方法は、次の各工程からなる多
層プリント配線板の製造方法である。 (1)導体回路を形成している複数枚の基板を、導体回
路が露出している電子部品収納穴を所定の位置に形成し
ながら積層、加圧接着して電子部品収納穴を有する積層
体を形成する工程; (2)前記電子部品収納穴の開口端面を覆う蓋体と、こ
の蓋体の外周を包囲する、蓋体より大きい開口部を有す
る接着部材を前記積層体の表面に配し、さらに、蓋体と
接着部材を覆うように導電材を配して積層し、次いで、
加圧接着して導電材で被覆された多層板を形成する工
程; (3)蓋体が存在する位置以外の個所にスルーホールを
形成し、このスルーホールにメッキを施す工程; (4)多層板の表面に外層回路を形成する工程; (5)蓋体を多層板から除去する工程; (6)電子部品収納穴内の導体回路にメッキを施す工
程。A method for manufacturing a multilayer printed wiring board according to a first aspect of the present invention is a method for manufacturing a multilayer printed wiring board comprising the following steps. (1) A laminated body having a plurality of substrates forming a conductor circuit, which are stacked and pressure-bonded while forming an electronic component storage hole in which the conductor circuit is exposed at a predetermined position, and having an electronic component storage hole (2) A lid that covers the opening end face of the electronic component storage hole and an adhesive member that surrounds the outer periphery of the lid and that has an opening that is larger than the lid are arranged on the surface of the laminate. , Furthermore, a conductive material is arranged and laminated so as to cover the lid and the adhesive member, and then,
(3) A step of forming a through hole at a position other than the position where the lid is present and plating the through hole; (4) Multilayer A step of forming an outer layer circuit on the surface of the board; (5) a step of removing the lid body from the multilayer board; (6) a step of plating the conductor circuit in the electronic component housing hole.
【0007】請求項2に係る発明の多層プリント配線板
の製造方法は、前記(2)の工程において、蓋体を積層
体の表面に配する前に、電子部品収納穴の開口端面の周
囲の、蓋体と接する部分の積層体の表面に、剥離性を有
するマスキング材を用いて剥離層を形成することを特徴
とする。According to a second aspect of the present invention, in the method of manufacturing a multilayer printed wiring board according to the second aspect, in the step (2), before arranging the lid body on the surface of the laminated body, the periphery of the opening end face of the electronic component storage hole is covered. It is characterized in that a peeling layer is formed on the surface of the laminated body in contact with the lid body by using a masking material having peelability.
【0008】[0008]
【発明の実施の形態】以下、本発明の実施の形態を図1
〜図4を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG.
This will be described with reference to FIGS.
【0009】図1(a)及び図1(b)に示すように、
導体回路5を形成した複数枚の基板1を底面が平坦であ
って、導体回路5が露出している凹状の電子部品収納穴
2を所定の位置に形成しながら積層する。導体回路5を
形成する基板1としては、エポキシ樹脂ガラス布基材銅
張積層板、ポリイミド樹脂ガラス布基材銅張積層板等が
用いられる。各基板1を接着するための接着部材4とし
ては、エポキシ樹脂系フィルム、ポリイミド樹脂系フィ
ルム、エポキシ樹脂ガラス布基材プリプレグ、ポリイミ
ド樹脂ガラス布基材プリプレグ等が用いられる。導体回
路5を形成した複数枚の基板1を積層、加圧接着して電
子部品収納穴2を有する積層体10を形成するが、図1
(b)に示すように、導体回路5を備えていない基板1
を最上部に積層するようにしても差し支えない。そし
て、この実施の形態では、最下部の基板1の外面側には
銅箔等よりなる導電材6を備えている。As shown in FIGS. 1 (a) and 1 (b),
A plurality of substrates 1 on which the conductor circuits 5 are formed are stacked while forming a concave electronic component housing hole 2 having a flat bottom surface and exposing the conductor circuits 5 at a predetermined position. As the substrate 1 for forming the conductor circuit 5, an epoxy resin glass cloth base material copper clad laminate, a polyimide resin glass cloth base material copper clad laminate, or the like is used. As the bonding member 4 for bonding the substrates 1, an epoxy resin film, a polyimide resin film, an epoxy resin glass cloth base prepreg, a polyimide resin glass cloth base prepreg, or the like is used. A plurality of substrates 1 on which conductor circuits 5 are formed are stacked and pressure-bonded to form a laminated body 10 having an electronic component housing hole 2.
As shown in (b), the substrate 1 not provided with the conductor circuit 5
May be laminated on the top. Further, in this embodiment, the conductive material 6 made of copper foil or the like is provided on the outer surface side of the lowermost substrate 1.
【0010】次いで、電子部品収納穴2の開口端面を覆
う蓋体7と、この蓋体7の外周を包囲する、蓋体7より
大きい開口部を有する接着部材4を前記積層体10の表
面に配し、さらに、蓋体7と接着部材4を覆うように銅
箔等の金属箔よりなる導電材6を図1(c)に示すよう
に配して積層し、次いで、加圧接着して図2(d)に示
すように導電材6で被覆された多層板11を形成する。
蓋体7は電子部品収納穴2の開口端面を塞ぐことができ
る大きさの基板であればよく、材質については制限はな
く、例えば各種積層板を使用することができる。また、
蓋体7の外周を包囲する接着部材4としては、エポキシ
樹脂系フィルム、ポリイミド樹脂系フィルム、エポキシ
樹脂ガラス布基材プリプレグ、ポリイミド樹脂ガラス布
基材プリプレグ等が用いられ、厚みは蓋体7の厚みとほ
ぼ同じ厚みであることが望ましい。なお、この実施の形
態は電子部品収納穴2の開口端面は積層体10の一方の
表面にのみ存在する場合であるが、電子部品搭載部とし
て銅コア等の多層プリント配線板に付設する基板を使用
する場合には、電子部品収納穴2の底面側にも開口部を
形成し、この底面側の開口端面に対しても同様な処理を
施して多層プリント配線板を製造することが可能であ
る。Next, a lid 7 for covering the opening end face of the electronic component housing hole 2 and an adhesive member 4 surrounding the outer periphery of the lid 7 and having an opening larger than the lid 7 are provided on the surface of the laminate 10. Then, a conductive material 6 made of a metal foil such as a copper foil is arranged so as to cover the lid 7 and the adhesive member 4 as shown in FIG. 1C, and laminated, and then pressure-bonded. As shown in FIG. 2D, the multi-layer plate 11 covered with the conductive material 6 is formed.
The lid 7 may be any substrate as long as it has a size capable of closing the opening end face of the electronic component housing hole 2, and the material is not limited, and various laminated plates can be used, for example. Also,
An epoxy resin film, a polyimide resin film, an epoxy resin glass cloth base material prepreg, a polyimide resin glass cloth base material prepreg, or the like is used as the adhesive member 4 that surrounds the outer periphery of the cover body 7. It is desirable that the thickness be almost the same as the thickness. In this embodiment, the opening end face of the electronic component housing hole 2 is present only on one surface of the laminated body 10. However, a substrate attached to a multilayer printed wiring board such as a copper core is mounted as an electronic component mounting portion. When used, it is possible to form an opening also on the bottom surface side of the electronic component housing hole 2 and perform similar processing on the opening end surface on the bottom surface side to manufacture a multilayer printed wiring board. .
【0011】次いで、多層板11の蓋体6が存在する位
置以外の個所にスルーホール8を形成し(図2
(e))、このスルーホール8にメッキを施す(図示せ
ず)。Next, through holes 8 are formed in the multilayer plate 11 at positions other than the position where the lid 6 is present (see FIG. 2).
(E)) The through holes 8 are plated (not shown).
【0012】次いで、多層板11の表面にレジスト塗
布、露光、現像、エッチングを行うことにより、多層板
11の表面に外層回路9を形成する(図2(f))。こ
の外層回路9を形成する工程で、蓋体7の上の導電材6
をエッチングで除いておくと、次の工程での蓋体7の除
去が容易にできるので好ましい。Next, resist coating, exposure, development and etching are performed on the surface of the multilayer board 11 to form the outer layer circuit 9 on the surface of the multilayer board 11 (FIG. 2 (f)). In the step of forming the outer layer circuit 9, the conductive material 6 on the lid 7 is formed.
Is preferably removed by etching because the lid 7 can be easily removed in the next step.
【0013】次いで、蓋体7を多層板11から除去し
て、電子部品収納穴2を外部に通じさせる(図3)。次
いで、電子部品収納穴2内の導体回路5にメッキを施し
てニッケルメッキや金メッキの層を形成する。Next, the lid 7 is removed from the multi-layer plate 11 and the electronic component storage hole 2 is communicated with the outside (FIG. 3). Next, the conductor circuit 5 in the electronic component housing hole 2 is plated to form a nickel-plated or gold-plated layer.
【0014】この実施の形態では、着脱可能な蓋体7を
用いて電子部品収納穴2を保護していることから、電子
部品収納穴2を外部に通じさせる開口部を形成するの
に、ルータ等で最外層の基板を切削加工する必要がない
ので、樹脂屑等の発生がなく、従って電子部品収納穴2
内に露出した導体回路5が汚染されることがない。ま
た、ルータ等で最外層の基板を切削加工する必要がない
ので、最外層の基板にザグリ加工により溝を形成してお
くことも必要がなく、最外層の基板の厚みを特別に厚く
する必要もない。そのため多層板全体の厚みを薄くする
ことが可能となる。In this embodiment, since the electronic component storage hole 2 is protected by using the detachable lid 7, the router is used to form the opening for communicating the electronic component storage hole 2 to the outside. Since it is not necessary to cut the outermost layer substrate by means such as resin, there is no generation of resin scraps, and therefore the electronic component storage hole 2
The conductor circuit 5 exposed inside is not contaminated. Also, since it is not necessary to cut the outermost layer substrate with a router, it is not necessary to form a groove in the outermost layer substrate by counterboring, and it is necessary to increase the thickness of the outermost layer substrate particularly. Nor. Therefore, it is possible to reduce the thickness of the entire multilayer board.
【0015】また、上記した実施の形態において、電子
部品収納穴2の開口端面を覆う蓋体7を積層体10の表
面に配する前に、図4に示すように電子部品収納穴2の
開口端面の周囲の、蓋体7と接する部分の積層体10の
表面に、剥離性を有するマスキング材を印刷、半硬化さ
せて剥離層12を形成しておくと、蓋体4と積層体10
の間の間隙が剥離層12で確実に塞がれるので、外層回
路を形成する工程で、蓋体8の上の導電材6をエッチン
グで除く際に、エッチング液が電子部品収納穴2内に侵
入するのを防止できるようになり、望ましい。なお、こ
の剥離層12を形成する材質については、特に限定はな
く、最終的には積層体10から分離・除去できて、蓋体
7と積層体10の間の間隙を塞ぐことができる材質であ
ればよい。Further, in the above-described embodiment, before placing the lid 7 covering the opening end face of the electronic component storage hole 2 on the surface of the laminated body 10, as shown in FIG. 4, the opening of the electronic component storage hole 2 is performed. When the peeling layer 12 is formed by printing and semi-curing a masking material having releasability on the surface of the laminated body 10 around the end face and in contact with the lid body 7, the lid body 4 and the laminated body 10 are formed.
Since the gap between the layers is surely closed by the peeling layer 12, when the conductive material 6 on the lid 8 is removed by etching in the step of forming the outer layer circuit, the etching liquid enters the electronic component storage hole 2. It is desirable because it can prevent intrusion. The material for forming the peeling layer 12 is not particularly limited, and is a material that can be finally separated / removed from the laminated body 10 to close the gap between the lid body 7 and the laminated body 10. I wish I had it.
【0016】[0016]
【発明の効果】請求項1及び請求項2に係る発明の多層
プリント配線板の製造方法では、スルーホールにメッキ
を施す際に、着脱可能な蓋体を用いて電子部品収納穴を
保護するようにしている。従って、請求項1及び請求項
2に係る発明の多層プリント配線板の製造方法によれ
ば、スルーホールにメッキを施した後で、電子部品収納
穴を外部に通じさせる開口部を形成するのに、ルータ等
で最外層の基板を切削加工する必要がないので、樹脂屑
等の発生がなく、電子部品収納穴内の導体回路が汚染さ
れるという問題が生じない。従って、品質の安定した多
層プリント配線板を製造することが可能となる。In the method for manufacturing a multilayer printed wiring board according to the first and second aspects of the present invention, when the through hole is plated, the removable lid is used to protect the electronic component storage hole. I have to. Therefore, according to the method for manufacturing a multilayer printed wiring board of the present invention according to claim 1 and claim 2, after the through hole is plated, an opening for communicating the electronic component accommodating hole to the outside can be formed. Since it is not necessary to cut the outermost substrate with a router or the like, resin scraps and the like are not generated and the problem that the conductor circuit in the electronic component housing hole is contaminated does not occur. Therefore, it becomes possible to manufacture a multilayer printed wiring board with stable quality.
【図1】本発明の多層プリント配線板の製造方法の工程
をモデル的に説明する断面図である。FIG. 1 is a cross-sectional view schematically illustrating a process of a method for manufacturing a multilayer printed wiring board according to the present invention.
【図2】図1に続く工程をモデル的に説明する断面図で
ある。FIG. 2 is a cross-sectional view illustrating a process following FIG. 1 as a model.
【図3】図2に続く工程をモデル的に説明する断面図で
ある。FIG. 3 is a cross-sectional view schematically illustrating a process following FIG. 2;
【図4】請求項2に係る発明の多層プリント配線板の製
造方法の工程の一部をモデル的に説明する断面図であ
る。FIG. 4 is a cross-sectional view for explaining, as a model, part of the steps of the method for manufacturing a multilayer printed wiring board according to the second aspect of the invention.
【図5】従来の多層プリント配線板の製造方法の工程を
モデル的に説明する断面図である。FIG. 5 is a cross-sectional view schematically illustrating a process of a conventional method for manufacturing a multilayer printed wiring board.
【図6】従来の多層プリント配線板の製造方法の工程
の、図5に続く工程をモデル的に説明する断面図であ
る。FIG. 6 is a cross-sectional view schematically illustrating a step following FIG. 5 of the step of the conventional method for manufacturing a multilayer printed wiring board.
1 基板 2 電子部品収納穴 3 電子部品搭載部 4 接着部材 5 導体回路 6 導電材 7 蓋体 8 スルーホール 9 外層回路 10 積層体 11 多層板 12 剥離層 13 開口部 1 Substrate 2 Electronic Component Storage Hole 3 Electronic Component Mounting Portion 4 Adhesive Member 5 Conductor Circuit 6 Conductive Material 7 Lid Body 8 Through Hole 9 Outer Layer Circuit 10 Laminated Body 11 Multilayer Board 12 Release Layer 13 Opening
───────────────────────────────────────────────────── フロントページの続き (72)発明者 金谷 大介 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 石川 正治 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 兼子 醇治 大阪府門真市大字門真1048番地松下電工株 式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Daisuke Kanaya 1048, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works Co., Ltd. (72) Shoji Ishikawa, 1048, Kadoma, Kadoma City, Osaka Matsushita Electric Works Co. 72) Inventor Kaneko Daiji Matsuda Electric Works Co., Ltd. 1048 Kadoma, Kadoma, Osaka Prefecture
Claims (2)
の製造方法。 (1)導体回路を形成している複数枚の基板を、導体回
路が露出している電子部品収納穴を所定の位置に形成し
ながら積層、加圧接着して電子部品収納穴を有する積層
体を形成する工程; (2)前記電子部品収納穴の開口端面を覆う蓋体と、こ
の蓋体の外周を包囲する、蓋体より大きい開口部を有す
る接着部材を前記積層体の表面に配し、さらに、蓋体と
接着部材を覆うように導電材を配して積層し、次いで、
加圧接着して導電材で被覆された多層板を形成する工
程; (3)蓋体が存在する位置以外の個所にスルーホールを
形成し、このスルーホールにメッキを施す工程; (4)多層板の表面に外層回路を形成する工程; (5)蓋体を多層板から除去する工程; (6)電子部品収納穴内の導体回路にメッキを施す工
程。1. A method for manufacturing a multilayer printed wiring board comprising the following steps. (1) A laminated body having a plurality of substrates forming a conductor circuit, which are stacked and pressure-bonded while forming an electronic component storage hole in which the conductor circuit is exposed at a predetermined position, and having an electronic component storage hole (2) A lid that covers the opening end face of the electronic component storage hole and an adhesive member that surrounds the outer periphery of the lid and that has an opening that is larger than the lid are arranged on the surface of the laminate. , Furthermore, a conductive material is arranged and laminated so as to cover the lid and the adhesive member, and then,
(3) A step of forming a through hole at a position other than the position where the lid is present and plating the through hole; (4) Multilayer A step of forming an outer layer circuit on the surface of the board; (5) a step of removing the lid body from the multilayer board; (6) a step of plating the conductor circuit in the electronic component housing hole.
体の表面に配する前に、電子部品収納穴の開口端面の周
囲の、蓋体と接する部分の積層体の表面に、剥離性を有
するマスキング材を用いて剥離層を形成することを特徴
とする請求項1記載の多層プリント配線板の製造方法。2. In the step (2), before arranging the lid on the surface of the laminated body, peeling is performed on the surface of the laminated body around the opening end surface of the electronic component storage hole and in contact with the lid. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the release layer is formed using a masking material having properties.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8129796A JPH09321437A (en) | 1996-05-24 | 1996-05-24 | Manufacture of multialyr printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8129796A JPH09321437A (en) | 1996-05-24 | 1996-05-24 | Manufacture of multialyr printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09321437A true JPH09321437A (en) | 1997-12-12 |
Family
ID=15018449
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8129796A Pending JPH09321437A (en) | 1996-05-24 | 1996-05-24 | Manufacture of multialyr printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09321437A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114531793A (en) * | 2022-02-25 | 2022-05-24 | 黄石西普电子科技有限公司 | Manufacturing method of eight-layer HDI board combining softness and hardness |
-
1996
- 1996-05-24 JP JP8129796A patent/JPH09321437A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114531793A (en) * | 2022-02-25 | 2022-05-24 | 黄石西普电子科技有限公司 | Manufacturing method of eight-layer HDI board combining softness and hardness |
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