JPH0799215A - Semiconductor mounting structure - Google Patents
Semiconductor mounting structureInfo
- Publication number
- JPH0799215A JPH0799215A JP24240493A JP24240493A JPH0799215A JP H0799215 A JPH0799215 A JP H0799215A JP 24240493 A JP24240493 A JP 24240493A JP 24240493 A JP24240493 A JP 24240493A JP H0799215 A JPH0799215 A JP H0799215A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- flexible wiring
- mounting structure
- conductor foil
- flip chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体実装構造に関し、
特に半導体チップをフレキシブル配線板にフェイスダウ
ンボンディングする半導体実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor packaging structure,
In particular, it relates to a semiconductor mounting structure for face down bonding a semiconductor chip to a flexible wiring board.
【０００２】[0002]
【従来の技術】従来の技術について図３乃至図５を参照
して説明する。図３は従来例によるチップ実装構造を示
す断面図、図４は他の従来例によるチップ実装構造を示
す断面図、図５はさらに他の従来例によるチップ実装構
造を示す断面図である。図３乃至図５において、同一機
能部分には同一記号を付している。2. Description of the Related Art A conventional technique will be described with reference to FIGS. 3 is a sectional view showing a chip mounting structure according to a conventional example, FIG. 4 is a sectional view showing a chip mounting structure according to another conventional example, and FIG. 5 is a sectional view showing a chip mounting structure according to yet another conventional example. 3 to 5, the same functional parts are designated by the same reference numerals.
【０００３】従来、柔軟材料の両面導体配線板、例えば
フレキシブル配線板にベアチップＩＣを実装する場合、
図３に示すように、フレキシブル配線板２０上の導体箔
２１に対して、フリップチップＩＣ２２を回路面がフェ
ースアップの状態となるようにして搭載し、フリップチ
ップＩＣ２２のアルミ電極とフレキシブル配線板２０の
接合パッド２３とを金ワイヤー２４でワイヤーボンディ
ングしていた。ここで、フレキシブル配線板２０の基材
ベース２５と導体箔２１との間には接着剤層２６が介挿
されている。また、２７はカバーレイ、２８は封止樹脂
である。Conventionally, when a bare chip IC is mounted on a double-sided conductor wiring board made of a flexible material, for example, a flexible wiring board,
As shown in FIG. 3, the flip chip IC 22 is mounted on the conductor foil 21 on the flexible wiring board 20 so that the circuit surface is in a face-up state, and the aluminum electrode of the flip chip IC 22 and the flexible wiring board 20 are mounted. The bonding pad 23 of the above was wire-bonded with the gold wire 24. Here, the adhesive layer 26 is interposed between the base material base 25 of the flexible wiring board 20 and the conductor foil 21. Further, 27 is a coverlay and 28 is a sealing resin.
【０００４】また他の従来例として、図４に示すよう
に、フリップチップＩＣ２２の電極にハンダバンプ２９
を形成し、このハンダバンプ２９によって、フレキシブ
ル配線板２０に対してリフローによりハンダ付けするも
のもあった。As another conventional example, as shown in FIG. 4, solder bumps 29 are formed on the electrodes of the flip chip IC 22.
In some cases, the solder bumps 29 are used to solder the flexible wiring board 20 by reflow.
【０００５】図５の従来例は図４の従来例と同様、ワイ
ヤーボンディングを用いない構造であるが、図４のハン
ダバンプ２９に代えて金バンプ３０を用い、接合の際も
リフローではなく、加熱しつつ荷重を加えて接合する点
が異なっている。The conventional example shown in FIG. 5 is similar to the conventional example shown in FIG. 4 in that the wire bonding is not used, but gold bumps 30 are used in place of the solder bumps 29 shown in FIG. However, the point that they are joined by applying a load is different.
【０００６】[0006]
【発明が解決しようとする課題】ところで、上記図３に
示す従来例の場合、ワイヤーボンディングする際に、金
ワイヤー２４を一本ずつボンディングする時間が必要で
あるので、接合に時間がかかっていた。また、図４に示
す従来例の場合、ハンダバンプ接合する場合にフラック
スを使用しなければならず、接合した後はフラックスを
洗浄する必要があり手間を要していた。By the way, in the case of the conventional example shown in FIG. 3, since it is necessary to bond the gold wires 24 one by one, the bonding takes time. . Further, in the case of the conventional example shown in FIG. 4, a flux has to be used for solder bump bonding, and it is necessary to wash the flux after bonding, which is troublesome.
【０００７】図５の従来例の場合、図４の従来例のよう
にハンダ付けをするものではないので、フラックス洗浄
が不要であるというメリットがあるが、基材ベース２５
と導体箔２１との間に接着剤層２６を介挿しているの
で、基材ベースハンダ付けの際に金バンプ３０に荷重を
加えて接合しようとすると、導体箔２１が接着剤層２６
に沈み込み、フリップチップＩＣ２２のエッジと導体箔
２１とが、Ａ部に示すように接触してしまうという問題
があった。The conventional example shown in FIG. 5 does not require soldering unlike the conventional example shown in FIG. 4, so that there is an advantage that flux cleaning is unnecessary.
Since the adhesive layer 26 is interposed between the conductor foil 21 and the conductor foil 21, the conductor foil 21 will not be bonded to the adhesive layer 26 when a load is applied to the gold bumps 30 when soldering the base material base.
There is a problem in that the edge of the flip chip IC 22 and the conductor foil 21 come into contact with each other as shown in the section A.
【０００８】そこで本発明の目的は、ワイヤーボンディ
ングやフラックス洗浄の必要性がない金バンプ接合を行
い、しかも、フリップチップＩＣの接合時にフリップチ
ップＩＣのエッジと導体箔が接触するという問題もない
高信頼性の半導体実装構造を提供することにある。Therefore, an object of the present invention is to perform gold bump bonding without the need for wire bonding or flux cleaning, and there is no problem that the edge of the flip chip IC and the conductor foil come into contact when the flip chip IC is bonded. It is to provide a reliable semiconductor mounting structure.
【０００９】[0009]
【課題を解決するための手段】前記目的を達成するため
に本発明は、樹脂材料からなる基材ベースの表面に直接
導体箔を形成したフレキシブル配線板に、金バンプを介
して半導体チップＩＣを搭載、接合してなることを特徴
とする。In order to achieve the above object, the present invention provides a flexible wiring board having a conductive foil directly formed on the surface of a base material made of a resin material, and a semiconductor chip IC via a gold bump. It is characterized by being mounted and joined.
【００１０】[0010]
【作用】金バンプを使用した接合であるので、ワイヤー
ボンディングを使用せず、ワイヤーを一本ずつ接続する
必要がなく一度に全電極を接合でき、製造工程が簡易で
ある。また、金バンプ接合は、加圧、加熱によって接合
するものであるので、ハンダバンプのようにフラックス
洗浄を必要とせず、さらに製造工程の簡略化、製造コス
トの低減を図れる。[Operation] Since the bonding is performed using gold bumps, all electrodes can be bonded at one time without using wire bonding, and it is not necessary to connect wires one by one, and the manufacturing process is simple. In addition, since gold bump bonding is performed by applying pressure and heat, flux washing is not required unlike solder bumps, and the manufacturing process can be further simplified and the manufacturing cost can be reduced.
【００１１】本発明は、以上のような利点を有する金バ
ンプ接合を行うものであって、しかも、基材ベースの表
面に導体箔を直接形成している構成であるので、フリッ
プチップＩＣ接合時の荷重によって導体箔が接着剤層に
沈むことがなく、従来のようにフリップチップＩＣのエ
ッジが導体箔に接触するという問題も発生せず、高信頼
性を保証できる。According to the present invention, the gold bump bonding having the above advantages is carried out, and the conductor foil is directly formed on the surface of the base material. The conductor foil does not sink into the adhesive layer due to the load, and the problem that the edge of the flip chip IC contacts the conductor foil as in the conventional case does not occur, and high reliability can be guaranteed.
【００１２】[0012]
【実施例】本発明の一実施例について図１を参照して説
明する。図１は本実施例によるチップ実装構造を示す断
面図である。図３乃至図５に示す従来例と同一機能部分
には同一記号を付している。ここでは主に、従来例と異
なる点について説明する。本実施例の特徴は、フリップ
チップＩＣを搭載する配線板として、接着剤層の無いフ
レキシブル配線板を使用した点にある。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional view showing a chip mounting structure according to this embodiment. The same functional parts as those in the conventional example shown in FIGS. 3 to 5 are designated by the same symbols. Here, differences from the conventional example will be mainly described. The feature of this embodiment is that a flexible wiring board having no adhesive layer is used as the wiring board on which the flip chip IC is mounted.
【００１３】即ち、図１に示すように、フレキシブル配
線板１の基材ベース２上には導体箔３が直接形成されて
いる。このフレキシブル配線板１は銅箔あるいはアルミ
ニウム箔に液状のポリイミド樹脂あるいはポリエステル
樹脂をコーティングして硬化させたものや、ポリイミド
樹脂あるいはポリエステル樹脂に銅あるいはアルミニウ
ムを蒸着もしくはスパッタリングしてメッキしたものを
用いる。That is, as shown in FIG. 1, the conductor foil 3 is directly formed on the base material base 2 of the flexible wiring board 1. As the flexible wiring board 1, a copper foil or an aluminum foil coated with a liquid polyimide resin or polyester resin and cured, or a polyimide resin or a polyester resin plated with copper or aluminum by vapor deposition or sputtering is used.
【００１４】このフレキシブル配線板１の基材ベース２
の厚みは８〜７５μｍで、導体箔３の厚みは８〜４０μ
ｍが適当である。前記導体箔のメッキは、ニッケル・金
の場合、ニッケル０．１〜７μｍの上にさらに金０．０
１〜５μｍをメッキする。ニッケルをメッキしない場合
は金を厚めにする。なお、錫メッキの場合は０．０５〜
１０μｍ程度のメッキが適当である。Base material base 2 of this flexible wiring board 1
Has a thickness of 8 to 75 μm, and the conductor foil 3 has a thickness of 8 to 40 μm.
m is suitable. In the case of nickel / gold, the conductor foil may be plated with nickel 0.0 to 7 μm and gold 0.0
Plate 1-5 μm. Gold is thicker when nickel is not plated. In the case of tin plating, 0.05-
A plating of about 10 μm is suitable.
【００１５】上記のように、表面に直接導体箔３が形成
されたフレキシブル配線板１に金バンプ４付きのフリッ
プチップＩＣ５を搭載し、加熱と加圧によって接合す
る。図中、６は配線板の表裏を電気的に接続するスルー
ホールである。As described above, the flip chip IC 5 with the gold bumps 4 is mounted on the flexible wiring board 1 having the conductor foil 3 directly formed on the surface thereof and bonded by heating and pressing. In the figure, 6 is a through hole for electrically connecting the front and back of the wiring board.
【００１６】上記した実施例によれば、複数の金バンプ
４とフレキシブル配線板１を１度に接合するため、従来
のように金ワイヤーを用いて一本ずつワイヤーボンディ
ングするよりも遥かに時間を短縮でき、金ワイヤーが不
要な分、ＩＣ実装領域も小さくできる。According to the above-described embodiment, since the plurality of gold bumps 4 and the flexible wiring board 1 are bonded at once, it takes much longer time than the conventional wire bonding using gold wires one by one. It can be shortened, and the IC mounting area can be made smaller because gold wires are unnecessary.
【００１７】また、フレキシブル配線板１には接着剤層
がないため、チップ接合時に荷重が加わっても導体箔が
沈み込んでＩＣエッジと導体箔が接触するという従来の
問題は生じない。Since the flexible wiring board 1 does not have an adhesive layer, the conventional problem that the conductor foil sinks and the IC edge and the conductor foil contact each other does not occur even when a load is applied during chip bonding.
【００１８】さらに、ハンダバンプを用いないのでフラ
ックスを使用せず、接合後のフラックスの洗浄を必要と
しなくなり、製造工程が短縮されコストダウンを図れ
る。Further, since solder bumps are not used, no flux is used, and cleaning of the flux after joining is not required, and the manufacturing process can be shortened and the cost can be reduced.
【００１９】図２は本発明の他の実施例によるチップ実
装構造の断面図である。図１の実施例と略同一である
が、異なる点は、フレキシブル配線板６の裏面の内、チ
ップ実装部に相当する箇所の導体箔を除去した点であ
る。FIG. 2 is a sectional view of a chip mounting structure according to another embodiment of the present invention. Although it is substantially the same as the embodiment of FIG. 1, the difference is that the conductor foil is removed from the back surface of the flexible wiring board 6 at a portion corresponding to the chip mounting portion.
【００２０】このように導体箔を除去しておけば、図１
の実施例の効果に加え、チップ実装部のフレキシブル配
線板６全体の厚みが薄く、しかも透光性が向上すること
から、フリップチップＩＣ５として例えばＥＰＲＯＭを
搭載した場合であれば、裏面側より紫外線を照射するこ
とによって、ＥＰＲＯＭの書き込み内容の消去ができ
る。また、配線板裏面よりフリップチップＩＣ５の外観
を観察できるというメリットもある。If the conductor foil is removed in this way, FIG.
In addition to the effects of the embodiment described above, the total thickness of the flexible wiring board 6 in the chip mounting portion is thin and the translucency is improved. By irradiating with, the contents written in the EPROM can be erased. There is also a merit that the appearance of the flip chip IC 5 can be observed from the back surface of the wiring board.
【００２１】なお、上記図１及び図２の実施例はいづれ
も、基材ベースの表裏両面に導体箔を形成した３層構造
を取り上げて説明したが、例えば基材ベースの一面のみ
に導体箔を形成した２層構造であってもよい。In each of the embodiments shown in FIGS. 1 and 2, the three-layer structure in which the conductor foils are formed on both front and back surfaces of the base material base has been described, but for example, the conductor foil is formed on only one surface of the base material base. It may have a two-layer structure in which
【００２２】この場合も、上記実施例と同様、実装工程
の時間を短縮でき、ＩＣ実装領域も小さくできる。ま
た、チップ接合時に導体箔が沈み込んでＩＣエッジと導
体箔が接触するという問題は生じない。さらに、接合後
のフラックスの洗浄が不要なので、製造工程が短縮され
コストダウンを図れる。しかも、図２の実施例と同様、
ＥＰＲＯＭ等の書き込み内容の消去、外観検査を容易に
行える。Also in this case, as in the above embodiment, the time for the mounting process can be shortened and the IC mounting area can be reduced. Further, there is no problem that the conductor foil sinks at the time of chip bonding and the IC edge and the conductor foil contact each other. Further, since it is not necessary to wash the flux after joining, the manufacturing process can be shortened and the cost can be reduced. Moreover, as in the embodiment of FIG.
It is possible to easily erase the written contents of the EPROM or the like, and easily perform the visual inspection.
【００２３】[0023]
【発明の効果】以上のように、本発明によれば、ワイヤ
ーボンディングやフラックス洗浄の必要性がない金バン
プ接合を用いて、しかも、フリップチップＩＣの接合時
にフリップチップＩＣのエッジと導体箔が接触するとい
う従来の問題を解消できる高信頼性の半導体実装構造を
提供できる。As described above, according to the present invention, gold bump bonding, which does not require wire bonding or flux cleaning, is used, and the edge of the flip chip IC and the conductor foil are bonded together when the flip chip IC is bonded. It is possible to provide a highly reliable semiconductor packaging structure that can solve the conventional problem of contact.
【図１】本発明の一実施例によるチップ実装構造の断面
図である。FIG. 1 is a sectional view of a chip mounting structure according to an embodiment of the present invention.
【図２】本発明の他の実施例によるチップ実装構造の断
面図である。FIG. 2 is a cross-sectional view of a chip mounting structure according to another embodiment of the present invention.
【図３】従来例によるチップ実装構造の断面図である。FIG. 3 is a sectional view of a conventional chip mounting structure.
【図４】他の従来例によるチップ実装構造の断面図であ
る。FIG. 4 is a cross-sectional view of a chip mounting structure according to another conventional example.
【図５】さらに他の従来例によるチップ実装構造の断面
図である。FIG. 5 is a sectional view of a chip mounting structure according to still another conventional example.
１ フレキシブル配線板 ２ 基材ベース ３ 導体箔 ４ 金バンプ ５ フリップチップＩＣ 1 flexible wiring board 2 base material 3 conductor foil 4 gold bump 5 flip chip IC
Claims (1)
接導体箔を形成したフレキシブル配線板に、金バンプを
介して半導体チップを搭載、接合してなることを特徴と
する半導体実装構造。1. A semiconductor packaging structure comprising a flexible wiring board having a conductor foil directly formed on a surface of a base material made of a resin material, and a semiconductor chip mounted and bonded to the flexible wiring board via gold bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24240493A JP3382316B2 (en) | 1993-09-29 | 1993-09-29 | Semiconductor mounting structure and semiconductor mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24240493A JP3382316B2 (en) | 1993-09-29 | 1993-09-29 | Semiconductor mounting structure and semiconductor mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0799215A true JPH0799215A (en) | 1995-04-11 |
| JP3382316B2 JP3382316B2 (en) | 2003-03-04 |
Family
ID=17088640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24240493A Expired - Fee Related JP3382316B2 (en) | 1993-09-29 | 1993-09-29 | Semiconductor mounting structure and semiconductor mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3382316B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101451887B1 (en) * | 2012-04-26 | 2014-10-16 | 하나 마이크론(주) | Integrated circuit device package and method for manufacturing the same |
-
1993
- 1993-09-29 JP JP24240493A patent/JP3382316B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101451887B1 (en) * | 2012-04-26 | 2014-10-16 | 하나 마이크론(주) | Integrated circuit device package and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3382316B2 (en) | 2003-03-04 |
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