JPH0324740A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a thin type by the amount of a pair chip thickness, and improve strength and reliability, by face-down-bonding and mounting a pair chip on an inner layer pattern of a mulilayered substrate. CONSTITUTION:A pair chip 1 is subjected to face down bonding on at least the inner layer pattern of a multilayered substrate 6, made to drop in the multilayer substrate 6, and mounted thereon. That is, a hole in which the pair chip 1 is dropped is made in a first layer substrate 7; an inner layer substratum 8 having a pattern 5 capable of connecting the pair chip 1 by using a gold bump 2 is stuck by using adhesive agent and the like; the first Layer pattern 4 and the inner layer pattern 6 are electrically connected by using through holes and the Iike; the inner pattern 5 is gold-plated. The pair chip 1 and the inner pattern 5 are electrically connected, and simultaneously the first layer pattern 4 is also electrically connected, which are packaged by using sealing material 3. Thereby a thin type device can be realized, and strength and reliability can be improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device in which paired chips are face-down bonded and mounted on a multilayer board. However, the above-mentioned conventional technology has the problem that the paired chips are exposed and the chip becomes thick. Also, the second
As shown in the figure, since only a small amount of sealant can be applied, there are problems in terms of strength and reliability. The present invention is intended to solve these problems, and its purpose is to make it thinner. Another object of the present invention is to provide a semiconductor device that can be improved in terms of strength and reliability.

[Means for Solving the Problems] The semiconductor device of the present invention is a semiconductor device in which paired chips are mounted by seven-eighth down bonding on a multilayer board having three or more layers, in which the bare chip is mounted face-to-face on an inner layer pattern of the multilayer board. down bonding,
It is characterized in that the paired chips are mounted on the multilayer board.

[Embodiment] FIG. 1 is a main sectional view in an embodiment of the present invention. The first layer base material 7K has a pattern 5 in which holes are made into which paired chips 1 can be inserted, and the paired chips 1 can be connected by gold bumps 2. The inner layer base material 8 is bonded together with an adhesive or the like, the first layer pattern 4 and the inner layer pattern 5 are electrically connected through a through hole or the like, and the inner layer pattern 5 is plated with gold by electrolytic plating. The pair chips 1 are connected to the gold bumps 2 and the inner layer pattern 5 by heat, ultrasonic waves, etc., and the pair chips 1 and the inner layer pattern 5 are electrically connected, and the first layer pattern 4 is also electrically connected to the pair chips 1 through the through holes. This is a face-down bonding mounting structure in which the components are connected and packaged with a sealant 5. Pair chip 1 is not directly connected to multilayer board 60 surface pattern 4,
The paired chips 1 are dropped into the thickness of the multilayer substrate 6.

[Effects of the Invention] As described above, according to the present invention, the semiconductor device of the present invention can be made thinner by the thickness of the paired chips by 7-eight down bonding and mounting the paired chips on the inner layer pattern of the multilayer board. It has the effect that

Furthermore, since the paired chips are embedded in the substrate, the sealant can be made thicker, which has the effect of improving strength and reliability.

[Brief explanation of drawings]

FIG. 1 is a main sectional view showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a main sectional view showing a conventional semiconductor device. 1...Pair chip 2...Gold bumps formed on the pair chip 3...Sealant 4...・1st layer pattern 5 of multi-layer board 5・
......Second layer pattern 6 of multilayer board...
...Multilayer board 7...First pigeon base material 8 of multilayer board...
...Second layer base material of multilayer board or higher

Claims (1)

[Claims] A semiconductor device in which paired chips are face-down bonded and mounted on a multilayer board having three or more layers, characterized in that the paired chips are face-down bonded and mounted on at least an inner layer pattern of the multilayer board.