JP2008041801A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve quality and reliability of a semiconductor device by increasing process margin. <P>SOLUTION: In an SIP 10 where a semiconductor chip 1, an interposer substrate 2, and a semiconductor chip 3 are laminated on a wiring circuit board 7; ultrasonic-wave vibration can be transferred sufficiently during stud bump bonding process, because a part of the stud bump 2d in the upper stage side of the semiconductor chip 1 is embedded within a through-hole 1e of the semiconductor chip 1, and the through-hole 1e is opening to the external side of a bonding part 1f of a first electrode pad 1c. Accordingly, stud bump connection for reducing occurrence of defective shape and peeling or the like of the stud bump 1d can be assured, and process control on the occasion of forming the through-hole 1e with the laser process or etching process can be done easily, resulting in increment of process margin. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a semiconductor device having a plurality of stacked semiconductor chips.

The back surface of the semiconductor chip is thinned to a predetermined thickness by back grinding, etc., and a hole is formed at the back surface position corresponding to the device-side external electrode portion by dry etching until the surface electrode is reached. There is a technique in which a metal bump is formed by pressure welding a metal bump of another semiconductor chip laminated on the upper side into a through hole provided with the metal plating film (for example, a patent) Reference 1).
Japanese Patent Laying-Open No. 2005-340389 (FIG. 1)

  In recent years, SIP (System In Package) technology that realizes high-speed and high-functional systems in a short period of time by mounting a plurality of semiconductor chips with integrated circuits at high density has attracted attention. Has been proposed. In particular, development of a package having a structure in which a plurality of semiconductor chips are three-dimensionally stacked and wiring between these chips is three-dimensionally connected (hereinafter this structure is also referred to as a three-dimensional stacked structure) is being actively promoted. .

  In the three-dimensional stacked structure, through holes are formed in the semiconductor chip, and among the stacked semiconductor chips, some of the bumps (protruding electrodes) provided on the upper semiconductor chip are through holes in the lower semiconductor chip. Thus, the lower semiconductor chip and the upper semiconductor chip are electrically connected.

  Further, in order to realize a three-dimensional stacked structure, it is required to reduce the thickness of the semiconductor chip. Therefore, back grinding of the semiconductor wafer is performed, and then a through hole is formed by laser processing, etching processing, or the like from the back surface side to the approximate center of the electrode pad (first electrode pad) on the main surface.

  At that time, the hole must be stopped in front of the aluminum layer without penetrating the hole to the surface of the electrode pad. This is because, when a hole is formed in the bonding part of the electrode pad, when the stud bump bonding is performed on the electrode pad, the hole becomes a resistance and it is difficult to transmit ultrasonic vibration, and the stud bump has a defective shape or is peeled off. This is to cause bonding failure.

  Therefore, when forming the through-hole from the back side of the semiconductor wafer, the hole must be stopped before the aluminum layer of the electrode pad on the main surface side. The problem is that it cannot be stopped. In particular, when the through hole is formed by laser processing, it is a problem that it is difficult to control the irradiation energy.

  As a result, it is not possible to stabilize the treatment at the time of forming the through hole, and there is also a problem that the quality and reliability of the product are lowered.

  In the three-dimensional stacked structure of the semiconductor device described in Patent Document 1 (Japanese Patent Laid-Open No. 2005-340389), a through hole is formed in the bonding portion of the electrode pad, and an upper stud bump is formed in the through hole. Is embedded and exposed to the main surface side. Therefore, it is difficult to transmit ultrasonic vibration during stud bump bonding, which causes a defective bonding such as a shape defect or peeling of the stud bump.

  An object of the present invention is to provide a technique capable of increasing the process margin and improving the quality and reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes a wiring board, a first semiconductor chip connected to the wiring board via a first protruding electrode, and a second semiconductor electrode stacked on the first semiconductor chip via a second protruding electrode. And a second semiconductor chip stacked on the interposer substrate via a third protruding electrode. Further, the first semiconductor chip has a plurality of first electrode pads formed on the main surface, and a through hole reaching the first electrode pad from the back surface of the first semiconductor chip, and has a second protruding shape. A part of the electrode is embedded in the through hole, and the through hole of the first semiconductor chip is opened outside the bonding portion to which the first protruding electrode of the first electrode pad is connected. It is.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A part of the second protruding electrode on the upper stage of the first semiconductor chip is embedded in the through hole of the first semiconductor chip, and the through hole is the first protruding electrode of the first electrode pad. Since the opening is formed outside the bonding portion to which the is connected, ultrasonic vibrations can be sufficiently transmitted during the stud bump bonding. As a result, it is possible to secure a stud bump connection that reduces bonding defects. Therefore, when forming a through-hole, the first electrode pad is opened without stopping the hole before the aluminum layer of the first electrode pad. Through-holes can be formed. As a result, the process margin when forming the through hole by laser processing or etching processing can be increased, and the quality and reliability of the product (semiconductor device) can be improved.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
1 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing a connection structure between chips in the semiconductor device shown in FIG. 1, and FIG. It is an expanded partial sectional view which shows the structure of the A section shown. 4 is a partial cross-sectional view showing the structure cut along the line AA shown in FIG. 3, and FIG. 5 is a partial cross-sectional view showing a modification of the structure cut along the line AA shown in FIG. 6 is a partial cross-sectional view showing another modification of the structure cut along the line AA shown in FIG. 7 is an enlarged partial sectional view showing the structure of the through hole shown in FIG. 4, FIG. 8 is an enlarged partial sectional view showing the structure of the through hole shown in FIG. 5, and FIG. 9 is a method for forming the through hole shown in FIG. FIG. 10 is a manufacturing flow diagram showing a modified example of the through hole forming method shown in FIG. 7, and FIG. 11 is a manufacturing flow diagram showing an example of the through hole forming method shown in FIG. .

  The semiconductor device of the present embodiment is a semiconductor package having a plurality of semiconductor chips formed using a thinned semiconductor wafer.

  The semiconductor device described in the present embodiment is a SIP 10 in which a plurality of semiconductor chips 1 and 3 and an interposer substrate 2 are mounted with high density to realize a high-speed and high-function system. 1 and 3 and the interposer substrate 2 are stacked and mounted, and have a three-dimensional stacked structure in which wiring between these chips and between the chip and the substrate is three-dimensionally connected. In order to realize a three-dimensional laminated structure, it is necessary to mount a thin chip.

  The SIP 10 shown in FIG. 1 and FIG. 3 as an example of the semiconductor device of the present embodiment includes a chip stacked body 8 composed of a plurality of chips and the interposer substrate 2 that are three-dimensionally stacked on the main surface 7 a of the wiring substrate 7. It has a package structure. Although not limited to this in the present embodiment, for example, two semiconductor chips 1 and 3 are three-dimensionally stacked with an interposer substrate 2 interposed therebetween.

  As shown in FIG. 2, the wiring substrate 7 has a square shape in a plane that intersects the plate thickness direction. Although not limited to this, for example, it is made of a resin substrate obtained by impregnating glass fiber with epoxy or polyimide resin, and the main surface 7a is made of a part of each of the plurality of wirings as shown in FIG. A plurality of connection electrodes 7c are arranged, and a plurality of bump lands 7e made of a part of each of the plurality of wirings are arranged on the back surface 7b opposite to the main surface 7a. That is, the wiring board 7 is a two-layer board in which wiring is formed on each of the main surface 7a and the back surface 7b, and the connection electrode 7c on the main surface 7a is connected to the back surface 7b via the through-hole wiring 7d formed inside. It is electrically connected to the bump land 7e.

  Further, for example, solder bumps 6 are electrically and mechanically connected as external connection terminals to each of the plurality of bump lands 7e.

  Further, as shown in FIG. 2, each of the semiconductor chips 1 and 3 and the interposer substrate 2 has a rectangular plane shape that intersects with the thickness direction thereof. Here, as shown in FIG. 3, the semiconductor chip 1 as the first semiconductor chip has a main surface (circuit forming surface, element forming surface) 1 a and a back surface 1 b located on opposite sides, and the main surface thereof. An integrated circuit is formed on the surface 1a side. As the integrated circuit, for example, a control circuit is formed. Further, a plurality of first electrode pads 1c are formed on the main surface 1a along the peripheral edge.

  Further, as shown in FIGS. 3 and 4, the semiconductor chip 1 has through holes 1 e provided corresponding to the plurality of first electrode pads 1 c. The through hole 1e is a hole formed by laser processing or etching processing, and has a shape that reaches the first electrode pad 1c on the main surface 1a side from the back surface 1b side of the semiconductor chip 1. At that time, the through-hole 1e opens to the outside of the bonding portion 1f to which the stud bump (first protruding electrode) 1d of the first electrode pad 1c is connected. That is, the through-hole 1e reaches the first electrode pad 1c from the back surface 1b side and opens, but does not open in the bonding portion 1f to which the stud bump 1d is connected. It is formed so as to open in a region outside the bonding portion 1f in 1c.

  Similarly to the semiconductor chip 1, the semiconductor chip 3 as the second semiconductor chip has a main surface (circuit forming surface, element forming surface) 3a and a back surface 3b located on the opposite sides. An integrated circuit is formed on the surface 3a side. As the integrated circuit, for example, an SDRAM (Synchronous Dynamic Random Access Memory) which is one of the memory circuits is formed. Further, a plurality of second electrode pads 3c are formed on the main surface 3a along the peripheral edge.

  The interposer substrate 2 is a substrate made of silicon having a thickness of about 30 μm, for example, and has a main surface 2a and a back surface 2b positioned on opposite sides. The interposer substrate 2 is a substrate that is disposed between the lowermost semiconductor chip 1 and the uppermost semiconductor chip 3 and serves as a bridge for wiring when the electrode pads of both chips are electrically connected. A gold-plated wiring portion 2c is formed on the main surface 2a side. Further, the interposer substrate 2 has a through-hole that reaches and opens from the back surface 2b to the gold-plated wiring portion 2c on the main surface 2a, corresponding to the position of the second electrode pad 3c of the semiconductor chip 3 arranged on the upper stage. 2e is formed.

  Here, in the through hole 1e of the semiconductor chip 1 and the through hole 2e of the interposer substrate 2, as shown in FIG. 7, a hole insulating film 1k is formed on the inner peripheral wall, and further, it is made of Cr or the like. A seed layer 1j is formed, and a plating film 1i made of Au, Cu, or the like is formed thereon. Further, on the interlayer insulating film 1m of the main surface 1a, a first electrode pad 1c electrically connected to the plated film 1i of the through hole 1e through the seed layer 1j is formed on the seed layer 1n made of Ti or the like. Is formed.

  As described above, the semiconductor chip 1 and the interposer substrate 2 have the first electrode pads 1c and the gold-plated wiring portions 2c provided on the main surfaces 1a and 2a, and the inner peripheral wall surfaces of the respective through holes 1e and the through holes 2e. And a through electrode made of a plated film 1i electrically connected to the first electrode pad 1c and the gold-plated wiring portion 2c is formed. The through electrodes are led out to the back surface 1b of the semiconductor chip 1 and the back surface 2b of the interposer substrate 2, respectively, and have a concave shape along the inner peripheral wall surfaces of the through holes 1e and the through holes 2e.

  In the SIP 10 of the present embodiment, as shown in FIG. 3, first, the semiconductor chip 1 is mounted on the wiring board 7 via the stud bumps 1 d that are the first protruding electrodes. At this time, the stud bump 1 d is connected to the bonding portion 1 f of the first electrode pad 1 c of the semiconductor chip 1, and the stud bump 1 d is connected to the connection electrode 7 c on the main surface 7 a of the wiring substrate 7 and the solder material 9. Electrically connected.

  The interposer substrate 2 disposed on the semiconductor chip 1 is mounted via stud bumps 2d that are second projecting electrodes. At this time, the stud bump 2d is connected to the gold-plated wiring portion 2c formed on the main surface 2a by gold-gold connection, and a part of the tip side is embedded in the through hole 1e of the semiconductor chip 1. (Pressurized and injected into the recess of the through electrode). More specifically, a part of the stud bump 2d of the interposer substrate 2 arranged on the upper stage side is inserted into the through hole 1e of the semiconductor chip 1 arranged on the lower stage side (a concave portion of the through electrode), and the lower stage It is electrically connected to the first electrode pad 1c of the semiconductor chip 1 on the side. A part of the stud bump 2d is pressed into the through hole 1e (a concave portion of the through electrode) by deformation accompanied by plastic flow.

  Thereby, the first electrode pad 1c of the semiconductor chip 1 and the gold-plated wiring portion 2c of the main surface 2a of the interposer substrate 2 are electrically connected via the stud bump 2d.

  Further, the semiconductor chip 3 disposed on the interposer substrate 2 is disposed on the interposer substrate 2 via the stud bumps 3d that are the third protruding electrodes, as in the case of the interposer substrate 2 disposed on the semiconductor chip 1. It is mounted on. At that time, the stud bump 3d is connected to the second electrode pad 3c formed on the main surface 3a, and a part on the tip side thereof is embedded in the through hole 2d of the interposer substrate 2.

  Thereby, the gold-plated wiring portion 2c of the interposer substrate 2 and the second electrode pad 3c of the semiconductor chip 3 are electrically connected via the stud bump 3d.

  In this way, the first electrode pad 1c of the lowermost semiconductor chip 1 is connected to the second electrode of the uppermost semiconductor chip 3 via the stud bump 2d, the gold-plated wiring portion 2c on the interposer substrate 2 and the stud bump 3d. Three-dimensionally and electrically connected to the pad 3c.

  The stud bumps 1d, 2d, and 3d are projecting electrodes formed of, for example, Au.

  Further, in the chip laminated body 8, the lowermost semiconductor chip 1 is bonded and fixed to the main surface 7 a of the wiring substrate 7 with an adhesive 4 interposed between the main surface 1 a and the main surface 7 a of the wiring substrate 7. Has been. As the adhesive 4, for example, a sheet-like anisotropic conductive resin (ACF: Anisotropic Conductive Film) in which a large number of conductive particles are mixed in an epoxy thermosetting insulating resin is used. Further, the stud bump 1d of the lowermost semiconductor chip 1 is pressed into contact with the connection electrode 7c of the wiring board 7 by the heat shrinkage force of the adhesive material 4, the thermosetting shrinkage force of the adhesive material 4, and the like. Electrically connected.

  Further, the space between the semiconductor chip 1 and the interposer substrate 2 and the space between the interposer substrate 2 and the semiconductor chip 3 are sealed with a sealing adhesive 5 to maintain mechanical strength and at the same time be protected from the external environment. .

  According to the semiconductor device of the present embodiment, a part of the upper stud bump 2d of the semiconductor chip 1 is embedded in the through hole 1e of the semiconductor chip 1, and the through hole 1e is formed on the first electrode pad 1c. Since the opening is formed outside the bonding portion 1f to which the stud bump 1d is connected, and the through hole 1e is disposed outside the bonding portion 1f where the stud bump bonding is performed, the ultrasonic vibration is sufficiently transmitted during the stud bump bonding. be able to.

  As a result, it is possible to secure a stud bump connection that reduces bonding defects such as defective shape and peeling of the stud bump 1d. As a result, when forming a through hole, a hole is formed in front of the aluminum layer of the first electrode pad 1c. The through-hole 1e opened to the 1st electrode pad 1c can be formed, without making it stop.

  This facilitates process control when forming the through-hole 1e by laser processing or etching processing, thereby increasing the process margin and, as a result, improving the quality and reliability of the product (SIP10). it can.

  Next, a modification of the present embodiment will be described. FIG. 5 shows a structure in which the through hole is divided into two stages of a first through hole and a second through hole. That is, as shown in FIG. 8, the through-hole 1e communicates with the first through-hole 1g that opens to the main surface 1a side of the semiconductor chip 1 and the first through-hole 1g, and the first through-hole. The second through hole 1h having a hole diameter larger than 1 g is formed. At that time, the diameter of the first through hole 1g opened on the main surface 1a side is made smaller than the diameter of the second through hole 1h opened on the back surface 1b side, whereby the first electrode pad on the main surface 1a side. Even when the area of 1c is small and there is a small empty area outside the bonding part 1f connecting the stud bump 1d in the first electrode pad 1c, the area is outside the bonding part 1f of the first electrode pad 1c. The first through hole 1g can be opened.

  In the modification shown in FIG. 6, the through hole 1e of the semiconductor chip 1 is formed so as to open to the lead-out wiring portion 1p connected to the first electrode pad 1c. That is, the through hole 1e does not necessarily have to be formed in the first electrode pad region, and may be formed to open to the lead-out wiring portion 1p connected to the first electrode pad 1c.

  Next, a method for forming a through electrode including a through hole will be described. FIG. 9 shows a procedure for forming the through-hole shown in FIG. 7 by forming a through-hole by etching. First, a BG (Back Grinding) completed semiconductor wafer shown in step S1 is prepared. Thereafter, resist coating in step S2 and photolithography in step S3 are sequentially performed, and further, a through hole is formed by etching in step S4 to form a through hole 1e.

Thereafter, the resist removal in step S5 and the insulating film (SiO ₂ ) formation in step S6 are sequentially performed to form the hole insulating film 1k and the interlayer insulating film 1m. Further, the Cr / Au seed layer is formed in step S7 to form the seed layer 1j on the insulating film, and then the electrolytic Au plating is formed in step S8 to form the Au or Cu plating film 1i on the seed layer 1j. Form.

  Thereafter, photolithography in step S9 is performed, and Au / Cr wet etching in step S10 is further performed to complete the through electrode.

  Next, the modification shown in FIG. 10 shows the procedure in the case of forming the through-hole shown in FIG. 7 by forming the through-hole by laser processing. First, a BG (Back Grinding) completed semiconductor wafer shown in step S11 is prepared, and then a hole is dug by a laser in step S12 to form a through hole 1e.

Thereafter, an insulating film (SiO ₂ ) is formed in step S13 to form a hole insulating film 1k and an interlayer insulating film 1m. Further, the Cr / Au seed layer is formed in step S14 to form the seed layer 1j on the insulating film, and then the electrolytic Au plating is formed in step S15 to form the Au or Cu plating film 1i on the seed layer 1j. Form.

  Thereafter, photolithography in step S16 is performed, and Au / Cr wet etching is further performed in step S17, thereby completing the through electrode.

  Next, the modification shown in FIG. 11 shows a procedure in the case where the through-hole shown in FIG. 8 is formed by forming the through-hole in two stages by etching. First, a BG (Back Grinding) completed semiconductor wafer shown in step S21 is prepared. Thereafter, resist coating in step S22 and photolithography in step S23 are sequentially performed, and further, Si dry etching in step S24 is performed to form a second through hole 1h having a large hole diameter.

Thereafter, the resist removal in step S25 and the insulating film (SiO ₂ ) formation in step S26 are sequentially performed to form the hole insulating film 1k and the interlayer insulating film 1m. Further, the contact insulating film in step S27 is etched to form a first through hole 1g having a smaller diameter than the second through hole 1h, and is composed of the first through hole 1g and the second through hole 1h. The through hole 1e is formed.

  Thereafter, the Cr / Au seed layer is formed in step S28 to form the seed layer 1j on the insulating film, and then the electrolytic Au plating is formed in step S29 to form the Au or Cu plating film 1i on the seed layer 1j. Form.

  Thereafter, photolithography in step S30 is performed, and Au / Cr wet etching in step S31 is further performed to complete the through electrode.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above embodiment, the case where the semiconductor chip and the interposer substrate are stacked in three stages in the SIP 10 has been described. However, the number of stacked semiconductor chips may be any number, and the interposer substrate is mounted. Any number of sheets may be stacked as necessary.

  The present invention is suitable for an electronic device having a plurality of stacked semiconductor chips.

It is sectional drawing which shows an example of the structure of the semiconductor device of embodiment of this invention. FIG. 2 is a plan view showing a developed connection structure between chips in the semiconductor device shown in FIG. 1. FIG. 2 is an enlarged partial cross-sectional view showing a structure of a portion A shown in FIG. 1. It is a fragmentary sectional view which shows the structure cut | disconnected along the AA line shown in FIG. It is a fragmentary sectional view which shows the modification of the structure cut | disconnected along the AA line shown in FIG. It is a fragmentary sectional view which shows the other modification of the structure cut | disconnected along the AA line shown in FIG. FIG. 5 is an enlarged partial sectional view showing the structure of the through hole shown in FIG. 4. FIG. 6 is an enlarged partial sectional view showing the structure of the through hole shown in FIG. 5. It is a manufacturing flowchart which shows an example of the formation method of the through-hole shown in FIG. It is a manufacturing flowchart which shows the modification of the formation method of the through-hole shown in FIG. It is a manufacturing flowchart which shows an example of the formation method of the through-hole shown in FIG.

Explanation of symbols

1 Semiconductor chip (first semiconductor chip)
1a main surface 1b back surface 1c first electrode pad 1d stud bump (first protruding electrode)
1e Through-hole 1f Bonding part 1g 1st through-hole 1h 2nd through-hole 1i Plating film 1j Seed layer 1k Insulating film for 1m Interlayer insulating film 1n Seed layer 1p Lead-out wiring part 2 Interposer substrate 2a Main surface 2b Back surface 2c Gold plating Wiring part 2d Stud bump (second protruding electrode)
2e Through hole 3 Semiconductor chip (second semiconductor chip)
3a main surface 3b back surface 3c second electrode pad 3d stud bump (third projecting electrode)
DESCRIPTION OF SYMBOLS 4 Adhesive material 5 Sealing adhesive 6 Solder bump 7 Wiring board 7a Main surface 7b Back surface 7c Connection electrode 7d Through-hole wiring 7e Bump land 8 Chip laminated body 9 Solder material 10 SIP (semiconductor device)

Claims (5)

A wiring board having a main surface and a back surface facing the main surface, the main surface having a plurality of connection electrodes;
A first semiconductor chip having a main surface and a back surface opposite to the main surface, mounted on the main surface of the wiring board, and connected to the connection electrode via a first protruding electrode;
An interposer substrate laminated on the first semiconductor chip via a second protruding electrode;
A second semiconductor chip stacked on the interposer substrate via a third protruding electrode;
The first semiconductor chip has a plurality of first electrode pads formed on a main surface thereof, and a through hole reaching the first electrode pad from the back surface of the first semiconductor chip,
A part of the second protruding electrode is embedded in the through hole,
The semiconductor device according to claim 1, wherein the through hole of the first semiconductor chip is opened outside a bonding portion to which the first protruding electrode of the first electrode pad is connected.   2. The semiconductor device according to claim 1, wherein the through-hole communicates with the first through-hole opening on the main surface side of the first semiconductor chip, the first through-hole, and the first through-hole. A semiconductor device comprising a second through hole having a larger hole diameter than the hole.   2. The semiconductor device according to claim 1, wherein the first semiconductor chip has a control circuit, and the second semiconductor chip has a memory circuit.   2. The semiconductor device according to claim 1, wherein the through hole is a hole formed by laser processing or etching processing. A wiring board having a main surface and a back surface facing the main surface, the main surface having a plurality of connection electrodes;
A first semiconductor chip having a main surface and a back surface opposite to the main surface, mounted on the main surface of the wiring board, and connected to the connection electrode via a first protruding electrode;
An interposer substrate laminated on the first semiconductor chip via a second protruding electrode;
A second semiconductor chip stacked on the interposer substrate via a third protruding electrode;
The first semiconductor chip has a plurality of first electrode pads formed on a main surface thereof, and a through hole reaching the main surface from the back surface of the first semiconductor chip,
The first protruding electrode is connected to the first electrode pad;
A part of the second protruding electrode is embedded in the through hole,
The semiconductor device according to claim 1, wherein the through hole of the first semiconductor chip is opened in a lead-out wiring portion connected to the first electrode pad.

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