JPH046841A - Mounting structure of semiconductor device - Google Patents
Mounting structure of semiconductor deviceInfo
- Publication number
- JPH046841A JPH046841A JP10811390A JP10811390A JPH046841A JP H046841 A JPH046841 A JP H046841A JP 10811390 A JP10811390 A JP 10811390A JP 10811390 A JP10811390 A JP 10811390A JP H046841 A JPH046841 A JP H046841A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- mounting structure
- pads
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000007747 plating Methods 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 3
- 230000008646 thermal stress Effects 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 229910000846 In alloy Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 20
- 229910052782 aluminium Inorganic materials 0.000 description 19
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 19
- 239000010410 layer Substances 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は、フェースボンディングされる半導体装置の実
装構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mounting structure for a semiconductor device that is face-bonded.
〔従来の技術］
第７図は、従来の半導体装置がフェースボンディングに
より半導体装置実装基板に搭載された実装例を示すもの
で、半導体装置実装基板ｌの基板２はプラスチック系部
材により形成され、その上に導体リード３が設けられて
いる。この導体リード３が、半導体装置４に設けられた
アルミパッド５と導電性ゴム６により接着されて電気的
な接続が採られたものである。[Prior Art] FIG. 7 shows a mounting example in which a conventional semiconductor device is mounted on a semiconductor device mounting board by face bonding. A conductor lead 3 is provided on top. This conductor lead 3 is bonded to an aluminum pad 5 provided on a semiconductor device 4 using conductive rubber 6 to establish an electrical connection.
第８図は、従来の半導体装置がフェースボンディングに
より半導体装！実装基板に搭載された別の実装例を示す
もので、前記従来例と同様に半導体装置実装基板１の基
板２はプラスチック系部材により形成され、その上に導
体リード３が設けられている。一方、半導体装置４は突
起状電極バンプ７が形成された、いわゆるフリップチッ
プで、この電極バンプ７を前記電極リード３上に半田８
により接合して電気的な接続が採られたものである。Figure 8 shows that a conventional semiconductor device is a semiconductor device made by face bonding! This shows another example of mounting on a mounting board, in which the board 2 of the semiconductor device mounting board 1 is made of a plastic material, and conductor leads 3 are provided thereon, similar to the conventional example. On the other hand, the semiconductor device 4 is a so-called flip chip in which protruding electrode bumps 7 are formed, and the electrode bumps 7 are soldered onto the electrode leads 3 with solder 8.
An electrical connection is made by joining the two.
ところで、第７図に示す従来の実装構造においては、半
導体装置実装基板１の基板２と半導体装置４の熱膨張率
の差により熱的なストレス生し、このストレスが接合部
に加わると導電性ゴム６が半導体装Ｗ４のアルミパッド
５からはがれ易く、また、接合部の接触抵抗が大きいた
めにそれらの間の導電性が非常に悪く電圧鋒下を生じ、
高速な信号伝達を必要とする半導体装Ｗ４を搭載できな
いという問題点があった。By the way, in the conventional mounting structure shown in FIG. 7, thermal stress is generated due to the difference in thermal expansion coefficient between the substrate 2 of the semiconductor device mounting board 1 and the semiconductor device 4, and when this stress is applied to the joint, the conductivity increases. The rubber 6 easily peels off from the aluminum pad 5 of the semiconductor device W4, and since the contact resistance at the joint is large, the conductivity between them is very poor, causing voltage drop.
There was a problem in that the semiconductor device W4, which requires high-speed signal transmission, could not be mounted.
また、第８図に示す従来の別の実装構造においては、半
導体装置実装基板１の導電性リード３と半導体装置４の
アルミパッド５が半田８により密着して固定されている
ため、それらの熱膨張率の差により熱的なストレスが加
わると接合部が疲労し、クランクが生じたり断線したり
するという問題点があった。In addition, in another conventional mounting structure shown in FIG. 8, the conductive leads 3 of the semiconductor device mounting board 1 and the aluminum pads 5 of the semiconductor device 4 are closely fixed by solder 8, so that the heat generated between them is When thermal stress is applied due to the difference in expansion coefficients, the joints become fatigued, causing problems such as cranking or wire breakage.
本発明は、前記背景に鑑みてなされたものであり、その
目的とするところは、熱的なストレスに強くかつ、接合
部の接触抵抗が低く導電性の良い半導体装置の実装構造
を提供することにある。The present invention has been made in view of the above-mentioned background, and its purpose is to provide a mounting structure for a semiconductor device that is resistant to thermal stress, has low contact resistance at joints, and has good conductivity. It is in.
〔課題を解決するための手段］
上記課題を解決するため本発明は、パッド５を存する半
導体袋１４を、電極バンプ９を有する半導体装置実装基
板１にフェースポンディングにより実装する半導体装置
４の実装構造であって、前記電極バンプ９が、弾性を有
する導電性部材により構成されると共に、高導電率を有
する、例えばＡｕ＋ Ｃｕ＋ Ｉｎ合金等の金属部材に
よるメンキ層１０で覆われ、かつ、該電極バンプ９の大
ききが、前記半導体装置４のパッド５より小さく、前記
電極バンプ９と前記半導体装置４のパッド５を、圧接す
ることにより電気的接続が採られることを特徴とするも
のである。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a method for mounting a semiconductor device 4 in which a semiconductor bag 14 having a pad 5 is mounted on a semiconductor device mounting board 1 having an electrode bump 9 by face bonding. In this structure, the electrode bump 9 is made of an elastic conductive member, and is covered with a coating layer 10 made of a metal member having high conductivity, such as an Au+Cu+In alloy. The bumps 9 are smaller in size than the pads 5 of the semiconductor device 4, and electrical connection is achieved by pressing the electrode bumps 9 and the pads 5 of the semiconductor device 4 into contact with each other.
上記のように本発明の実装構造においては、半導体装置
４を半導体装置実装基板１にフェースポンディングして
、アルミパッド５と電極バンプ９を圧接接続しているた
め、熱的なストレスを加えても、そのストレスが比較的
小さい場合には、電極バンプ９の弾性により電極バンプ
９が変形して応力を吸収し、ストレスが大きい場合には
電極バンプ９の弾性に加えて、電極バンプ９とアルミバ
ンド５の接触点が移動して応力を吸収するという応力に
対するコンプライアンス（応力吸収性）を持つ。なお、
この時電極バンプ９とアルミパッド５は圧接接続されて
いるため、それらの間には互いに吸引する方向の力が常
時存在し、電気的導通は常時確保されている。また、電
極バンプ９の表面は、高導電率を有する金属部材による
メッキ層１０で覆われているため、メッキ層１０にも電
流が流れ、アルミパッド５との間の接触抵抗は低くなり
、導電性が極めて良くなる。As described above, in the mounting structure of the present invention, the semiconductor device 4 is face bonded to the semiconductor device mounting board 1, and the aluminum pad 5 and the electrode bump 9 are connected by pressure contact, so that thermal stress is not applied. However, when the stress is relatively small, the elasticity of the electrode bump 9 deforms the electrode bump 9 and absorbs the stress, and when the stress is large, in addition to the elasticity of the electrode bump 9, the electrode bump 9 and the aluminum It has stress compliance (stress absorbability) in which the contact point of the band 5 moves and absorbs stress. In addition,
At this time, since the electrode bumps 9 and the aluminum pads 5 are pressure-contacted, a mutually attractive force is always present between them, and electrical continuity is always ensured. In addition, since the surface of the electrode bump 9 is covered with a plating layer 10 made of a metal member having high conductivity, current also flows through the plating layer 10, and the contact resistance with the aluminum pad 5 becomes low, making it conductive. Sexuality is greatly improved.
第１図乃至第４図は、本発明の第１の実施例を示すもの
で、前記第１の従来例と異なる点は、電極バンプ９と該
電極バンプ９とアルミパッド５を圧接するための圧接手
段としての樹脂１１であり、以下具なる点について詳述
する。1 to 4 show a first embodiment of the present invention, which differs from the first conventional example in that the electrode bump 9 and the electrode bump 9 and the aluminum pad 5 are pressed into contact with each other. The resin 11 serves as a pressure contact means, and the following details will be described below.
電極バンプ９は、半導体装置実装基板ｌの導体リード３
上に設けられ、導電性ゴムや弾性を有する導電性樹脂等
により形成され、その表面には、例えばＡｕ、Ｃｕ、Ｉ
ｎ合金等の高導電率を有する薄膜のメンキ層１０が形成
されている。この電極バンプ９は導体リード３の先端で
あって、フェースポンディングにより搭載される半導体
装１４のアルミパッド５と対向する位置に設けられ、そ
の大きさは、アルミパッド５の大きさ以下に設定されて
いる。The electrode bumps 9 are connected to the conductor leads 3 of the semiconductor device mounting board l.
It is formed of conductive rubber, elastic conductive resin, etc., and its surface is coated with, for example, Au, Cu, I
A thin coating layer 10 made of n-alloy or the like having high conductivity is formed. This electrode bump 9 is provided at the tip of the conductor lead 3 at a position facing the aluminum pad 5 of the semiconductor device 14 mounted by face bonding, and its size is set to be smaller than the size of the aluminum pad 5. has been done.
圧接手段である樹脂１１は、半導体装置４と実装基板１
の間で、アルミパッド５と電極バンプ９の間の部分を除
いて充填され、この硬化時の収縮を利用して電極バンプ
９とアルミパッド５を吸引し圧接接続させて半導体装置
４を実装させるように構成したものである。The resin 11, which is a pressure contact means, is used to connect the semiconductor device 4 and the mounting board 1.
The area between the aluminum pads 5 and the electrode bumps 9 is filled, and the shrinkage during curing is used to attract the electrode bumps 9 and the aluminum pads 5 and press them together to mount the semiconductor device 4. It is configured as follows.
第２図は、本実施例の実装基板１の製造方法を示すもの
で、先ず、基板２上に設けた導体リード３の先端に導電
性ゴムによる突起部９ａをスクリーン印刷又は滴下環に
より形成する（同図（ａ）参照）。ここで導電性ゴＬは
例えばシリコン系のような接着性のあるものを用い、導
電性を持たせるためにＡｕ、Ｃｕ、Ａｇ、Ｎｉ等を混入
したものを使用する。FIG. 2 shows a method of manufacturing the mounting board 1 of this embodiment. First, a protrusion 9a made of conductive rubber is formed at the tip of the conductor lead 3 provided on the board 2 by screen printing or a dropping ring. (See figure (a)). Here, the conductive rubber L is made of adhesive material such as silicone, and mixed with Au, Cu, Ag, Ni, etc. to provide conductivity.
次に、突起部９ａを除いてマスキングテープ１２等でマ
スキングを行い（同図■）参照） 、Ａｕ＋Ｃｕ＋Ｉｎ
合金等の電解メッキにより突起部９ａに薄膜のメッキ層
ｌＯを形成しく同図（Ｃ）参照）、その後、マスキング
テープ１２を剥がすことにより製造される（同図（ｄ）
参照）。Next, masking is performed with masking tape 12, etc., except for the protrusion 9a (see (■) in the same figure), and the Au+Cu+In
A thin plating layer 10 is formed on the projection 9a by electrolytic plating of an alloy or the like (see figure (C)), and then the masking tape 12 is peeled off (see figure (d)).
reference).
このような実装構造によれば、半導体装置４を半導体装
置実装基板１にフェースボンディングして、アルミパッ
ド５と電極バンブ９を圧接接続しているため、熱的なス
トレスを加えても、そのストレスが比較的小さい場合に
は、第３図に示すように電極バンプ９の弾性により電極
バンプ９が変形して応力を吸収し、ストレスが大きい場
合には、第４図に示すように電極バンブ９の弾性に加え
て、電気的導通を保ったままで電極バンブ９とアルミパ
ッド５の接触点が、移動量Ｗだけ移動して応力を吸収す
るという応力に対するコンプライアンス（応力吸収性）
を持ち、熱によるストレスに非常に強い。また、電極バ
ンブ９の表面は、高導電率を有する金属部材によるメン
キ層１０で覆われているため、メッキ層１０にも電流が
流れ、アルミパッド５との間の接触抵抗は低くなり、導
電性が極めて良くなり、高速な信号伝達を必要とする半
導体装置４の搭載が可能となる。According to such a mounting structure, since the semiconductor device 4 is face-bonded to the semiconductor device mounting board 1 and the aluminum pad 5 and the electrode bump 9 are pressure-connected, even if thermal stress is applied, the stress will be suppressed. When the stress is relatively small, the elasticity of the electrode bump 9 deforms the electrode bump 9 to absorb the stress, as shown in FIG. 3, and when the stress is large, the electrode bump 9 deforms as shown in FIG. In addition to the elasticity, the contact point between the electrode bump 9 and the aluminum pad 5 moves by the amount of movement W and absorbs stress while maintaining electrical continuity (stress absorbability).
and is extremely resistant to heat stress. Furthermore, since the surface of the electrode bump 9 is covered with a plating layer 10 made of a metal member having high conductivity, current also flows through the plating layer 10, and the contact resistance with the aluminum pad 5 becomes low, making it conductive. This makes it possible to mount a semiconductor device 4 that requires high-speed signal transmission.
第５図は本発明の第２の実施例を示すもので、前記第１
の実施例と異なる点は、圧接手段としての樹脂１１を半
導体装置４を覆うように充填したことであり、本実施例
においても前記第１の実施例と同様の効果を奏する。FIG. 5 shows a second embodiment of the present invention.
The difference from the first embodiment is that the semiconductor device 4 is filled with resin 11 as a pressure contact means, and the present embodiment has the same effect as the first embodiment.
第６図は本発明の第３の実施例を示すもので、前記第１
の実施例と異なる点は、圧接手段としての板バネ１１を
用いた点である。この板バネ１１は半導体装置４と半導
体装基板１を挟み込む形で設けられ、電極バンプ９とア
ルミパッド５を圧接接続するものである。このように構
成しても、前記第１の実施例と同様の効果を奏する。FIG. 6 shows a third embodiment of the present invention.
This embodiment differs from the embodiment in that a leaf spring 11 is used as the pressure contact means. The plate spring 11 is provided to sandwich the semiconductor device 4 and the semiconductor substrate 1, and connects the electrode bump 9 and the aluminum pad 5 by pressure contact. Even with this configuration, the same effects as in the first embodiment can be achieved.
なお、本実施例において圧接手段１１は板バネに限らず
、半導体装置４と半導体装基板１の電極間に、それらを
押し当てる方向の力を加えるどのような圧接具であって
も良く、また、前記各実施例において電極バンプ９は円
柱状に限って説明を行ったが、本発明はこれに限らず、
球状や角柱状のようなどのようなものであっても良いこ
とは勿論である。In this embodiment, the pressure contact means 11 is not limited to a leaf spring, but may be any pressure contact tool that applies a force in the direction of pressing the semiconductor device 4 and the semiconductor device substrate 1 between the electrodes. In each of the above embodiments, the electrode bump 9 has been described as having a cylindrical shape, but the present invention is not limited to this.
Of course, the shape may be spherical or prismatic.
本発明の実装構造によれば、半導体装置を半導体装置実
装基板にフェースポンディングして、半導体装置のアル
ミパッドと実装基板の電極バンプを圧接接続しているた
め、熱的なストレスを加えても、そのストレスが比較的
小さい場合には、電極バンプの弾性により電極バンブが
変形して応力を吸収し、ストレスが大きい場合には、電
極バンプの弾性に加えて、電気的導通を保ったままで電
極バンプとアルミパッドの接触点が移動して応力を吸収
するという応力に対するコンプライアンス（応力吸収性
）を持ち、熱によるストレスに非常に強い。また、電極
バンブの表面は、高導電率を有する金属部材によるメッ
キ層で覆われているため、メッキ層にも電流が流れ、ア
ルミパッドとの間の接触抵抗は低くなり、導電性が極め
て良くなり、高速な信号伝達を必要とする半導体装置４
の搭載が可能となる。According to the mounting structure of the present invention, the semiconductor device is face-bonded to the semiconductor device mounting board, and the aluminum pad of the semiconductor device and the electrode bump of the mounting board are pressure-connected, so that thermal stress is not applied. When the stress is relatively small, the elasticity of the electrode bump deforms and absorbs the stress, and when the stress is large, the elasticity of the electrode bump deforms the electrode and causes the electrode to deform while maintaining electrical continuity. It has stress compliance (stress absorption ability) in which the contact point between the bump and the aluminum pad moves and absorbs stress, and is extremely resistant to thermal stress. In addition, since the surface of the electrode bump is covered with a plating layer made of a metal member with high conductivity, current also flows through the plating layer, resulting in low contact resistance with the aluminum pad and extremely good conductivity. Semiconductor device 4 that requires high-speed signal transmission
It becomes possible to install
第１図は本発明の第１の実施例を示す一部断面側面図、
第２図（ａ）〜（ｄ）は同上の製造方法を示す一部断面
側面図、第３図は同上の熱による応力が小さい場合の一
部断面側面図、第４回は同上の熱による応力が大きい場
合の一部断面側面図、第５図は本発明の第２の実施例を
示す一部断面側面図、第６図は本発明の第３の実施例を
示す一部断面側面図、第７図は半導体装置の従来の実装
構造を示す一部断面側面図、第８図は従来の別の実装構
造を示す一部断面側面図である。
１−半導体装置実装基板
４−半導体装置 ５−バンドFIG. 1 is a partially sectional side view showing a first embodiment of the present invention;
Figures 2 (a) to (d) are partial cross-sectional side views showing the same manufacturing method as above, Figure 3 is a partial cross-sectional side view when stress due to heat as above is small, and 4th figure is a side view in partial cross section showing the same manufacturing method as above. FIG. 5 is a partial cross-sectional side view showing a second embodiment of the present invention; FIG. 6 is a partial cross-sectional side view showing a third embodiment of the present invention. 7 is a partially sectional side view showing a conventional mounting structure for a semiconductor device, and FIG. 8 is a partially sectional side view showing another conventional mounting structure. 1-Semiconductor device mounting board 4-Semiconductor device 5-Band
Claims (1)
る半導体装置実装基板に、フェースボンディングにより
実装する半導体装置の実装構造であって、前記電極バン
プが弾性を有する導電性部材により構成されると共に、
高導電率を有する金属部材によるメッキ層で覆われ、か
つ、該電極バンプの大きさが前記半導体装置のパッドよ
り小さく、前記電極バンプと前記半導体装置のパッドを
圧接することにより電気的接続が採られることを特徴と
する半導体装置の実装構造。(1) A semiconductor device mounting structure in which a semiconductor device having a pad is mounted on a semiconductor device mounting board having electrode bumps by face bonding, wherein the electrode bumps are made of an elastic conductive member, and
The electrode bump is covered with a plating layer made of a metal member having high conductivity, and the size of the electrode bump is smaller than the pad of the semiconductor device, and an electrical connection is achieved by pressing the electrode bump and the pad of the semiconductor device. A mounting structure for a semiconductor device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10811390A JPH046841A (en) | 1990-04-24 | 1990-04-24 | Mounting structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10811390A JPH046841A (en) | 1990-04-24 | 1990-04-24 | Mounting structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH046841A true JPH046841A (en) | 1992-01-10 |
Family
ID=14476232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10811390A Pending JPH046841A (en) | 1990-04-24 | 1990-04-24 | Mounting structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046841A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5281883A (en) * | 1990-11-05 | 1994-01-25 | Fujitsu Limited | Surface acoustic wave device with improved junction bonding and package miniaturization |
| US5345365A (en) * | 1992-05-05 | 1994-09-06 | Massachusetts Institute Of Technology | Interconnection system for high performance electronic hybrids |
| US5477087A (en) * | 1992-03-03 | 1995-12-19 | Matsushita Electric Industrial Co., Ltd. | Bump electrode for connecting electronic components |
| EP0951063A4 (en) * | 1996-03-06 | 1999-10-20 | ||
| US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
| US7875807B2 (en) | 2002-07-18 | 2011-01-25 | Ricoh Company, Ltd. | Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin |
-
1990
- 1990-04-24 JP JP10811390A patent/JPH046841A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5281883A (en) * | 1990-11-05 | 1994-01-25 | Fujitsu Limited | Surface acoustic wave device with improved junction bonding and package miniaturization |
| US5477087A (en) * | 1992-03-03 | 1995-12-19 | Matsushita Electric Industrial Co., Ltd. | Bump electrode for connecting electronic components |
| US5345365A (en) * | 1992-05-05 | 1994-09-06 | Massachusetts Institute Of Technology | Interconnection system for high performance electronic hybrids |
| US6077725A (en) * | 1992-09-03 | 2000-06-20 | Lucent Technologies Inc | Method for assembling multichip modules |
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| EP0951063A4 (en) * | 1996-03-06 | 1999-10-20 | ||
| EP0951063A1 (en) * | 1996-03-06 | 1999-10-20 | Matsushita Electric Industrial Co., Ltd | Semiconductor device and process for producing the same |
| US6103551A (en) * | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
| US6452280B1 (en) | 1996-03-06 | 2002-09-17 | Matsushita Electric Industrial Co., Ltd. | Flip chip semiconductor apparatus with projecting electrodes and method for producing same |
| US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
| US7875807B2 (en) | 2002-07-18 | 2011-01-25 | Ricoh Company, Ltd. | Elastic conductive resin, and electronic device including elastic conductive bumps made of the elastic conductive resin |
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