JP3106846B2 - Method for manufacturing semiconductor chip mounting board - Google Patents

Method for manufacturing semiconductor chip mounting board

Info

Publication number
JP3106846B2
JP3106846B2 JP9129994A JP9129994A JP3106846B2 JP 3106846 B2 JP3106846 B2 JP 3106846B2 JP 9129994 A JP9129994 A JP 9129994A JP 9129994 A JP9129994 A JP 9129994A JP 3106846 B2 JP3106846 B2 JP 3106846B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
insulating
wiring board
conductive
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9129994A
Other languages
Japanese (ja)
Other versions
JPH07297317A (en
Inventor
功二 田邉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP9129994A priority Critical patent/JP3106846B2/en
Publication of JPH07297317A publication Critical patent/JPH07297317A/en
Application granted granted Critical
Publication of JP3106846B2 publication Critical patent/JP3106846B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、各種電子機器に使用さ
れる半導体チップ実装基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor chip mounting board used for various electronic devices.

【0002】[0002]

【従来の技術】近年、各種電子機器は携帯しやすいよう
に、また多くの機能を保有しながら、小形軽量化を達成
するために、LEDやマイコン等の半導体素子をベアチ
ップの状態で実装することが要求されてきている。また
薄型化された電子機器において電子部品を高密度に実装
するために筐体の曲面や隙間に自由に配線できるフレキ
ジブル回路板(以下、FPCという)の需要が急増して
いる。
2. Description of the Related Art In recent years, semiconductor devices such as LEDs and microcomputers have been mounted in the form of bare chips in order to achieve various electronic devices that are easy to carry and have many functions while achieving small size and light weight. Has been required. In addition, a demand for a flexible circuit board (hereinafter, referred to as FPC) that can be freely wired on a curved surface or a gap of a housing in order to mount electronic components at high density in a thin electronic device is rapidly increasing.

【0003】従来、半導体素子をベアチップの状態で実
装する方法としては金細線(ワイヤ)で半導体ベアチッ
プの電極パッドと回路配線板上の対応する各電極を接続
した後、半導体ベアチップおよび接続部分を樹脂封止す
るワイヤボンディング法(以下、WB法という)や、ポ
リイミド樹脂よりなる配線板に金バンプを介して半導体
ベアチップの電極パッドと回路配線板の対応する各電極
とを接続した後、半導体ベアチップおよび接続部分を樹
脂封止するTAB法が一般的に実用化されている。
Conventionally, as a method of mounting a semiconductor element in a bare chip state, after connecting an electrode pad of the semiconductor bare chip and each corresponding electrode on a circuit wiring board with a fine gold wire (wire), the semiconductor bare chip and the connection portion are made of resin. After connecting the electrode pads of the semiconductor bare chip and the corresponding electrodes of the circuit wiring board to the wiring board made of polyimide resin via gold bumps on a wiring board made of a polyimide resin, A TAB method of resin-sealing a connection portion is generally put to practical use.

【0004】また近年では極めて平滑度の高いセラミッ
ク基板を回路配線板としてその上に金バンブを介して半
導体ベアチップの電極パッドと回路配線板の各対応する
電極を加熱融着して接続し、その後に光硬化収縮性の封
止樹脂で電極接着部分を封止する実装方法(以下、MB
B法という)や液晶表示板のガラス基板上の透明電極に
半導体ベアチップを直接実装する方法として、半導体ベ
アチップの電極パッドに金バンプを形成しておき、その
金バンプを介して導電性接着剤でガラス基板の各対応す
る電極に接着して接続し、その後に光硬化収縮性の封止
樹脂で電極接着部分を封止する実装方法(以下、COB
法という)がよく知られている。
In recent years, a ceramic substrate having extremely high smoothness is used as a circuit wiring board, and the electrode pads of the semiconductor bare chip and the corresponding electrodes of the circuit wiring board are connected by heating and bonding via a gold bump. A method of sealing the electrode bonding portion with a light-curing shrinkable sealing resin (hereinafter referred to as MB
As a method of directly mounting a semiconductor bare chip on a transparent electrode on a glass substrate of a liquid crystal display panel, a gold bump is formed on an electrode pad of a semiconductor bare chip, and a conductive adhesive is applied through the gold bump. A mounting method (hereinafter referred to as COB) in which the electrodes are bonded and connected to the corresponding electrodes on the glass substrate, and then the electrode bonding portions are sealed with a light-curing shrinkable sealing resin.
Is well known.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来のWB法、TAB法、MBB法、COB法のいずれの
実装方法においても半導体ベアチップおよびその接続部
分を外部環境から保護するために封止樹脂で封止するこ
とが必要であった。WB法、TAB法の場合、封止樹脂
の硬化時の体積収縮が内部ストレスとして残存し、接続
信頼性に悪影響を及ぼすという課題があった。そのため
封止樹脂の材料物性の選定や硬化条件の微妙な管理を必
要としていた。
However, in any of the above-mentioned conventional WB, TAB, MBB and COB mounting methods, a semiconductor bare chip and a connection portion thereof are protected by a sealing resin in order to protect the semiconductor bare chip and its connection portion from the external environment. It was necessary to seal. In the case of the WB method and the TAB method, there has been a problem that volume shrinkage during curing of the sealing resin remains as internal stress, which adversely affects connection reliability. Therefore, it is necessary to select the material properties of the sealing resin and delicately control the curing conditions.

【0006】さらに封止樹脂は内部にストレスを残存さ
せないように長い時間をかけてゆっくり硬化させる必要
があるため生産性が悪いという課題があった。MBB
法、COB法は実装する回路基板の平滑度が極めて高度
に要求され、かつ回路基板と半導体ベアチップの熱膨張
係数を近似させることが必要であり、結果的に高価にな
るという課題があった。
Further, the sealing resin needs to be slowly cured over a long period of time so as not to leave stress inside, and thus there is a problem that productivity is poor. MBB
The method and the COB method require a very high degree of smoothness of the circuit board to be mounted, and it is necessary to approximate the thermal expansion coefficients of the circuit board and the semiconductor bare chip.

【0007】一方、より薄型軽量でかつ筐体の曲面や隙
間に自由に配線できる可能性を有するFPCへの半導体
ベアチップの実装は基板の平滑度や熱膨張係数からMB
B法、COB法は適用できない。WB法、TAB法はF
PCへの適用は可能であるが封止樹脂の厚さを厳密に一
定化することは困難であり、前記したような課題を同様
に有するものである。
On the other hand, the mounting of a semiconductor bare chip on an FPC, which is thinner and lighter and has the possibility of being freely wired to the curved surface or gap of the housing, requires a smaller MB due to the smoothness and thermal expansion coefficient of the substrate.
The B method and COB method cannot be applied. WB method, TAB method is F
Although it can be applied to a PC, it is difficult to make the thickness of the sealing resin strictly constant, and thus has the same problems as described above.

【0008】本発明は上記課題を解決するものであり、
樹脂封止を必要とせず、安定した接続信頼性を得ること
ができる半導体チップ実装基板の製造方法を提供するこ
とを目的とする。
[0008] The present invention is to solve the above problems,
It is an object of the present invention to provide a method of manufacturing a semiconductor chip mounting board which does not require resin sealing and can obtain stable connection reliability.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明は、絶縁基体上に形成した第一の導電回路パタ
ーンの一部を除いて絶縁レジストでオーバーコートした
後、前記第一の導電回路パターンの一部に異方性導電接
着剤または導電性接着剤により半導体チップの片面に設
けられた電極を接着した第一の回路配線板と、他の絶縁
基体上に前記第一の回路配線板と対向させたときに前記
半導体チップのもう一方の片面上の各電極パッドに相当
する位置を少なくとも含む第二の導電回路パターンを形
成した後前記半導体チップのもう一方の片面の電極パッ
ドの相当する位置を除いて絶縁レジストでオーバーコー
トした第二の回路配線板とを対向させて、少なくとも前
記半導体チップ周辺部の前記絶縁レジストを前記半導体
チップを挟み込むように加圧加熱して接着させて前記第
二の導電回路パターンと前記半導体チップのもう一方の
片面の電極パッドとを接続させるものである。
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: overcoating with an insulating resist except for a part of a first conductive circuit pattern formed on an insulating substrate; A first circuit wiring board in which an electrode provided on one side of a semiconductor chip is adhered to a part of a conductive circuit pattern by an anisotropic conductive adhesive or a conductive adhesive; and the first circuit on another insulating base. After forming a second conductive circuit pattern including at least a position corresponding to each electrode pad on the other side of the semiconductor chip when facing the wiring board, the electrode pad on the other side of the semiconductor chip is formed. Except for the corresponding position, the second circuit wiring board overcoated with the insulating resist is opposed to sandwich the semiconductor chip with at least the insulating resist around the semiconductor chip. It is intended to connect the other side of the electrode pads of the semiconductor chip and the second electrically conductive circuit pattern are adhered by heating sea urchin pressurized and.

【0010】[0010]

【作用】したがって本発明によれば、第二の回路配線板
と半導体チップの各電極の電気的接続が基本的に圧接に
よってなされるために従来方法のように回路配線板の絶
縁基体と半導体チップの熱膨張率を厳密に合わせなくて
も常に圧接状態となり高い信頼性を得ることができる。
Therefore, according to the present invention, the electrical connection between the second circuit wiring board and each electrode of the semiconductor chip is basically made by pressure contact, so that the insulating base of the circuit wiring board and the semiconductor chip are different from the conventional method. Even if the coefficient of thermal expansion is not strictly adjusted, it is always in a pressed state, and high reliability can be obtained.

【0011】また、回路配線板と半導体チップの各電極
を接合した後の樹脂封止の必要性がないために内部応力
による障害を受けず接続信頼性を向上することができ、
さらに製造工程を極めて短縮することが可能となる。
In addition, since there is no need for resin sealing after joining the circuit wiring board and each electrode of the semiconductor chip, connection reliability can be improved without being affected by internal stress,
Further, the manufacturing process can be extremely shortened.

【0012】[0012]

【実施例】以下、本発明の一実施例における半導体チッ
プ実装基板の製造方法について図面を参照しながら説明
する。図1(a),(b)および(c)は本発明の一実
施例における半導体チップの実装方法を示す概略断面図
であり、(a)は第1の回路配線板、(b)は第2の回
路配線板、(c)は第1の回路配線板と第2の回路配線
板を貼り合わせた半導体チップ実装基板を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor chip mounting board according to an embodiment of the present invention will be described below with reference to the drawings. 1A, 1B and 1C are schematic sectional views showing a method for mounting a semiconductor chip according to one embodiment of the present invention, wherein FIG. 1A is a first circuit wiring board, and FIG. 2 shows a circuit board, and (c) shows a semiconductor chip mounting board in which a first circuit board and a second circuit board are bonded together.

【0013】図1(a)に示すように、絶縁基体1上に
形成された第一の導電回路パターン2a,2b,2cの
一部を露出させて絶縁レジスト3でオーバーコートし、
導電回路パターン2aの露出部に導電性接着剤4を塗布
し、半導体チップ5の片面に設けられた電極を接着して
第一の回路配線板を形成する。
As shown in FIG. 1A, a part of the first conductive circuit patterns 2a, 2b, 2c formed on the insulating base 1 is exposed and overcoated with an insulating resist 3.
A conductive adhesive 4 is applied to an exposed portion of the conductive circuit pattern 2a, and an electrode provided on one surface of the semiconductor chip 5 is bonded to form a first circuit wiring board.

【0014】つぎに図1(b)に示すように、絶縁基体
6上に、第一の回路配線板と対向させたときに半導体チ
ップ5のもう一方の片面に設けられている電極パッド5
c,5dに相当する位置7c,7dを少なくとも含む第
二の導電回路パターン7a,7bを形成し、半導体チッ
プ5のもう一方の片面上の電極パッド5c,5dに相当
する導電回路パターン7a,7bのそれぞれの位置7
c,7dを少なくとも露出させて絶縁レジスト8をオー
バーコートした第二の回路配線板を形成する。なお、本
実施例において絶縁基体6はフレキシブル性を有するも
のを使用したが、本発明の第一の回路配線板および第二
の回路配線板のそれぞれ絶縁基体1および6は両方と
も、またはいずれか一方がフレキシブル性を有するもの
を使用することができ、かつ絶縁レジスト3および8は
両方またはそのいずれか一方が熱可塑性を有する接着剤
または熱硬化性を有する接着剤を用いることができる。
Next, as shown in FIG. 1B, an electrode pad 5 provided on the other side of the semiconductor chip 5 when facing the first circuit wiring board on the insulating base 6.
Second conductive circuit patterns 7a and 7b including at least positions 7c and 7d corresponding to c and 5d are formed, and conductive circuit patterns 7a and 7b corresponding to the electrode pads 5c and 5d on the other surface of the semiconductor chip 5 are formed. Each position 7 of
A second circuit wiring board is formed by overcoating the insulating resist 8 by exposing at least c and 7d. Although the insulating substrate 6 used in this example has flexibility, the insulating substrates 1 and 6 of the first circuit wiring board and the second circuit wiring board of the present invention may be either or both. One having flexibility can be used, and as the insulating resists 3 and 8, both or one of them can be an adhesive having thermoplasticity or an adhesive having thermosetting properties.

【0015】つぎに上記のように構成した第一の回路配
線板(a)および第二の回路配線板(b)を対向させ、
図1(c)に示すように少なくとも半導体チップ5の周
辺部の絶縁レジスト3および8を半導体チップ5を挟み
込むように加圧加熱して接着させて第二の導電回路パタ
ーン7c,7dと半導体チップ5の電極パッド5c,5
dを圧接させる。
Next, the first circuit wiring board (a) and the second circuit wiring board (b) configured as described above are opposed to each other,
As shown in FIG. 1 (c), at least the insulating resists 3 and 8 at the peripheral portion of the semiconductor chip 5 are pressed and heated so as to sandwich the semiconductor chip 5, and are adhered to the second conductive circuit patterns 7c and 7d. 5 electrode pads 5c, 5
d is pressed.

【0016】第二の導電回路パターン7a,7bの一端
は、異方性導電接着剤9、または圧接によって第一の導
電回路パターン2bに接続され、配線回路の外部への導
出は第一の導電回路パターン2bを用いて行うことがで
きる。なお、異方性導電接着剤9に代えて半田または導
電接着剤を使用することも可能である。
One end of each of the second conductive circuit patterns 7a and 7b is connected to the first conductive circuit pattern 2b by an anisotropic conductive adhesive 9 or press contact. This can be performed using the circuit pattern 2b. In addition, it is also possible to use solder or a conductive adhesive instead of the anisotropic conductive adhesive 9.

【0017】半導体チップ5がLEDの場合は第二の回
路配線板の絶縁基体6を透明または半透明とし、絶縁レ
ジスト3および8をなくすかまたは絶縁レジスト3およ
び8も透明または半透明とすることにより照光が可能で
あり、さらに図2に示すように第二の回路配線板の絶縁
基体6にLEDを中心として凹凸部10を形成すること
により効率的な光の拡散を得ることができ、第二の回路
配線板にLEDの接続、物理的保護および光の拡散照光
等、多くの機能を一括して持たせることが可能となる。
When the semiconductor chip 5 is an LED, the insulating base 6 of the second circuit wiring board is made transparent or translucent, and the insulating resists 3 and 8 are eliminated or the insulating resists 3 and 8 are also made transparent or translucent. 2 can be illuminated. Further, as shown in FIG. 2, by forming the uneven portion 10 around the LED on the insulating base 6 of the second circuit wiring board, efficient light diffusion can be obtained. Many functions such as LED connection, physical protection and light diffusion illumination can be collectively provided to the two circuit wiring boards.

【0018】半導体チップ5の形状が大きい場合は物理
的補強のため第一または第二の回路配線板の裏面に補強
板(図示せず)を貼り付けるか第二の回路配線板の絶縁
基体6の剛性を第一の回路配線板の剛性より高く設定す
ることが半導体チップ5の各電極パッドと第二の回路基
板の対応する各電極の接続安定化のために望ましい。さ
らに高い接続信頼性を確保するために、半導体チップ5
の各電極パッド材料として金を使用するかまたは金メッ
キ、金ワイヤ線の超音波加熱融着等の方法により金バン
プを設けるか、第二の回路配線板の対応する電極位置に
半導体チップ5と同様の方法により金バンプを設ける
か、または金レジン系ペーストをスクリーン印刷等によ
り金−レジンバンプを形成することが可能である。
When the shape of the semiconductor chip 5 is large, a reinforcing plate (not shown) is attached to the back surface of the first or second circuit wiring board for physical reinforcement, or the insulating substrate 6 of the second circuit wiring board is provided. Is preferably set higher than the rigidity of the first circuit wiring board in order to stabilize the connection between each electrode pad of the semiconductor chip 5 and each corresponding electrode of the second circuit board. To ensure higher connection reliability, the semiconductor chip 5
Using gold as a material of each electrode pad, or providing gold bumps by gold plating, ultrasonic heating and fusion of gold wire lines, or the same as the semiconductor chip 5 at the corresponding electrode position of the second circuit wiring board It is possible to form a gold-resin bump by providing a gold bump by the method described above, or by screen-printing a gold-resin-based paste.

【0019】第一および第二の回路配線板間には部分的
に微小な隙間が生じるため使用する絶縁基体1および6
として透湿性のない、または透湿性の低い材料を使用す
ることが必要である。
Since a minute gap is partially formed between the first and second circuit wiring boards, the insulating bases 1 and 6 used are used.
It is necessary to use a material having no or low moisture permeability.

【0020】第一および第二の回路配線板の接着は前記
したように加圧加熱によって行われるものであり、第一
および第二の回路配線板の絶縁レジスト3および8が両
方ともに加圧加熱により接着性を有する材料である必然
性はなく、そのいずれか一方が加圧加熱により接着性を
有する材料であり、他方はレジストがないかまたは加圧
加熱による接着性を有しない材料であってもよい。加圧
加熱条件は使用する絶縁レジスト材料または絶縁基体材
料によって異なるが、直接加熱する場合一般に少なくと
も100℃以上で2〜10秒間以上加熱することが接着
後の信頼性を確保するために必要である。加熱時間は超
音波加熱または高周波誘導加熱を適用することにより
0.05〜1秒以内に短縮することも可能である。
The first and second circuit boards are bonded by pressure and heating as described above, and both the insulating resists 3 and 8 of the first and second circuit boards are pressed and heated. It is not necessary to use a material having adhesiveness due to pressure and heating, and the other is a material having no resist or having no adhesiveness due to pressure and heat. Good. The heating conditions under pressure vary depending on the insulating resist material or insulating base material used, but in the case of direct heating, it is generally necessary to heat at least 100 ° C. or more for 2 to 10 seconds or more in order to ensure reliability after bonding. . The heating time can be reduced to within 0.05 to 1 second by applying ultrasonic heating or high-frequency induction heating.

【0021】(実施例1)つぎに図2を用いて本発明の
第一の実施例についてさらに詳しく説明する。
(Embodiment 1) Next, a first embodiment of the present invention will be described in more detail with reference to FIG.

【0022】厚さ75μmのポリ塩化ビニリデン(PV
DC)コート2軸延伸ポリエチレンテレフタレートフィ
ルムよりなる絶縁基体1に銀レジン系ペースト(東洋紡
製DW−250H)により所定パターンの第一の導電回
路パターン2をスクリーン印刷形成し、150℃のIR
炉で2分間乾燥した。次いでLEDチップ5を配置する
部分および外部導出用テール部分を除いて加熱接着性の
絶縁レジスト3(藤倉化成製XB−804)を同様に形
成した後、導電性接着剤4(藤倉化成製FA−707)
を塗布し、LEDチップ5を接着、150℃の温度で1
0分間乾燥して第一の回路配線板を作製した。
Polyvinylidene chloride having a thickness of 75 μm (PV
DC) A first conductive circuit pattern 2 having a predetermined pattern is screen-printed and formed with a silver resin-based paste (Toyobo DW-250H) on an insulating substrate 1 made of a coated biaxially stretched polyethylene terephthalate film.
Dry in oven for 2 minutes. Next, a heat-adhesive insulating resist 3 (XB-804 manufactured by Fujikura Kasei) is formed in the same manner except for a portion where the LED chip 5 is arranged and a tail portion for external lead-out, and then a conductive adhesive 4 (FA-Facil manufactured by Fujikura Kasei) is used. 707)
Is applied, and the LED chip 5 is adhered.
After drying for 0 minutes, a first circuit wiring board was prepared.

【0023】つぎに厚さ300μmのアクリル板よりな
る絶縁基体6上のLEDチップ5の電極対応位置を含む
所定パターンを銀レジン系ペースト(同上)により第二
の導電回路7を印刷形成し、LEDチップ5の電極対応
位置を除いて絶縁レジスト8を印刷形成した。さらにL
EDチップ5の周囲の第二の導電回路7を除く部分にピ
ッチ100μm、断面角度30度の連続的な凹凸部10
を設けた第二の回路配線板を作製した。
Next, a second conductive circuit 7 is formed by printing a predetermined pattern including a position corresponding to the electrode of the LED chip 5 on the insulating substrate 6 made of an acrylic plate having a thickness of 300 μm using a silver resin-based paste (same as above). The insulating resist 8 was formed by printing except for the position corresponding to the electrode of the chip 5. Further L
A continuous uneven portion 10 having a pitch of 100 μm and a cross-sectional angle of 30 degrees is formed in a portion around the ED chip 5 except for the second conductive circuit 7.
The second circuit wiring board provided with was manufactured.

【0024】つぎに第一および第二の回路配線板を対向
させてLEDチップ5の周囲を圧力15kgf/cm2、温
度150℃で4秒間加圧加熱し、接着させた。
Next, the first and second circuit wiring boards were opposed to each other, and the periphery of the LED chip 5 was pressurized and heated at a pressure of 15 kgf / cm 2 and a temperature of 150 ° C. for 4 seconds to be bonded.

【0025】このように作製した試料の接続信頼性を確
認するため、 i)85℃高温槽内1000時間、 ii)60℃90〜95%RH高温高湿槽中1000時
間、 iii)85℃1時間、−40℃1時間を1サイクルとし
て500サイクル中に、それぞれ放置した後、LEDの
輝度、VF特性を測定したがいずれも異常はなかった。
また第二の回路配線板に連続的な凹凸部10を設けない
ものに比較して輝度は30%向上した。
In order to confirm the connection reliability of the thus prepared sample, i) 1000 hours in a high temperature and high temperature chamber at 85 ° C., ii) 1000 hours in a high temperature and high humidity chamber at 60 ° C. and 95% RH, iii) 85 ° C. After standing for 500 cycles, each of which was performed for one cycle at -40 ° C. for one hour, the brightness and VF characteristics of the LED were measured.
Further, the luminance was improved by 30% as compared with the case where the continuous uneven portion 10 was not provided on the second circuit wiring board.

【0026】(実施例2)つぎに図3を用いて本発明の
第二の実施例について説明する。
(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIG.

【0027】厚さ35μmの銅箔貼り25μm厚ポリイ
ミドフィルムよりなる絶縁基体1の電極ランド部分に導
電性接着剤(藤倉化成製SA−0426)を塗布して第
一の導電回路2aを形成し、その上にマイコンチップ5
を接着した状態で200℃、30秒間硬化させて第一の
回路配線板を作製した。なお、マイコンチップ5および
その他の部品実装部分を除いて絶縁レジスト3(四国化
成製CF−30G)をオーバーコートした。またマイコ
ンチップ5の電極パッドにはあらかじめ金バンプ11を
形成しておいた。
A first conductive circuit 2a is formed by applying a conductive adhesive (SA-0426 manufactured by Fujikura Kasei) to the electrode land portions of the insulating substrate 1 made of a 25 μm thick polyimide film pasted with a 35 μm thick copper foil, On top of that, a microcomputer chip 5
Was cured at 200 ° C. for 30 seconds to form a first circuit wiring board. The insulating resist 3 (CF-30G manufactured by Shikoku Chemicals Co., Ltd.) was overcoated except for the microcomputer chip 5 and other component mounting parts. The gold bumps 11 were formed on the electrode pads of the microcomputer chip 5 in advance.

【0028】つぎに厚さ0.6mmの4層配線銅貼りガラ
スエポキシ積層基板よりなる絶縁基体6のマイコンチッ
プ5の電極対応位置にニッケル下地金メッキよりなる第
二の導電回路パターン7a,7bを形成し、マイコンチ
ップ5の電極対応位置を除いて(表1)に示す加熱接着
性の絶縁レジスト8を印刷形成して第二の回路配線板を
作製した。
Next, second conductive circuit patterns 7a and 7b made of nickel-base gold plating are formed at positions corresponding to the electrodes of the microcomputer chip 5 on the insulating base 6 made of a four-layer wiring copper-clad glass epoxy laminated substrate having a thickness of 0.6 mm. Then, except for the positions corresponding to the electrodes of the microcomputer chip 5, the insulating adhesive 8 having heat adhesion shown in (Table 1) was formed by printing to produce a second circuit wiring board.

【0029】つぎに第一および第二の回路配線板を対向
させてマイコンチップ5の周囲を圧力15kgf/cm2
温度190℃で4秒間加圧加熱し、接着させた。さらに
本実施例ではマイコンチップ5の形状が大きいため、絶
縁基体6のマイコンチップ5の位置に相当する裏面に接
着剤12を介して補強板13を貼り付けて接続信頼性を
向上させている。
Next, a pressure of 15 kgf / cm 2 is applied around the microcomputer chip 5 with the first and second circuit wiring boards facing each other .
Pressure bonding and heating were performed at a temperature of 190 ° C. for 4 seconds for bonding. Further, in this embodiment, since the microcomputer chip 5 has a large shape, a reinforcing plate 13 is attached via an adhesive 12 to a back surface of the insulating base 6 corresponding to the position of the microcomputer chip 5 to improve connection reliability.

【0030】このように作製した試料の接続信頼性を確
認するため、 i)85℃高温槽内1000時間、 ii)60℃90〜95%RH高温高湿槽中1000時
間、 iii)85℃1時間、−40℃1時間を1サイクルとし
て500サイクル中に、それぞれ放置した後、マイコン
の動作状態を確認した結果、いずれの試験環境条件下に
おいて異常は発生しなかった。
In order to confirm the connection reliability of the sample thus prepared, i) 1000 hours in a high temperature and high humidity chamber at 85 ° C., ii) 1000 hours in a high temperature and high humidity chamber at 60 ° C. and 95% RH, iii) 85 ° C. The operation state of the microcomputer was confirmed after standing for 500 cycles, each of which was a cycle of 1 hour at -40 ° C. for 1 hour. As a result, no abnormality occurred under any of the test environment conditions.

【0031】[0031]

【表1】 [Table 1]

【0032】(実施例3)実施例1における第一および
第二の回路配線板を対向させて加圧加熱し接着する代わ
りに超音波ホーンで35kgf/cm2加圧し、20kHzで
0.2秒間超音波加熱溶着して第三の実施例を作製した
が、本試料においても実施例1と同じ信頼性を得ること
ができた。
(Example 3) Instead of bonding the first and second circuit wiring boards in Example 1 with each other by pressing and heating and bonding them, 35 kgf / cm 2 is pressed with an ultrasonic horn and 0.2 kHz at 20 kHz. The third example was manufactured by ultrasonic heating and welding, and the same reliability as in Example 1 was obtained with this sample.

【0033】(実施例4)実施例2において、マイコン
チップ5の電極パッドとして金バンプは形成せず、金蒸
着とし、また第二の回路配線板の対応する電極位置に
(表2)に示す金ペーストをスクリーン印刷して180
℃、3分間乾燥した。乾燥状態では膜厚30μmであっ
たがこの試料を実施例2と同様に加圧加熱接着し、特性
を測定したところ同様の信頼性を得ることができた。
(Embodiment 4) In Embodiment 2, gold bumps are not formed as electrode pads of the microcomputer chip 5, gold is deposited, and the corresponding electrode positions on the second circuit wiring board are shown in (Table 2). Screen printing of gold paste 180
C. and dried for 3 minutes. Although the film thickness was 30 μm in the dry state, this sample was pressure-heated and bonded in the same manner as in Example 2, and the characteristics were measured. As a result, the same reliability could be obtained.

【0034】[0034]

【表2】 [Table 2]

【0035】[0035]

【発明の効果】上記実施例より明らかなように本発明に
よれば、半導体部品の物理的保護のための樹脂封止を行
う必要がなく、そのため封止樹脂の内部ストレスによる
半導体部品への障害もなく短時間に接続作業を行うこと
が可能となる。さらに第二の回路配線板との接続が圧接
によるものであるため導体部品と絶縁基体の熱膨張率を
厳密に合わせる必要がなく、安定した接続信頼性を得る
ことができる。
As is apparent from the above embodiment, according to the present invention, there is no need to perform resin sealing for physical protection of the semiconductor component, and therefore, there is no obstacle to the semiconductor component due to internal stress of the sealing resin. It is possible to perform the connection work in a short time without any. Furthermore, since the connection with the second circuit wiring board is made by pressure welding, there is no need to strictly match the thermal expansion coefficients of the conductor component and the insulating base, and stable connection reliability can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例における半導体チップ実装基
板の製造方法を示す部分断面図
FIG. 1 is a partial cross-sectional view illustrating a method for manufacturing a semiconductor chip mounting board according to an embodiment of the present invention.

【図2】本発明の第一の実施例の半導体チップ実装基板
の製造方法によって作製された半導体チップ実装基板の
部分断面図
FIG. 2 is a partial cross-sectional view of the semiconductor chip mounting board manufactured by the method for manufacturing a semiconductor chip mounting board according to the first embodiment of the present invention;

【図3】同第二の実施例の製造方法によって作製された
半導体チップ実装基板の部分断面図
FIG. 3 is a partial cross-sectional view of a semiconductor chip mounting substrate manufactured by the manufacturing method of the second embodiment.

【符号の説明】[Explanation of symbols]

1 絶縁基体 2a,2b,2c 第一の導電回路パターン 3 絶縁レジスト 4 導電性接着剤 5 マイコンチップ(半導体チップ) 6 他の絶縁基体 7a,7b,7c,7d 第二の導電回路パターン 8 絶縁レジスト 9 異方性導電接着剤 DESCRIPTION OF SYMBOLS 1 Insulating base 2a, 2b, 2c First conductive circuit pattern 3 Insulating resist 4 Conductive adhesive 5 Microcomputer chip (semiconductor chip) 6 Other insulating bases 7a, 7b, 7c, 7d Second conductive circuit pattern 8 Insulating resist 9 Anisotropic conductive adhesive

フロントページの続き (56)参考文献 特開 平4−369846(JP,A) 特開 平5−198694(JP,A) 特開 昭55−43871(JP,A) 特開 平3−73559(JP,A) 特開 平6−151635(JP,A) 特開 平7−94861(JP,A) 実開 昭52−159163(JP,U) 実開 平1−110469(JP,U) 実開 平3−6867(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 23/00 H01L 23/12 H01L 21/60 Continuation of the front page (56) References JP-A-4-369846 (JP, A) JP-A-5-198694 (JP, A) JP-A-55-43871 (JP, A) JP-A-3-73559 (JP, A) JP-A-6-151635 (JP, A) JP-A-7-94861 (JP, A) JP-A 52-159163 (JP, U) JP-A 1-110469 (JP, U) 3-6867 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 23/00 H01L 23/12 H01L 21/60

Claims (12)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁基体上に形成した第一の導電回路パ
ターンの一部を除いて絶縁レジストでオーバーコートし
た後、前記第一の導電回路パターンの一部に異方性導電
接着剤または導電性接着剤により半導体チップの片面に
設けられた電極を接着した第一の回路配線板と、他の絶
縁基体上に前記第一の回路配線板と対向させたときに前
記半導体チップのもう一方の片面上の各電極パッドに相
当する位置を少なくとも含む第二の導電回路パターンを
形成した後、前記半導体チップのもう一方の片面の電極
パッドの相当する位置を除いて絶縁レジストでオーバー
コートした第二の回路配線板とを対向させて、少なくと
も前記半導体チップ周辺部の前記絶縁レジストを前記半
導体チップを挟み込むように加圧加熱して接着させて前
記第二の導電回路パターンと前記半導体チップのもう一
方の片面の電極パッドとを接続させる半導体チップ実装
基板の製造方法。
1. After overcoating with an insulating resist except for a part of a first conductive circuit pattern formed on an insulating substrate, an anisotropic conductive adhesive or conductive material is applied to a part of the first conductive circuit pattern. A first circuit wiring board to which electrodes provided on one side of a semiconductor chip are adhered by a conductive adhesive, and the other of the semiconductor chip when facing the first circuit wiring board on another insulating substrate. After forming the second conductive circuit pattern including at least the position corresponding to each electrode pad on one surface, the second overcoated with an insulating resist except for the position corresponding to the electrode pad on the other one surface of the semiconductor chip The second conductive circuit board by pressing and heating at least the insulating resist at the peripheral portion of the semiconductor chip so as to sandwich the semiconductor chip. A method for manufacturing a semiconductor chip mounting board, wherein a turn is connected to an electrode pad on the other side of the semiconductor chip.
【請求項2】 絶縁基体または他の絶縁基体の少なくと
もいずれか一方が可撓性を有する絶縁基体である請求項
1記載の半導体チップ実装基板の製造方法。
2. The method according to claim 1, wherein at least one of the insulating base and the other insulating base is a flexible insulating base.
【請求項3】 絶縁基体または他の絶縁基体がポリ塩化
ビニリデンコート2軸延伸ポリエチレンテレフタレート
またはアクリルよりなる絶縁基体または他の絶縁基体で
ある請求項1記載の半導体チップ実装基板の製造方法。
3. The method according to claim 1, wherein the insulating substrate or another insulating substrate is an insulating substrate made of polyvinylidene chloride-coated biaxially stretched polyethylene terephthalate or acrylic or another insulating substrate.
【請求項4】 第一の導電回路パターンをオーバーコー
トするための絶縁レジストまたは第二の導電回路パター
ンをオーバーコートするための絶縁レジストの少なくと
もいずれか一方が加熱接着性を有する絶縁レジストであ
る請求項1記載の半導体チップ実装基板の製造方法。
4. An insulating resist for overcoating a first conductive circuit pattern or at least one of an insulating resist for overcoating a second conductive circuit pattern is an insulating resist having heat adhesion. Item 2. The method for manufacturing a semiconductor chip mounting substrate according to Item 1.
【請求項5】 異方性導電接着剤または導電性接着剤に
代えて半田または圧接により第一の導電回路パターンの
一部と半導体チップの片面に設けられた電極とを接続す
る請求項1記載の半導体チップ実装基板の製造方法。
5. The method according to claim 1, wherein a part of the first conductive circuit pattern is connected to an electrode provided on one surface of the semiconductor chip by soldering or pressure welding instead of the anisotropic conductive adhesive or the conductive adhesive. Manufacturing method of a semiconductor chip mounting substrate.
【請求項6】 半導体チップがLEDであり、少なくと
も第二の回路配線板を形成する他の絶縁基体および絶縁
レジストが透明または半透明である請求項1,2,3,
4または5記載の半導体チップ実装基板の製造方法。
6. The semiconductor chip is an LED, and at least another insulating base and an insulating resist forming the second circuit wiring board are transparent or translucent.
6. The method for manufacturing a semiconductor chip mounting board according to 4 or 5.
【請求項7】 第二の導電回路パターンと接続する半導
体チップの電極パッドが金よりなる電極パッドである
か、または前記電極パッド上に金バンプを形成した電極
パッドである請求項1記載の半導体チップ実装基板の製
造方法。
7. The semiconductor according to claim 1, wherein the electrode pad of the semiconductor chip connected to the second conductive circuit pattern is an electrode pad made of gold or an electrode pad formed with a gold bump on the electrode pad. Manufacturing method of chip mounting board.
【請求項8】 半導体チップの電極パッドと接続する第
二の導電回路パターン上に金バンプを形成するか、また
は金粉−レジン系の導電ペーストでパターン印刷して金
−レジンバンプを形成する請求項1記載の半導体チップ
実装基板の製造方法。
8. A gold-resin bump is formed on a second conductive circuit pattern connected to an electrode pad of a semiconductor chip, or a gold-resin bump is formed by pattern printing with a gold powder-resin-based conductive paste. The manufacturing method of the semiconductor chip mounting board as described in the above.
【請求項9】 加圧加熱に超音波または高周波を用いる
請求項1記載の半導体チップ実装基板の製造方法。
9. The method according to claim 1, wherein an ultrasonic wave or a high frequency wave is used for heating under pressure.
【請求項10】 第一または第二の回路配線板の絶縁基
体の裏面に補強板を貼り付けた請求項1記載の半導体チ
ップ実装基板の製造方法。
10. The method for manufacturing a semiconductor chip mounting board according to claim 1, wherein a reinforcing plate is attached to the back surface of the insulating base of the first or second circuit wiring board.
【請求項11】 LED周辺部の第二の回路配線板の表
面に連続的な凹凸部を形成した請求項5記載の半導体チ
ップ実装基板の製造方法。
11. The method for manufacturing a semiconductor chip mounting board according to claim 5, wherein a continuous uneven portion is formed on the surface of the second circuit wiring board around the LED.
【請求項12】 第一の回路配線板を構成する絶縁基体
の剛性より第二の回路配線板を構成する絶縁基体の剛性
を高くした請求項1記載の半導体チップ実装基板の製造
方法。
12. The method according to claim 1, wherein the rigidity of the insulating base forming the second circuit wiring board is higher than the rigidity of the insulating base forming the first circuit wiring board.
JP9129994A 1994-04-28 1994-04-28 Method for manufacturing semiconductor chip mounting board Expired - Fee Related JP3106846B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9129994A JP3106846B2 (en) 1994-04-28 1994-04-28 Method for manufacturing semiconductor chip mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9129994A JP3106846B2 (en) 1994-04-28 1994-04-28 Method for manufacturing semiconductor chip mounting board

Publications (2)

Publication Number Publication Date
JPH07297317A JPH07297317A (en) 1995-11-10
JP3106846B2 true JP3106846B2 (en) 2000-11-06

Family

ID=14022598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9129994A Expired - Fee Related JP3106846B2 (en) 1994-04-28 1994-04-28 Method for manufacturing semiconductor chip mounting board

Country Status (1)

Country Link
JP (1) JP3106846B2 (en)

Also Published As

Publication number Publication date
JPH07297317A (en) 1995-11-10

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