JPH0744202B2 - Chip mounting method - Google Patents
Chip mounting methodInfo
- Publication number
- JPH0744202B2 JPH0744202B2 JP62323146A JP32314687A JPH0744202B2 JP H0744202 B2 JPH0744202 B2 JP H0744202B2 JP 62323146 A JP62323146 A JP 62323146A JP 32314687 A JP32314687 A JP 32314687A JP H0744202 B2 JPH0744202 B2 JP H0744202B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- circuit wiring
- mounting method
- protective plate
- chip mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は各種電子機器に使用されるチップの実装方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip mounting method used in various electronic devices.
従来の技術 従来、チップの実装は、銅箔付ガラスクロス積層板等を
エッチング法により導電回路を形成し、導電性接着剤で
回路配線の一部にチップを接着せしめ、チップ表面の電
極部と回路配線とを金線で接続するいわゆるワイヤーボ
ンディング法が良く知られている。金線はチップの電極
部と配線回路間にブリッジ構造になっているため、機械
的強度は極めて弱く、そのためにチップと金線全体を絶
縁性樹脂でモールドする必要がある。Conventional technology Conventionally, in the mounting of chips, a conductive circuit is formed by etching a glass cloth laminated plate with copper foil, etc., and the chip is bonded to a part of the circuit wiring with a conductive adhesive, and the electrodes on the chip surface are connected. A so-called wire bonding method for connecting a circuit wiring to a gold wire is well known. Since the gold wire has a bridge structure between the electrode portion of the chip and the wiring circuit, the mechanical strength is extremely weak. Therefore, it is necessary to mold the entire chip and gold wire with an insulating resin.
発明が解決しようとする問題点 しかしながら、ワイヤーボンディング法では電極部数の
多い半導体チップを多数個実装する場合や、発光ダイオ
ードを、面照光を目的として多数個を実装する場合、接
続ケ所が多いために、多大の時間を要し、さらに使用す
る金線の量も多いことから安価に製造することが困難で
あった。さらにワイヤボンディング法の場合は金の細線
を用いるためにチップの電極部と回路配線の接続部は近
接して設置させる必要性があり、回路設計の自由度をそ
こなうことも多かった。Problems to be Solved by the Invention However, in the wire bonding method, when mounting a large number of semiconductor chips with a large number of electrode parts, or when mounting a large number of light emitting diodes for the purpose of surface illumination, there are many connection points. However, it takes a lot of time, and since the amount of gold wire used is large, it is difficult to manufacture at low cost. Further, in the case of the wire bonding method, since the gold fine wire is used, it is necessary to place the electrode portion of the chip and the connection portion of the circuit wiring close to each other, which often impairs the degree of freedom in circuit design.
問題点を解決するための手段 本発明は、チップを導電性接着剤等で基体上の回路配線
に接着せしめる工程までは従来と同一であるが、チップ
表面の電極部と回路配線との電気的接続を、スクリーン
印刷等により、導電性塗料で一括してパターン印刷形成
することにより、安価に製造し得る実装方法を提供せん
とするものである。詳述するならば、本発明は少なくと
も表面部分が絶縁性の基体上に回路配線を形成し、回路
配線上に導電性または絶縁性接着剤または半田付けによ
って、任意個数のチップを接着し、保護板をチップ表面
に密着させた状態で保護板と回路配線のすき間に絶縁性
樹脂を注入して固化させる。この後、保護板を取りはず
せばチップ表面の電極部と回路配線の一部は急な段差の
ない、スクリーン印刷等での印刷が可能な平面が得られ
る。このチップ表面の電極部と露出した回路配線をスク
リーン印刷等でパターニングされた導電塗膜を一括して
形成する。Means for Solving the Problems The present invention is the same as the conventional method up to the step of adhering the chip to the circuit wiring on the substrate with a conductive adhesive or the like, but the electrical connection between the electrode portion on the surface of the chip and the circuit wiring is It is an object of the present invention to provide a mounting method that can be manufactured at low cost by collectively forming a pattern of conductive paint by screen printing or the like by screen printing or the like. More specifically, the present invention forms a circuit wiring on a substrate whose surface portion is at least insulative, and adheres and protects an arbitrary number of chips on the circuit wiring with a conductive or insulating adhesive or soldering. Insulating resin is injected into the gap between the protective plate and the circuit wiring while the plate is in close contact with the surface of the chip to solidify. After that, if the protective plate is removed, a flat surface that can be printed by screen printing or the like can be obtained without a steep step between the electrode portion on the chip surface and a part of the circuit wiring. The electrode portions on the chip surface and the exposed circuit wiring are collectively formed with a conductive coating film patterned by screen printing or the like.
作用 本発明によれば、スクリーン印刷法等により、一括して
接続が可能となるため、電極部の数が多ければ多い程、
接続の短期間化がはかられ、さらに高価な金線も不要と
なるため、極めて大きな経済的効果を有する。また、金
の細線による接続と異なり、絶縁性樹脂上に塗布された
導電塗膜による接続になるため、チップの電極部と回路
配線の接続部は従来のように近接させる必然性は無く、
回路設計の自由度も大となる。Effect According to the present invention, since it is possible to collectively connect by the screen printing method or the like, the greater the number of electrode portions,
Since the connection can be shortened and an expensive gold wire is unnecessary, it has an extremely large economic effect. In addition, unlike the connection using a thin gold wire, the connection is made by a conductive coating film coated on the insulating resin, so there is no need to bring the electrode part of the chip and the connection part of the circuit wiring close to each other as in the conventional case.
The degree of freedom in circuit design is also great.
さらには、接続用の導電塗膜は、酸化スズ系や、アンチ
モンドープインジュム系の透明な導電塗膜で形成するこ
とも可能であり、発光ダイオードの接続にも適した工法
が得られる。Furthermore, the conductive coating film for connection can be formed of a transparent conductive coating film of tin oxide type or antimony-doped indium type, and a method suitable for connecting light emitting diodes can be obtained.
実施例 本実施例は第１図のごとく少なくとも表面部分が絶縁性
の基体１上に回路配線2,2aを形成し、回路配線2a上に導
電性または絶縁性接着剤または半田付け３によって、任
意個数のチップ４を接着し、保護板５をチップ表面と回
路配線２の一部に密着させる。そしてこの状態で保護板
５と回路配線2,2aのすき間に絶縁性樹脂６を注入して固
化させる。この後、第２図のごとく保護板５を取りはず
せばチップ４表面の電極部4aと回路配線２の一部は急な
段差のない、スクリーン印刷等での印刷が可能な平面が
得られる。次に第３図のごとくこのチップ表面の電極部
4aと露出した回路配線２をスクリーン印刷等でパターニ
ングされた導電塗膜７を一括して形成する。絶縁性樹脂
６は、基体１およびチップ４側面に対して接着性を有す
る熱硬化性樹脂であることが最も望ましい。なぜなら
ば、チップ４あるいは回路配線2,2aと絶縁性樹脂６の界
面が熱ショック等で剥れ、両者を接続している導電塗膜
７が切断されるからである。熱可塑性樹脂を用いる場合
には、チップ４あるいは回路配線2,2aに対する接着性が
弱いため樹脂の流れ方向の線膨張率が４×10-5cm/℃以
下で、かつ吸水率が0.15％以下でないと、前記の理由に
より、導電塗膜７が切断される可能性がある。保護板５
の材質は金属でも、セラミック系でも固形樹脂でも良い
が、チップ表面や回路配線の一部を密着させた時、わず
かのすき間ができると、絶縁樹脂６を注入した際に毛細
管現象により入り込んでしまうため、少なくとも各密着
部分はシリコン系ゴム等でライニングして密着性を確保
するのが良い。一般的には従来工法であるワイヤボンデ
ィングの場合、チップ表面の電極ランド部の材質はAlで
あることが多いが、酸化し易いため電気的接続の信頼度
を充分確保するためには電極ランド部の材質はAU等の貴
金属にすることが望ましい。Example In this example, as shown in FIG. 1, the circuit wiring 2, 2a is formed on at least the surface of the insulating substrate 1, and the conductive or insulative adhesive or the soldering 3 is used on the circuit wiring 2a. A number of chips 4 are adhered, and the protective plate 5 is brought into close contact with the chip surface and a part of the circuit wiring 2. Then, in this state, the insulating resin 6 is injected into the gap between the protective plate 5 and the circuit wirings 2, 2a to be solidified. After that, if the protective plate 5 is removed as shown in FIG. 2, the electrode portion 4a on the surface of the chip 4 and a part of the circuit wiring 2 have a steep step and a flat surface which can be printed by screen printing or the like is obtained. Next, as shown in Fig. 3, the electrode part on the surface of this chip
4a and the exposed circuit wiring 2 are collectively formed with a conductive coating film 7 patterned by screen printing or the like. Most preferably, the insulating resin 6 is a thermosetting resin having adhesiveness to the side surfaces of the base 1 and the chip 4. This is because the interface between the chip 4 or the circuit wirings 2 and 2a and the insulating resin 6 is peeled off by heat shock or the like, and the conductive coating film 7 connecting them is cut. When a thermoplastic resin is used, the linear expansion coefficient in the resin flow direction is 4 × 10 -5 cm / ° C or less and the water absorption rate is 0.15% or less because the adhesiveness to the chip 4 or the circuit wiring 2, 2a is weak. Otherwise, the conductive coating film 7 may be cut due to the above reason. Protective plate 5
The material of may be metal, ceramic or solid resin, but if a small gap is made when the chip surface or part of the circuit wiring is adhered, it will enter due to the capillary phenomenon when the insulating resin 6 is injected. Therefore, it is preferable that at least each contact portion is lined with a silicone rubber or the like to secure the adhesion. Generally, in the case of wire bonding, which is a conventional method, the material of the electrode land part on the chip surface is often Al, but since it easily oxidizes, the electrode land part must be secured in order to secure sufficient reliability of electrical connection. It is desirable to use a precious metal such as AU for the material.
以下、さらに具体的な実施例を説明する。Hereinafter, more specific examples will be described.
材厚1.6mmのガラスエポキシ基板を用い、30×30mmのサ
イズで銅箔によるプリント回路配線板を作製し、面照光
を目的として36個のLEDチップを等間隔になるように導
電性接着剤で回路配線上に接着した。次に、各チップ表
面および、接続を要する回路配線部分に密着し得るよう
に、表面に0.2mmのシリコンゴムライニングした金属の
保護板５を作製し、各チップ表面と接続する回路配線部
2aに密着させて、エポキシ樹脂を真空引きしつつ回路板
2,2aと保護板５のすき間に注入し120℃90秒間で硬化さ
せた。次に保護板５を取りはずし、各チップ４表面の電
極部と回路配線２を相互に、銀系導電塗料７でスクリー
ン印刷法にて一括印刷し接続した。この面照光板を初期
および、1,2気圧240時間のプレッシャークッカーテスト
後、および−20℃85℃の温度サイクルテストを100サ
イクル後それぞれ点燈試験したが、いずれも36個のLED
チップ全てが発光した。Using a glass epoxy board with a material thickness of 1.6 mm, a printed circuit wiring board with a size of 30 × 30 mm is made of copper foil, and 36 LED chips are evenly spaced with a conductive adhesive for surface illumination. Adhered on the circuit wiring. Next, a metal protective plate 5 having 0.2 mm of silicon rubber lining on the surface is prepared so that it can be adhered to each chip surface and the circuit wiring part requiring connection, and the circuit wiring part to be connected to each chip surface
The circuit board is attached to 2a and the epoxy resin is evacuated.
It was injected into the gap between 2, 2a and the protective plate 5 and cured at 120 ° C. for 90 seconds. Next, the protective plate 5 was removed, and the electrode portion on the surface of each chip 4 and the circuit wiring 2 were connected to each other by printing with the silver-based conductive paint 7 at once by a screen printing method. This surface illuminating plate was initially and after pressure cooker test of 1,2 atmospheric pressure for 240 hours and after 100 cycles of temperature cycle test of -20 ° C and 85 ° C.
All chips emitted light.
発明の効果 以上述べたように本発明によるチップ実装方法によれ
ば、電極部数の多い場合でも安価に製造することが可能
であり、チップの電極部と回路配線の接続部を近接して
設置する必然性が無いため回路設計の自由度が増大し、
さらに高い信頼性を得ることができる。EFFECTS OF THE INVENTION As described above, according to the chip mounting method of the present invention, it is possible to manufacture at low cost even when the number of electrode parts is large, and the electrode part of the chip and the connection part of the circuit wiring are installed close to each other. Since there is no necessity, the degree of freedom in circuit design increases,
Higher reliability can be obtained.
第１図〜第３図は本発明の一実施例によるチップ実装方
法の製造工程を示す断面図である。 １……基体、2,2a……回路配線、４……チップ、５……
保護板、６……絶縁性樹脂、７……導電塗料。1 to 3 are sectional views showing manufacturing steps of a chip mounting method according to an embodiment of the present invention. 1 ... Base, 2.2a ... Circuit wiring, 4 ... Chip, 5 ...
Protective plate, 6 ... Insulating resin, 7 ... Conductive paint.
Claims (5)
導電性または絶縁性接着剤または半田付けにより単数ま
たは複数のチップを接着する工程と、保護板を前記チッ
プ表面に密着させた状態で、前記保護板と前記回路配線
のすき間部分に絶縁性樹脂を注入して固化させる工程
と、前記保護板を取りはずして、前記チップ表面の電極
部と前記回路配線の露出した部分を相互に導電性塗料に
より接続する工程とより成るチップ実装方法。1. An arbitrary portion of circuit wiring on an insulating substrate,
A step of adhering one or more chips by a conductive or insulating adhesive or soldering, and an insulating resin in the gap between the protective plate and the circuit wiring in a state where the protective plate is in close contact with the chip surface. A chip mounting method comprising a step of injecting and solidifying, and a step of removing the protective plate and connecting an electrode portion on the chip surface and an exposed portion of the circuit wiring to each other with a conductive paint.
脂である特許請求の範囲第１項に記載のチップ実装方
法。2. The chip mounting method according to claim 1, wherein the resin injected into the gap is a thermosetting resin.
線膨張率４×10-5cm/℃以下でかつ吸水率が0.15％以下
の熱可塑性樹脂である特許請求の範囲第１項に記載のチ
ップ実装方法。3. The resin to be injected into the gap is a thermoplastic resin having a linear expansion coefficient in the flow direction of 4 × 10 −5 cm / ° C. or less and a water absorption rate of 0.15% or less. Chip mounting method described.
る部分はゴム製とした特許請求の範囲第１項に記載のチ
ップ実装方法。4. The chip mounting method according to claim 1, wherein at least a portion of the protective plate that is in close contact with the chip surface is made of rubber.
されている特許請求の範囲第１項に記載のチップ実装方
法。5. The chip mounting method according to claim 1, wherein the front and back surfaces of the chip electrode portion are coated with a noble metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62323146A JPH0744202B2 (en) | 1987-12-21 | 1987-12-21 | Chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62323146A JPH0744202B2 (en) | 1987-12-21 | 1987-12-21 | Chip mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01164044A JPH01164044A (en) | 1989-06-28 |
| JPH0744202B2 true JPH0744202B2 (en) | 1995-05-15 |
Family
ID=18151594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62323146A Expired - Lifetime JPH0744202B2 (en) | 1987-12-21 | 1987-12-21 | Chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744202B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665653A (en) * | 1995-03-29 | 1997-09-09 | Unifet, Incorporated | Method for encapsulating an electrochemical sensor |
| JP2004281538A (en) | 2003-03-13 | 2004-10-07 | Seiko Epson Corp | Electronic device and its manufacturing method, circuit board and electronic apparatus |
| JP3772984B2 (en) | 2003-03-13 | 2006-05-10 | セイコーエプソン株式会社 | Electronic device and manufacturing method thereof, circuit board, and electronic apparatus |
| JP2007510301A (en) * | 2003-10-29 | 2007-04-19 | コンダクティブ・インクジェット・テクノロジー・リミテッド | Electrical connection of parts |
| JP6199094B2 (en) * | 2013-06-28 | 2017-09-20 | 富士機械製造株式会社 | Circuit device manufacturing method and mold for molding |
-
1987
- 1987-12-21 JP JP62323146A patent/JPH0744202B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01164044A (en) | 1989-06-28 |
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