JPH0795573B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention relates to a Bi-CMOS semiconductor integrated circuit in which a bipolar transistor and a complementary MOS transistor are integrated on the same substrate, and a manufacturing method thereof.

(B) Conventional Technology As the performance and functionality of semiconductor integrated circuits are increasing, composite devices that allow analog and digital functions to coexist on the same chip are drawing attention.

One technology that fulfills such demands for circuit functions is Bi-CMOS technology in which a bipolar transistor and a MOS transistor are integrated on the same semiconductor substrate. This technology
The characteristics of both low power consumption and high integration of the MOS type integrated circuit and the high speed and current driving capability of the bipolar type integrated circuit can be utilized.

FIG. 2 shows a conventional method for manufacturing a Bi-CMOS semiconductor device, which is described in Japanese Patent Application No. 63-56940.

First, as shown in FIG. 2A, after forming a thermal oxide film (2) on the surface of a P-type silicon semiconductor substrate (1), a thermal oxide film on a region where an N ⁺ type buried layer (3) is to be formed is formed. After the holes are formed by the well-known photo etching technique, N-type impurities (antimony and arsenic) are doped through the holes.

Then, as shown in FIGS. 2B and 2C, the P ⁺ -type buried layer (5) and the P ⁺ -type isolation region ( 6 ) in the thermal oxide film (4) on the surface of the substrate (1) are separated. A region corresponding to the region where the lower diffusion layer (7) is to be formed is opened, and a P-type impurity (for example, boron) is doped through this hole. Next, as shown in FIG. 2D, an N type epitaxial layer (8) is laminated on the semiconductor substrate (1) by a known vapor phase growth method.

Next, as shown in FIG. 2E, the epitaxial layer (8)
A P-type well region (10) for an N-channel type MOS transistor ( 9 ) is provided in a region corresponding to the P ⁺ type buried layer (5) on the surface.
Impurities (for example, boron) that form the are doped by a method such as ion implantation.

Then, as shown in FIG. 2F, the entire substrate (1) is heat-treated to drive in the previously doped boron.

Therefore, the lower diffusion layer (7) diffuses upward to more than half of the epitaxial layer (8), and the well region (1
0) is diffused downward so as to reach the P ⁺ type buried layer (5).

Next, as shown in FIG. 2G, first, impurities (for forming the upper diffusion layer (11)) are formed in a region corresponding to the upper diffusion layer (11) of the dispersion region ( 6 ) on the surface of the epitaxial layer (8). For example, boron) is doped. Then, a thermal oxide film and a silicon nitride film are sequentially stacked on the surface of the epitaxial layer (8), and the silicon nitride film is patterned to form a LOCOS film.
Forming an oxidation resistant mask to form an oxide film (12),
For example, the LOCOS oxide film (12) is formed in an oxidizing atmosphere at a temperature of 1000 ° C. and Wet O ₂ . Further, the thermal oxide film and the silicon nitride film are removed to expose the epitaxial layer (8), a thermal oxide film to become the gate oxide film (13) is formed again, and the base region ( 14) is formed.

Further, as shown in FIG. 2H, a non-doped polycrystalline silicon layer is laminated by the CVD method, and further, this polycrystalline silicon layer is doped with phosphorus to a predetermined concentration, and this is doped with P-channel type MOS transistor ( 15 ) and N. The gate electrode (16) of the channel type MOS transistor ( 9 ).

Further, a blocking mask is applied to the entire substrate, and boron is ion-implanted into the contact region (17) in the base region (14) and the source / drain region (18) of the P-channel type MOS transistor ( 15 ) region.

Therefore, the P type base contact region (17) is formed, and the source / drain (18) of the P channel type MOS transistor ( 15 ) is formed.

Finally, as shown in FIG. 2I, the blocking mask is re-formed in the same manner as in the previous step, and only the emitter region (19), collector contact region (20) and N-channel type MOS transistor ( 9 ) region are removed. , N-type impurity phosphorus is ion-implanted.

Therefore, the emitter region (19), the collector contact region (20) and the source / drain region (21) of the N-channel type MOS transistor ( 9 ) are formed.

Although not shown, the electrodes of the vertical transistor are formed thereafter.

(C) Problems to be Solved by the Invention The lower diffusion region ( 7 ) of the P ⁺ type isolation region ( 6 ) has a high resistance for the purpose of reducing the resistance of the isolation region and preventing parasitic NPN transistors between islands. It is necessary to adjust the concentration, and as shown in FIG. 2F, the lower diffusion region (17) is diffused upward to more than half of the epitaxial layer (8), that is, near the surface of the epitaxial layer (8), The upper diffusion region (11) must be shallow to prevent lateral diffusion and improve the degree of integration.

But in the manufacturing method described above, as in Fig. 2 B and the 2C, the lower diffusion region of the P ⁺ -type isolation region (6) (7) P ⁺
The buried layer (5) of the mold is simultaneously formed with the same impurity concentration.

Therefore, the P ⁺ type buried layer (5) reaches the source (21) and the drain (21) of the N-channel type MOS transistor ( 9 ), and the depletion layer region during operation is spread out by being spread over the high concentration region. However, there is a problem that the junction capacitance increases and the operation speed slows down.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and is a bipolar transistor, a MOS transistor of one conductivity type channel, and a MOS transistor of reverse conductivity type channel, which are separated by upper and lower isolation regions of one conductivity type. Is a semiconductor integrated circuit having the same semiconductor layer, wherein the impurity of the lower diffusion region forming the upper and lower isolation regions and a buried of one conductivity type formed in the MOS transistor region of the reverse conductivity type channel. The impurities of the layers are separately doped, the lower diffusion region is substantially upwardly diffused to the vicinity of the semiconductor layer surface, and the buried layer is formed so that the lower diffusion region is partially diffused upward. It is a solution by spreading.

(E) Operation By making the lower diffusion region (73) and the buried layer (54) of one conductivity type in separate steps, the impurity concentrations of both can be adjusted as necessary, and the lower diffusion can be performed. The region (73) is doped with a large amount of impurities, and the buried layer (54) immediately below the MOS transistor is reduced in the amount of doped impurities so that the lower diffusion region (73) is substantially formed. Semiconductor layer (5
2) Upwardly diffused to the vicinity of the surface, and the buried layer (54) is upwardly diffused below the lower diffusion region (73).

Therefore, since the buried layer (54) does not reach the source and drain (67) of the MOS transistor ( 57 ) of the reverse conductivity type channel, the region where the drain depletion layer is generated has a low concentration. Therefore, the depletion layer expands and the junction capacitance decreases.

(F) Embodiments Embodiments of the present invention will be described below with reference to the drawings.

First, for convenience of description, the configuration of the semiconductor integrated circuit achieved by the present invention will be described with reference to FIG.

This semiconductor integrated circuit includes a P type semiconductor substrate (51), an N type epitaxial layer (52) laminated on the entire surface of the semiconductor substrate (51), and a plurality of N layers provided on the surface of the semiconductor substrate (51). ⁺ -type and P ⁺ -type buried layer (53), and (54), P penetrating the epitaxial layer surrounding the N ⁺ -type buried layer that corresponds to the bipolar device formation region (53) (52) ⁺ LOCO formed on the epitaxial layer (52) for isolating the MOS isolation regions ( 56 ) and ( 57 ) from the isolation region ( 55 ) of the mold.
The S oxide film (58), an island (59) formed in an island shape by the isolation region ( 55 ), and a P ⁻ type base region () formed on the surface of the island (59) with the island (59) as a collector ( 60) and a N-type emitter region (61) formed in the base region (60), and a vertical bipolar transistor ( 62 ) and the surface of the epitaxial layer (52) surrounded by the LOCOS oxide film (58). A P-channel type MOS transistor ( 5 ) comprising a P-type source / drain region (63) formed on the gate electrode and a gate electrode (65) formed on the gate insulating film (64) on the surface of the epitaxial layer (52).
6 ), a P-type well region (66) surrounded by the LOCOS oxide film (58) and formed on the surface of the epitaxial layer (52), and an N-type source / drain region (67) formed in the well region (66). ) And a gate electrode (65) formed on the gate insulating film (64) on the surface of the epitaxial layer (52), and an N-channel type MOS transistor ( 57 ),
Although not shown, electrodes made of aluminum, for example, are formed in the respective regions to achieve a predetermined IC circuit.

Next, a method of manufacturing a semiconductor integrated circuit according to the present invention will be described in detail with reference to FIGS. 1A to 1G.

First, as shown in FIG. 1A, a thermal oxide film (70) is formed on the surface of a P-type silicon semiconductor substrate (51) having an impurity concentration of about 10 ¹⁵ atom / cm ³ , and then an N ⁺ -type buried layer (53) is formed. ), A thermal oxide film (70) on the region to be formed is opened by a well-known photoetching technique, and then N-type impurities (antimony or arsenic) are doped through this opening.

Subsequently, as shown in FIG. 1B, the thermal oxide film (70) on the semiconductor substrate (51) is entirely removed, and an extremely thin thermal oxide film (71) is formed again. After that, a photoresist film (72) to be a mask is attached on the entire surface, and then by a well-known photolithography method,
The area corresponding to the lower diffusion area (73) of the planned isolation area ( 55 ) is removed.

Then, using boron as an impurity, ion implantation is performed under the conditions of an acceleration voltage of about 100 KeV and a dose amount of about 10 ¹⁴ cm ^-3 . Then the first
As shown in FIG. C, after the photoresist film (72) is entirely removed, the photoresist film (74) serving as a mask is attached again, and the region corresponding to the planned P ⁺ type buried layer (54) is removed.

And boron as an impurity, acceleration voltage 100 KeV, dose amount
Ion implantation is performed under the condition of 10 ¹² to 10 ¹³ cm ^-3 .

Then, after removing the photoresist film (74), about 1000
A heat treatment is performed at a temperature of C for a predetermined time to diffuse the doped impurities on the semiconductor substrate (51).

The process described in FIGS. 1B and 1C is a feature of the present invention, in which the lower diffusion region (73) and the P ⁺ -type buried layer (54) are separately doped with impurities. However, the former is characterized in that it is set to a high concentration and the latter is set to a low concentration. (Details will be described later.) Here, the lower diffusion region (73) of the isolation region ( 55 ) is used for junction isolation of the bipolar element, and is formed so as to surround the N ⁺ type buried layer (53). , N corresponding to MOS transistor
^{The +} type buried layer (53) and the P ⁺ type buried layer (54) prevent parasitics.

Next, as shown in FIG. 1D, an N type epitaxial layer (52) is formed on the semiconductor substrate (51) by a known vapor phase growth method.
Are stacked.

Before stacking the epitaxial layer (52), the thermal oxide film (71) and the like on the surface of the substrate (51) are all removed. The thickness of the epitaxial layer (52) is set to about 2 μm, and re-diffusion of the previously doped impurities is normally performed during the formation of the epitaxial layer (52).

Next, as shown in FIG. 1E, the epitaxial layer (52)
A P-type well region (66) for an N-channel type MOS transistor ( 57 ) is provided in a region corresponding to the P ⁺ type buried layer (54) on the surface.
Impurities (for example, boron) that form the are selectively doped by a well-known method such as ion implantation.

Here, the ion implantation conditions are appropriately selected with an accelerating voltage of 80 to 100 KeV and a dose of 10 ¹² to 10 ¹³ cm ⁻³ .

Subsequently, as shown in FIG. 1F, the entire substrate is heat-treated to drive in the previously doped boron.

Therefore, the lower diffusion region (73) diffuses upward to the vicinity of the surface of the epitaxial layer (52), and the well region (66) diffuses downward so as to reach the P ⁺ -type buried layer (54). To be done.

Next, as shown in FIG. 1G, first, the upper diffusion region (75) of the isolation region ( 55 ) on the surface of the epitaxial layer (52).
Is doped with an impurity (for example, boron) forming the upper diffusion region (75). Then, a thermal oxide film and a silicon nitride film are sequentially laminated on the surface of the epitaxial layer (52), and the silicon nitride film is patterned to form an oxidation resistant mask, for example, at a temperature of 1000 ° C. in an oxidizing atmosphere of Wet O _2. A LOCOS oxide film (58) is formed. Further, the thermal oxide film and the silicon nitride film are removed to expose the epitaxial layer (52), a thermal oxide film to be the gate oxide film (64) is formed again, and a base region ( 60) to form.

Here, the ion implantation conditions are boron dose of 10 ¹³ to 10
It is processed at ¹⁴ cm ^-2 and an acceleration voltage of 30-40 KeV. Then, drive-in is performed, and the configuration as shown in FIG. 1G is obtained.

On the other hand, the base region (60) is not the first process but the first process.
In FIG. E, when the impurities forming the well region (66) are doped, they may be doped simultaneously. Further, in the step of FIG. 1E, the region corresponding to the upper diffusion layer (75) is doped with boron (B) which is an impurity, and the drive-in of FIG. ) Is the P ⁺ type buried layer (5
4), and further, the upper diffusion layer (75) and the lower diffusion layer (73) may be diffused to form the island region (59).

Further, as shown in FIG. 1H, a non-doped polycrystalline silicon layer having a thickness of 2500 to 5000 Å is laminated by a CVD method, and further, this polycrystalline silicon layer is doped with phosphorus to a predetermined concentration, and this is a P-channel type. The gate electrode (65) of the MOS transistor ( 56 ) and the N-channel type MOS transistor ( 57 ). Here, the sheet resistance is about 20Ω / □, and the gate electrode (65) is selectively removed by plasma etching. Further, a blocking mask is applied to the entire substrate, and the contact area (76) in the base area (60) is applied.
Then, boron is ion-implanted into the source / drain region (63) in the region of the P-channel type MOS transistor (56).

Therefore, the P-type base contact region (76) is formed, and the source / drain (63) of the P-channel type MOS transistor (56) is formed.

Finally, as shown in FIG. 1I, the blocking mask is re-formed in the same manner as in the previous step, and only the emitter region (61), collector contact region (77) and N-channel type MOS transistor ( 57 ) region are removed. , N-type impurities such as phosphorus or arsenic are ion-implanted.

Therefore, the emitter region (61), the collector contact region (77) and the source / drain region (67) of the N-channel type MOS transistor ( 57 ) are formed.

Although not shown, the electrode after this is formed and
IC circuit is achieved.

(G) Effects of the Invention As is clear from the above description, the lower diffusion region and the P ⁺ -type buried layer are separately boron-doped, and the lower diffusion region is formed as shown in FIG. 1F. The boron concentration is heavily doped to achieve near the surface of the epitaxial layer, and the P ⁺
The buried layer of the mold is lightly doped with a boron concentration so as to be smaller than the upward diffusion amount of the lower diffusion region.

Once both of the borons are doped, the heat treatment conditions thereafter are exactly the same, so the height of upward diffusion of the P ⁺ -type buried layer is lower than that of the lower diffusion region.

Therefore, since it is located below the source / drain of the N-channel MOS transistor and the concentration of the depletion layer is not high, the junction capacitance can be reduced.

On the other hand, since the lower diffusion region reaches the vicinity of the surface of the epitaxial layer sufficiently, the diffusion depth of the upper diffusion region is very shallow and lateral diffusion can be prevented. Therefore, high integration of the BiP region can be achieved.

[Brief description of drawings]

1A to 1I are sectional views showing a method for manufacturing a semiconductor integrated circuit according to the present invention, and FIGS. 2A to 2I are sectional views showing a method for manufacturing a conventional semiconductor integrated circuit.

Claims (3)

[Claims] 1. A bipolar transistor, which is separated by upper and lower isolation regions of one conductivity type, and a MOS of one conductivity type channel.
A method of manufacturing a semiconductor integrated circuit having a transistor and a MOS transistor of a reverse conductivity type channel in the same semiconductor layer, wherein impurities in a lower diffusion region forming the upper and lower isolation regions and a MOS transistor region of the reverse conductivity type channel are formed. Impurities of one conductivity type buried layer to be formed are separately doped, the lower diffusion region is substantially upwardly diffused to near the surface of the semiconductor layer, and the buried layer is above the lower diffusion region. A method of manufacturing a semiconductor integrated circuit, which comprises upwardly diffusing up to a middle of a directional diffusion height. 2. The one-conductivity-type buried layer is upwardly diffused so as to be located below a depletion layer region generated in a source region and a drain region of the MOS transistor of the reverse-conductivity type channel. And a method for manufacturing a semiconductor integrated circuit. 3. A step of doping a semiconductor substrate of one conductivity type with an impurity of a buried layer of the opposite conductivity type, and a lower diffusion of a vertical separation region of the one conductivity type so as to surround the buried layer of the opposite conductivity type. Depositing an impurity of a region; and depositing an impurity of a buried layer of one conductivity type in a MOS transistor region of a predetermined reverse conductivity type channel separately from the buried layer on the semiconductor substrate; Diffusing impurities therein, laminating an epitaxial layer of opposite conductivity type on the semiconductor substrate, and forming a well layer of one conductivity type in the epitaxial layer corresponding to the buried layer of one conductivity type A step of forming an upper diffusion region of the upper and lower isolation regions in the epitaxial layer corresponding to a lower diffusion region of the upper and lower isolation regions, and forming the MOS transistor in the well layer and the upper and lower isolation regions. Forming a bipolar transistor on the island, the lower diffusion region is substantially upwardly diffused to the vicinity of the surface of the epitaxial layer, and the buried layer of one conductivity type is above the lower diffusion region. A method of manufacturing a semiconductor integrated circuit, which comprises upwardly diffusing up to a middle of a directional diffusion height.