JPH0794671A - Bonding structure of cap for hybrid integrated circuit device - Google Patents
Bonding structure of cap for hybrid integrated circuit deviceInfo
- Publication number
- JPH0794671A JPH0794671A JP23685893A JP23685893A JPH0794671A JP H0794671 A JPH0794671 A JP H0794671A JP 23685893 A JP23685893 A JP 23685893A JP 23685893 A JP23685893 A JP 23685893A JP H0794671 A JPH0794671 A JP H0794671A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- substrate
- circuit wiring
- conductive adhesive
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はキャップに回路配線層を
設けた混成集積回路装置のキャップの接着構造に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cap bonding structure for a hybrid integrated circuit device in which a circuit wiring layer is provided on the cap.
【0002】[0002]
【従来の技術】従来、印刷配線積層基板(以下、単に基
板という)に凹設した収容部に半導体素子を搭載し、そ
の収容部開口をキャップにて閉塞して半導体素子を封止
した混成集積回路装置において、このキャップにも回路
配線層及び表面実装部品が設けられ、集積回路が形成さ
れたものがある。例えば、(特開平5−41570号)
に開示されているような構成が挙げられる。2. Description of the Related Art Conventionally, a hybrid integrated circuit in which a semiconductor element is mounted in a recess formed in a printed wiring board (hereinafter, simply referred to as a substrate), and the opening of the recess is closed by a cap to seal the semiconductor element. In some circuit devices, the cap is also provided with a circuit wiring layer and surface mount components to form an integrated circuit. For example, (JP-A-5-41570)
The configuration as disclosed in 1) can be mentioned.
【0003】この混成集積回路装置のパッケージは、上
部が開口した有底無蓋の箱形に形成されたセラミックベ
ースと、その上部開口部を閉塞するキャップとから構成
されている。箱形のセラミックベースは、その内部底面
に電子回路用配線導体を形成するとともに電子部品を実
装させている。また、箱形のセラミックベースは、その
上部開放面に電極を形成し、その電極と、内部底面に形
成した電子回路用配線導体を内壁面に沿って形成した配
線を介して電気的に接続されている。この電極には導電
樹脂または金バンプが施される。この電極より外側の上
部開放面には封止用の導体が上部開放面を一周するよう
に形成されている。The package of this hybrid integrated circuit device comprises a ceramic base formed in the shape of a box with an open top and an open top, and a cap for closing the opening of the top. In the box-shaped ceramic base, electronic circuit wiring conductors are formed on the inner bottom surface thereof and electronic components are mounted. Further, the box-shaped ceramic base has electrodes formed on its upper open surface, and the electrodes are electrically connected to the wiring conductors for electronic circuits formed on the inner bottom surface through the wiring formed along the inner wall surface. ing. A conductive resin or gold bump is applied to this electrode. A conductor for sealing is formed on the upper open surface outside the electrode so as to surround the upper open surface.
【0004】一方、セラミックベースの上部開口部を閉
塞するキャップは、薄い金属板の裏面に絶縁膜を形成し
たものであって、その絶縁膜上に電子回路用配線導体を
形成するとともに電子部品を実装させている。また、キ
ャップ裏面において、前記上部開放面の封止用の導体と
対応する外周部は絶縁膜が除去されている。On the other hand, the cap that closes the upper opening of the ceramic base is formed by forming an insulating film on the back surface of a thin metal plate. On the insulating film, a wiring conductor for an electronic circuit is formed and an electronic component is formed. I have it implemented. On the back surface of the cap, the insulating film is removed from the outer peripheral portion corresponding to the conductor for sealing the upper open surface.
【0005】そして、箱形のセラミックベースをキャッ
プにて封止する場合、セラミックベースの上部開放面に
形成した電極に導電樹脂または金バンプを施した後、キ
ャップの裏面に形成された電子回路用配線導体が対応す
る電極に当接するようにキャップをセラミックベースに
対してセットする。次に、熱、超音波、圧力又は光等で
導電樹脂または金バンプを介してセラミックベースとキ
ャップの両電子回路用配線導体を互いに電気的に接続す
る。電気的に接続した後、セラミックベースの上部開放
面に形成した封止用の導体とキャップ裏面の絶縁膜が除
去された金属部分との間で溶接が行われて気密封止が終
了する。When a box-shaped ceramic base is sealed with a cap, an electrode formed on the upper open surface of the ceramic base is provided with a conductive resin or gold bump, and then the electronic circuit is formed on the back surface of the cap. The cap is set on the ceramic base so that the wiring conductors abut the corresponding electrodes. Next, the wiring conductors for both electronic circuits of the ceramic base and the cap are electrically connected to each other by heat, ultrasonic waves, pressure, light or the like through the conductive resin or the gold bumps. After electrical connection, welding is performed between the sealing conductor formed on the upper open surface of the ceramic base and the metal portion on the back surface of the cap from which the insulating film has been removed, and the hermetic sealing is completed.
【0006】[0006]
【発明が解決しようとする課題】ところが、導電樹脂又
は金バンプによりキャップと基板の電気的接続を行った
後に、溶接等により気密封止を行っているので、セラミ
ックベースとキャップとの接着に2工程を必要としてお
り、生産効率の低下を招いている。また、溶接を行って
いることからセラミックベースとキャップとの接着は、
例えば銀ロウ付けであれば、約800℃という高温工程
となり、実装部品、特に半導体素子への影響が無視でき
なくなり、信頼性の低下を招いている。However, since the cap and the substrate are electrically connected by the conductive resin or the gold bump and then the hermetically sealed by welding or the like, it is necessary to adhere the ceramic base and the cap to each other. It requires a process, which causes a decrease in production efficiency. Also, since welding is performed, the adhesion between the ceramic base and the cap is
For example, in the case of silver brazing, a high temperature process of about 800 ° C. is required, and the influence on mounted components, especially semiconductor elements cannot be ignored, resulting in a decrease in reliability.
【0007】本発明は上記問題点を解決するためになさ
れたものであって、その目的は基板とキャップとの電気
的接続を気密封止と同時に、かつ、低温工程で行うこと
ができるようにし、生産効率を上げ、信頼性を高めるこ
とのできる混成集積回路装置のキャップの接着構造を提
供することにある。The present invention has been made to solve the above problems, and its purpose is to enable electrical connection between a substrate and a cap to be performed at the same time as hermetically sealing and at a low temperature step. Another object of the present invention is to provide an adhesive structure for a cap of a hybrid integrated circuit device, which can improve production efficiency and reliability.
【0008】[0008]
【課題を解決するための手段】本発明は上記問題点を解
決するため、印刷配線積層基板に収容部を凹設するとと
もに回路配線層を形成し、収容部に半導体素子を搭載
し、その収容部開口をキャップにて閉塞して半導体素子
を封止した混成集積回路装置において、キャップに回路
配線層を形成し、低温で接着可能なシール材にて印刷配
線積層基板とキャップとを接合するとともに、低温で接
着可能な導電性接着剤にて印刷配線積層基板の回路配線
層とキャップの回路配線層との電気的接続を行うことを
その要旨とする。In order to solve the above-mentioned problems, the present invention forms a circuit wiring layer by forming a recess in an accommodating portion in a printed wiring laminated board, and mounting a semiconductor element in the accommodating portion, and accommodating the same. In a hybrid integrated circuit device in which a semiconductor device is sealed by closing a part opening with a cap, a circuit wiring layer is formed on the cap, and the printed wiring laminated substrate and the cap are joined with a sealing material that can be adhered at a low temperature. The gist of the invention is to electrically connect the circuit wiring layer of the printed wiring laminated board and the circuit wiring layer of the cap with a conductive adhesive that can be bonded at a low temperature.
【0009】[0009]
【作用】従って、本発明によれば、印刷配線積層基板と
キャップとの接合部に設けられるシール材及び導電性接
着剤は、ともに低温工程での接着が可能であるので、混
成集積回路装置の気密封止及び印刷配線積層基板の回路
配線層とキャップの回路配線層との電気的接続が同時に
行うことができる。Therefore, according to the present invention, both the sealing material and the conductive adhesive provided at the joint between the printed wiring laminated substrate and the cap can be adhered in a low temperature process. It is possible to hermetically seal and electrically connect the circuit wiring layer of the printed wiring laminated board and the circuit wiring layer of the cap at the same time.
【0010】[0010]
【実施例】以下、本発明の混成集積回路装置を具体化し
た一実施例を図1に従って説明する。印刷配線積層基板
(以下、単に基板という)10はセラミック基板を積層
して形成され、各層には内部配線11と各層を電気的に
接続するビアホール12が設けられている。基板10中
央には階段状の収容部13が形成され、その収容部13
の下側の階段面をパッド面13a、上側の階段面をキャ
ップシール面13bとしている。パッド面13aには内
部配線11と接続している配線14が設けられている。
また、基板10表面には回路配線層15が形成されてい
る。前記収容部13には半導体素子16が導電性又は絶
縁性の接着剤17を介して固着されている。該半導体素
子16はワイヤ18にて収容部13の配線14と電気的
に接続されている。基板10裏面にはロウ材19を介し
て端子20が取着され、内部配線11及びビアホール1
2を介して基板10表面に形成された回路配線層15や
半導体素子16と電気的に接続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the hybrid integrated circuit device of the present invention will be described below with reference to FIG. A printed wiring laminated substrate (hereinafter, simply referred to as a substrate) 10 is formed by laminating ceramic substrates, and each layer is provided with an internal wiring 11 and a via hole 12 that electrically connects each layer. A staircase-shaped accommodating portion 13 is formed in the center of the substrate 10.
The lower staircase surface is the pad surface 13a, and the upper staircase surface is the cap seal surface 13b. Wiring 14 connected to the internal wiring 11 is provided on the pad surface 13a.
A circuit wiring layer 15 is formed on the surface of the substrate 10. A semiconductor element 16 is fixed to the housing portion 13 with a conductive or insulating adhesive 17. The semiconductor element 16 is electrically connected to the wiring 14 of the housing portion 13 by a wire 18. The terminals 20 are attached to the back surface of the substrate 10 via the brazing material 19, and the internal wiring 11 and the via holes 1 are formed.
It is electrically connected to the circuit wiring layer 15 and the semiconductor element 16 formed on the surface of the substrate 10 through the wiring 2.
【0011】キャップ30はセラミックで形成され、つ
ば部30aが上部周縁部に前記回路配線層15と対向す
るように延出形成され、腹部30bが下端部に膨出形成
されている。キャップ30の腹部30b下面は前記キャ
ップシール面13bに施してなるシール材31を介して
基板10に接着されている。シール材31はエポキシ系
樹脂に硬化剤、充填材を添加したもので、低温(約15
0℃〜200℃)にて硬化して、キャップ30と基板1
0とを接合する。キャップ30の表面及びつば部30a
裏面には回路配線層32,33が形成され、この回路配
線層32,33は、キャップ30内部に設けられたビア
ホール34により電気的に接続されている。キャップ3
0表面の回路配線層32上には表面実装部品35が半田
36を介して実装されている。キャップ30のつば部3
0a裏面の回路配線層33と前記基板10表面に形成さ
れた回路配線層15との間には、Agエポキシ、Agシ
リコン等の熱硬化型の導電性接着剤37が設けられ、電
気的に接続されている。この導電性接着剤37は低温
(約150℃〜200℃)工程での接着が可能である。The cap 30 is made of ceramic, a flange portion 30a is formed so as to extend in the upper peripheral edge portion so as to face the circuit wiring layer 15, and an abdominal portion 30b is formed so as to bulge at the lower end portion. The lower surface of the abdomen 30b of the cap 30 is adhered to the substrate 10 via a sealing material 31 formed on the cap sealing surface 13b. The sealing material 31 is an epoxy resin to which a curing agent and a filler are added, and the sealing material 31 has a low temperature (about 15
It is cured at 0 ° C. to 200 ° C., and the cap 30 and the substrate 1
Join 0. The surface of the cap 30 and the collar portion 30a
Circuit wiring layers 32 and 33 are formed on the back surface, and the circuit wiring layers 32 and 33 are electrically connected by via holes 34 provided inside the cap 30. Cap 3
A surface mount component 35 is mounted on the surface 0 of the circuit wiring layer 32 via solder 36. Collar 3 of cap 30
A thermosetting conductive adhesive agent 37 such as Ag epoxy or Ag silicon is provided between the circuit wiring layer 33 on the back surface of the substrate 0a and the circuit wiring layer 15 formed on the surface of the substrate 10 to electrically connect them. Has been done. The conductive adhesive 37 can be bonded in a low temperature (about 150 ° C. to 200 ° C.) process.
【0012】このように本実施例によれば、基板10表
面の回路配線層15とキャップ30のつば部30a裏面
の回路配線層33との電気的接続、キャップ30の腹部
30b下面とキャップシール面13bとの接着に、とも
に低温工程での接着が可能なシール材31、導電性接着
剤37を用いているので、この2工程は同時に行うこと
ができる。従って、生産工程における工数を低減し、生
産効率が上がる。しかも、シール材31に加えて導電性
接着剤37によってもキャップ30の接着が行われ、接
着面積が広くなり、従って接着強度が強くなるので、半
導体素子16の封止がより確実にできる。また、低温工
程での接着可能な導電性接着剤37を用いることによ
り、半導体素子16への影響が少なくなり、信頼性が高
まる。As described above, according to this embodiment, the circuit wiring layer 15 on the surface of the substrate 10 and the circuit wiring layer 33 on the rear surface of the collar portion 30a of the cap 30 are electrically connected, and the lower surface of the abdominal portion 30b of the cap 30 and the cap sealing surface. Since the sealing material 31 and the conductive adhesive 37, both of which can be bonded in the low temperature process, are used for bonding with 13b, these two processes can be performed at the same time. Therefore, the number of steps in the production process is reduced and the production efficiency is increased. Moreover, since the cap 30 is adhered by the conductive adhesive 37 in addition to the sealant 31 and the adhesion area is widened and therefore the adhesive strength is increased, the semiconductor element 16 can be sealed more reliably. Further, by using the conductive adhesive 37 that can be adhered in the low temperature process, the influence on the semiconductor element 16 is reduced and the reliability is improved.
【0013】また、キャップ30表面及びつば部30a
裏面に回路配線層32,33を設け、さらに回路配線層
32上には表面実装部品35を設けているので、実装効
率を上げることができる。キャップ30表面及びつば部
30a裏面に回路配線層32,33を設けるために本実
施例では、キャップ30内部にビアホール34を設けて
いる。このような構成とすることによって、キャップ3
0本来の、半導体素子16を封止するという機能を損な
うことはなく、従って、信頼性低下等の問題を生じるこ
ともなく、実装効率が上がる。また、キャップ30表面
に実装された表面実装部品35については、混成集積回
路装置作製後も修理、交換が可能であるので、信頼性試
験の結果、不具合が生じたときにはリペアをして、製品
として出荷することができ、歩留りも向上する。Further, the surface of the cap 30 and the collar portion 30a.
Since the circuit wiring layers 32 and 33 are provided on the back surface and the surface mounting component 35 is further provided on the circuit wiring layer 32, the mounting efficiency can be improved. In order to provide the circuit wiring layers 32 and 33 on the front surface of the cap 30 and the rear surface of the collar portion 30a, the via hole 34 is provided inside the cap 30 in this embodiment. With such a configuration, the cap 3
The original function of encapsulating the semiconductor element 16 is not impaired, and therefore the mounting efficiency is improved without causing a problem such as deterioration of reliability. Further, the surface-mounted component 35 mounted on the surface of the cap 30 can be repaired and replaced even after the hybrid integrated circuit device is manufactured. Therefore, as a result of the reliability test, when a defect occurs, the surface-mounted component 35 is repaired and the product is manufactured. It can be shipped and the yield is improved.
【0014】さらに、半導体素子16の基板10への実
装工程と表面実装部品35のキャップ30への実装工程
とは並行して行うことができるので、生産効率を上げる
ことができる。Furthermore, since the step of mounting the semiconductor element 16 on the substrate 10 and the step of mounting the surface mount component 35 on the cap 30 can be performed in parallel, the production efficiency can be improved.
【0015】なお、本発明は上記実施例に限定されるも
のでなく、本発明の趣旨を逸脱しない範囲において、例
えば次のように変更してもよい。 (1)上記実施例では、キャップ30の腹部30b下面
と基板10のキャップシール面13bとの間にシール材
31、つば部30a裏面と基板10表面との間に導電性
接着剤37をそれぞれ設けていたが、このシール材31
及び導電性接着剤37を設ける場所は図2に示すように
入れ換えてもよい。The present invention is not limited to the above embodiment, but may be modified as follows, for example, without departing from the gist of the present invention. (1) In the above embodiment, the sealing material 31 is provided between the lower surface of the belly portion 30b of the cap 30 and the cap sealing surface 13b of the substrate 10, and the conductive adhesive 37 is provided between the rear surface of the collar portion 30a and the front surface of the substrate 10. However, this sealing material 31
The places where the conductive adhesive 37 is provided may be replaced as shown in FIG.
【0016】すなわち、基板10の収容部13の上側の
階段面に回路配線層15を設け、基板10表面をキャッ
プシール面13bとする。キャップ30の腹部30b下
面には回路配線層33を回路配線層15に相対するよう
に設ける。そして、キャップ30は基板10のキャップ
シール面13bにおいてシール材31を介して接着さ
れ、回路配線層15,33が導電性接着剤37を介して
接着される。この実施例においては、導電性接着剤37
をシール材31の内側に設けているので、導電性接着剤
37が酸化等の汚染から保護されることになり、基板1
0とキャップ30の電気的接続の信頼性が高まる。That is, the circuit wiring layer 15 is provided on the upper step surface of the accommodating portion 13 of the substrate 10, and the surface of the substrate 10 serves as the cap sealing surface 13b. A circuit wiring layer 33 is provided on the lower surface of the abdomen 30b of the cap 30 so as to face the circuit wiring layer 15. Then, the cap 30 is bonded on the cap sealing surface 13b of the substrate 10 via the seal material 31, and the circuit wiring layers 15 and 33 are bonded via the conductive adhesive 37. In this embodiment, the conductive adhesive 37
Since the sealant 31 is provided inside the sealant 31, the conductive adhesive 37 is protected from contamination such as oxidation.
The reliability of the electrical connection between 0 and the cap 30 is improved.
【0017】(2)上記実施例では、キャップ30表面
及びつば部30a裏面の回路配線層32,33の電気的
接続はビアホール34を介して行っているが、次のよう
にしてもよい。(2) In the above embodiment, the circuit wiring layers 32 and 33 on the front surface of the cap 30 and the rear surface of the collar portion 30a are electrically connected through the via holes 34, but the following may be adopted.
【0018】図3に示すように、キャップ30表面及び
つば部30a裏面の回路配線層32,33を端部に向か
って延長させて、キャップ30側面に設けた配線38と
接続し、これによって電気的接続を行うようにしてもよ
い。この実施例においては、回路配線層32,33と配
線38が同一工程で形成することができるので、生産効
率を上げることができる。As shown in FIG. 3, the circuit wiring layers 32 and 33 on the front surface of the cap 30 and the rear surface of the collar portion 30a are extended toward the end portion and connected to the wiring 38 provided on the side surface of the cap 30. You may make it connect physically. In this embodiment, since the circuit wiring layers 32 and 33 and the wiring 38 can be formed in the same process, the production efficiency can be improved.
【0019】(3)上記実施例では、キャップ30はつ
ば部30aが基板10表面の回路配線層15と対向する
ように延出形成されており、シール材31及び導電性接
着剤37がそれぞれ基板10のキャップシール面13
b、基板10表面に設けられていたが、次のようにして
もよい。(3) In the above embodiment, the cap 30 is formed so that the flange portion 30a faces the circuit wiring layer 15 on the surface of the substrate 10, and the sealing material 31 and the conductive adhesive 37 are respectively provided on the substrate. 10 cap seal surface 13
b, it is provided on the surface of the substrate 10, but it may be performed as follows.
【0020】図4に示すように、キャップ30を基板1
0への落とし込み構造とし、基板10のキャップシール
面13bにシール材31及び導電性接着剤37を設ける
ようにしてもよい。この実施例ではキャップ30の形状
が簡単であるので、加工が容易となる。また、キャップ
30の厚みを薄くすることができるので、混成集積回路
装置全体の厚みも薄くし、小型化することができる。さ
らに、キャップ30を基板10への落とし込み構造とす
ることにより、キャップ30の位置決めが治具を用いな
くとも正確にできるようになり、生産効率を上げること
ができる。As shown in FIG. 4, the cap 30 is attached to the substrate 1.
The structure may be dropped to 0, and the sealing material 31 and the conductive adhesive 37 may be provided on the cap sealing surface 13b of the substrate 10. In this embodiment, the cap 30 has a simple shape, which facilitates processing. Further, since the thickness of the cap 30 can be reduced, the overall thickness of the hybrid integrated circuit device can be reduced and the size can be reduced. Further, by adopting a structure in which the cap 30 is dropped onto the substrate 10, the positioning of the cap 30 can be accurately performed without using a jig, and the production efficiency can be improved.
【0021】(4)上記実施例では表面実装部品35は
キャップ30表面にのみ設けているが、図5に示すよう
にキャップ30裏面にも表面実装部品35を設けてもよ
い。このとき、キャップ30表面及び裏面の回路配線層
32,33の電気的接続はキャップ30内部の端部側の
ビアホール34のみではなく、キャップ30表面及び裏
面の回路配線層32,33を直接接続するようなビアホ
ール34を設けてもよい。このような構成にすること
で、さらに実装効率を上げることができる。(4) Although the surface mount component 35 is provided only on the front surface of the cap 30 in the above embodiment, the surface mount component 35 may be provided on the rear surface of the cap 30 as shown in FIG. At this time, the circuit wiring layers 32 and 33 on the front and back surfaces of the cap 30 are electrically connected not only to the via holes 34 on the end side inside the cap 30, but also directly to the circuit wiring layers 32 and 33 on the front and back surfaces of the cap 30. Such via holes 34 may be provided. With such a configuration, the mounting efficiency can be further improved.
【0022】(5)上記実施例では、キャップ30はビ
アホール34を設けるのみであるが、さらに複雑な回路
を構成したい場合には図6に示すようにしてもよい。す
なわち、キャップ30内部にも基板10と同様に、内部
配線39を形成してもよい。このような構成にすること
で、キャップ30内部にも複雑な回路が構成されるの
で、高集積化をすることができる。(5) In the above embodiment, the cap 30 is only provided with the via hole 34, but if a more complicated circuit is desired to be formed, it may be arranged as shown in FIG. That is, the internal wiring 39 may be formed inside the cap 30 as in the case of the substrate 10. With such a configuration, since a complicated circuit is formed inside the cap 30, high integration can be achieved.
【0023】(6)上記実施例では、基板10表面及び
キャップ30裏面にそれぞれ回路配線層15,33を設
けていたが、回路配線層15,33の代わりに、電極パ
ターンのみで基板10とキャップ30の電気的接続を行
ってもよい。(6) In the above embodiment, the circuit wiring layers 15 and 33 are provided on the front surface of the substrate 10 and the back surface of the cap 30, respectively. However, instead of the circuit wiring layers 15 and 33, only the electrode pattern is used for the substrate 10 and the cap. Thirty electrical connections may be made.
【0024】(7)上記実施例及び上記(3)の別例に
おいて、キャップ30の少なくとも下部は基板10への
落とし込み構造となっていたが、図7に示すように、キ
ャップ30は基板10表面に設けられている構成であっ
てもよい。(7) In the above-described embodiment and the other example of (3), at least the lower portion of the cap 30 has a structure of being dropped into the substrate 10. However, as shown in FIG. May be provided in the.
【0025】(8)上記実施例では、導電性接着剤37
として熱硬化型のものを示したが、混成集積回路装置の
使用される環境に応じて適宜、常温硬化型、紫外線硬化
型等に変更してもよい。(8) In the above embodiment, the conductive adhesive 37
Although a thermosetting type is shown as the above, it may be appropriately changed to a room temperature curing type, an ultraviolet curing type or the like depending on the environment in which the hybrid integrated circuit device is used.
【0026】(9)上記実施例におけるシール材31と
してのエポキシ系樹脂の代わりに低融点ガラスを適用し
てもよい。低融点ガラスであっても低温(150℃〜3
50℃)工程での接着が可能である。(9) Instead of the epoxy resin as the sealing material 31 in the above embodiment, a low melting point glass may be applied. Low temperature (150 ° C-3
Adhesion is possible in the step of 50 ° C.
【0027】(10)上記実施例では、基板10はセラ
ミック基板を積層したものであったが、セラミック基板
の代わりにガラスエポキシ基板、ポリイミド基板を用い
てもよい。(10) In the above embodiment, the substrate 10 is formed by laminating the ceramic substrates, but a glass epoxy substrate or a polyimide substrate may be used instead of the ceramic substrate.
【0028】[0028]
【発明の効果】以上詳述したように本発明によれば、キ
ャップと基板との接合部にともに低温で接着可能なシー
ル材及び導電性接着剤を設けたことにより、半導体素子
の封止と、基板の回路配線層とキャップの回路配線層と
の電気的接続が同時に、かつ低温工程で行うことができ
るので、混成集積回路装置の生産効率を上げ、信頼性を
高めることができるという優れた効果がある。As described above in detail, according to the present invention, by providing the sealing material and the conductive adhesive which can be adhered at a low temperature together at the joint between the cap and the substrate, the semiconductor element can be sealed. Since the circuit wiring layer of the substrate and the circuit wiring layer of the cap can be electrically connected at the same time and in the low temperature process, the production efficiency and the reliability of the hybrid integrated circuit device can be improved. effective.
【図1】本発明の混成集積回路装置の一実施例を示す断
面図である。FIG. 1 is a sectional view showing an embodiment of a hybrid integrated circuit device of the present invention.
【図2】シール材と導電性接着剤の設けられる位置を入
れ換えた混成集積回路装置の断面図である。FIG. 2 is a cross-sectional view of the hybrid integrated circuit device in which the positions where the seal material and the conductive adhesive are provided are exchanged.
【図3】キャップ表面及び裏面の回路配線層をキャップ
側面の配線で電気的に接続した混成集積回路装置の断面
図である。FIG. 3 is a cross-sectional view of a hybrid integrated circuit device in which circuit wiring layers on a front surface and a back surface of a cap are electrically connected by wiring on a side surface of the cap.
【図4】キャップを基板への落とし込み構造とした混成
集積回路装置の要部断面図である。FIG. 4 is a cross-sectional view of essential parts of a hybrid integrated circuit device having a structure in which a cap is dropped onto a substrate.
【図5】キャップ裏面の回路配線層上にも表面実装部品
を設けた混成集積回路装置の要部断面図である。FIG. 5 is a cross-sectional view of a main part of a hybrid integrated circuit device in which a surface mounting component is also provided on a circuit wiring layer on the back surface of a cap.
【図6】キャップ内部にビアホールに加えて内部配線を
設けた混成集積回路装置の要部断面図である。FIG. 6 is a cross-sectional view of essential parts of a hybrid integrated circuit device in which internal wiring is provided in addition to via holes inside a cap.
【図7】キャップが基板表面に設けられている混成集積
回路装置の要部断面図である。FIG. 7 is a cross-sectional view of essential parts of a hybrid integrated circuit device in which a cap is provided on the surface of a substrate.
10…印刷配線積層基板、11…基板内部の内部配線、
12…基板内部のビアホール、13…収容部、13a…
パッド面、13b…キャップシール面、14…配線、1
5…基板表面に設けられた回路配線層、16…半導体素
子、17…接着剤、18…ワイヤ、19…ロウ材、20
…端子、30…キャップ、30a…キャップつば部、3
0b…キャップ腹部、31…シール材、32…キャップ
表面の回路配線層、33…キャップ裏面の回路配線層、
34…キャップ内部のビアホール、35…キャップ上に
実装された表面実装部品、36…半田、37…導電性接
着剤、38…側面配線、39…キャップ内の内部配線10 ... Printed wiring laminated board, 11 ... Internal wiring inside the board,
12 ... Via hole inside the substrate, 13 ... Housing portion, 13a ...
Pad surface, 13b ... Cap sealing surface, 14 ... Wiring, 1
5 ... Circuit wiring layer provided on substrate surface, 16 ... Semiconductor element, 17 ... Adhesive agent, 18 ... Wire, 19 ... Brazing material, 20
... terminals, 30 ... caps, 30a ... cap collars, 3
0b ... Cap abdomen, 31 ... Sealing material, 32 ... Circuit wiring layer on cap surface, 33 ... Circuit wiring layer on back surface of cap,
34 ... Via hole inside cap, 35 ... Surface mount component mounted on cap, 36 ... Solder, 37 ... Conductive adhesive, 38 ... Side wiring, 39 ... Internal wiring in cap
Claims (1)
ともに、回路配線層を形成し、前記収容部に半導体素子
を搭載し、その収容部開口をキャップにて閉塞して半導
体素子を封止した混成集積回路装置において、 前記キャップに回路配線層を形成し、低温で接着可能な
シール材にて印刷配線積層基板とキャップとを接合する
とともに、低温で接着可能な導電性接着剤にて印刷配線
積層基板の回路配線層とキャップの回路配線層との電気
的接続を行う混成集積回路装置のキャップの接着構造。1. A printed wiring laminated board is provided with a recess, a circuit wiring layer is formed, a semiconductor element is mounted on the recess, and the opening of the recess is closed by a cap to seal the semiconductor element. In the hybrid integrated circuit device that has been stopped, a circuit wiring layer is formed on the cap, and the printed wiring laminated substrate and the cap are joined by a sealing material that can be bonded at low temperature, and a conductive adhesive that can be bonded at low temperature A bonding structure of a cap of a hybrid integrated circuit device for electrically connecting a circuit wiring layer of a printed wiring laminated board and a circuit wiring layer of a cap.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23685893A JPH0794671A (en) | 1993-09-22 | 1993-09-22 | Bonding structure of cap for hybrid integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23685893A JPH0794671A (en) | 1993-09-22 | 1993-09-22 | Bonding structure of cap for hybrid integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0794671A true JPH0794671A (en) | 1995-04-07 |
Family
ID=17006849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23685893A Pending JPH0794671A (en) | 1993-09-22 | 1993-09-22 | Bonding structure of cap for hybrid integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0794671A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0713252A3 (en) * | 1994-11-16 | 1998-01-07 | Nec Corporation | Circuit elements mounting |
-
1993
- 1993-09-22 JP JP23685893A patent/JPH0794671A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0713252A3 (en) * | 1994-11-16 | 1998-01-07 | Nec Corporation | Circuit elements mounting |
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