JPH08213764A - Electronic part and manufacture thereof - Google Patents

Electronic part and manufacture thereof

Info

Publication number
JPH08213764A
JPH08213764A JP1685395A JP1685395A JPH08213764A JP H08213764 A JPH08213764 A JP H08213764A JP 1685395 A JP1685395 A JP 1685395A JP 1685395 A JP1685395 A JP 1685395A JP H08213764 A JPH08213764 A JP H08213764A
Authority
JP
Japan
Prior art keywords
electrode
hole
lid
insulating substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1685395A
Other languages
Japanese (ja)
Other versions
JP3546506B2 (en
Inventor
Keizaburo Kuramasu
敬三郎 倉増
Daizo Ando
大蔵 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1685395A priority Critical patent/JP3546506B2/en
Publication of JPH08213764A publication Critical patent/JPH08213764A/en
Application granted granted Critical
Publication of JP3546506B2 publication Critical patent/JP3546506B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Casings For Electric Apparatus (AREA)

Abstract

PURPOSE: To provide a small electronic part including a semiconductor element, a surface acoustic wave device or a crystal oscillator without a fluctuation in electrical characteristics caused by a change in inductance of an element used at high frequency. CONSTITUTION: In a bump forming board 5, a projected electrode 4 is provided with an electrode film 3 in between on an inside face of a through hole 2 in an insulating board 1. The projected electrode 4 of the bump forming board 5 and a drawing out electrode 7 of an element 8 are connected in a joint alloy state. In addition, a middle case 9 and a cover 10 are mounted on the bump forming board 5 to seal the whole body.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種電子機器に用いる
半導体素子、表面弾性波素子もしくは水晶振動子等を組
み込んだ電子部品およびその製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component incorporating a semiconductor element, a surface acoustic wave element, a crystal oscillator or the like used in various electronic devices and a method for manufacturing the same.

【0002】[0002]

【従来の技術】以下に従来の電子部品について説明す
る。
2. Description of the Related Art A conventional electronic component will be described below.

【0003】半導体素子や表面弾性波素子等を組み込む
パッケージは、それらの素子に対する電磁気的な影響を
防ぐとともに外気から気密を保ちつつ、それらの素子と
連結しているリード線をパッケージの外部に取り出す構
成としていた。図7および図8に示すように、アルミナ
等製の第1絶縁板51の端面部に設けられた接続端子5
2と、第1絶縁板51とアルミナ等製の第2絶縁板53
の間に設けられた第1導電パターン54と、第2絶縁板
53の垂直部に形設したくぼみ部に設けられた導電層5
5と、第2絶縁板53の上面に設けられた第2導電パタ
ーン56とからなるケースは、グリーンシート状のアル
ミナ板に導電体を印刷形成した後に、2枚のグリーンシ
ート状のアルミナ板を張り合わせてから焼成して作成さ
れる。このケースの上に半導体素子や表面弾性波素子等
の素子57を接着固定し、AuまたはAl製のリード線
58で素子57の電極部と第2導電パターン56とを接
続した後に、金属ふた59を第2絶縁板53の上に設け
た金属層60と半田付け、またはシーム溶接して封止し
た構成である。
In a package incorporating a semiconductor element, a surface acoustic wave element, etc., the lead wires connected to these elements are taken out of the package while preventing electromagnetic influences on these elements and keeping airtight from the outside air. It was composed. As shown in FIGS. 7 and 8, the connection terminal 5 provided on the end surface portion of the first insulating plate 51 made of alumina or the like.
2, the first insulating plate 51 and the second insulating plate 53 made of alumina or the like
Between the first conductive pattern 54 provided between the second insulating plate 53 and the first conductive pattern 54 and the conductive layer 5 provided in the recess formed in the vertical portion of the second insulating plate 53.
5 and the second conductive pattern 56 provided on the upper surface of the second insulating plate 53, the conductor is printed on the green sheet-shaped alumina plate, and then the two green sheet-shaped alumina plates are formed. It is made by laminating and firing. An element 57 such as a semiconductor element or a surface acoustic wave element is adhered and fixed on this case, and the electrode portion of the element 57 and the second conductive pattern 56 are connected by a lead wire 58 made of Au or Al, and then a metal lid 59. Is soldered or seam welded to the metal layer 60 provided on the second insulating plate 53 and sealed.

【0004】このような構成では、素子57と外部リー
ドとの導電的な接続をリード線58でワイヤボンド技術
を用いて行っているので、素子57の大きさに比べて電
子部品の大きさが大きくなり、小型化が困難であった。
In such a structure, since the element 57 and the external lead are electrically connected by the lead wire 58 using the wire bonding technique, the size of the electronic component is smaller than the size of the element 57. It became large and it was difficult to miniaturize it.

【0005】また、素子57のワイヤボンド接続面とケ
ースのワイヤボンド接続面との間の段差が大きくなる
と、良好なワイヤボンド接続が困難になるので、第2絶
縁板53の一部を切り欠き、この部分に素子57を配置
するようにして段差を無くしているが、このようなケー
スを作成することは複雑な工程を必要とし、ケースがコ
スト高となっていた。
Further, if the step difference between the wire bond connecting surface of the element 57 and the wire bond connecting surface of the case becomes large, it becomes difficult to make a good wire bond connection. Therefore, a part of the second insulating plate 53 is cut out. Although the step is eliminated by arranging the element 57 in this portion, the production of such a case requires a complicated process, and the case has a high cost.

【0006】さらに、素子57が表面弾性波素子のとき
は、使用周波数が1GHz近辺の高周波帯域になると、
リード線58の張り方やアース電極リード線と信号電極
リード線の配置の仕方などによって、素子57の周波数
特性が影響されるようになる。これは、高周波帯域で
は、それらのリード線がインダクタとして作用し、それ
らのリード線の張り方によりインダクタンスが変動する
ために生じるものである。
Further, when the element 57 is a surface acoustic wave element, when the operating frequency is in the high frequency band around 1 GHz,
The frequency characteristic of the element 57 is influenced by the way of arranging the lead wire 58 and the way of arranging the ground electrode lead wire and the signal electrode lead wire. This is because those lead wires act as inductors in the high frequency band, and the inductance varies depending on how the lead wires are stretched.

【0007】[0007]

【発明が解決しようとする課題】上述のように従来の構
成では、小型化が困難であるという問題点、また高周波
帯域で使用する素子を組み込んだときは、インダクタン
ス変動による電気的特性の周波数変動が生じるという問
題点、さらに製造工程が複雑でコスト高になるという問
題点を有していた。
As described above, the conventional configuration has a problem that it is difficult to miniaturize, and when an element used in a high frequency band is incorporated, frequency variation of electrical characteristics due to inductance variation is caused. However, the manufacturing process is complicated and the cost is high.

【0008】本発明は上記従来の問題点を解決するもの
で、小型化でき、高周波帯域で使用する素子を組み込ん
だときにインダクタンス変動による電気的特性の周波数
変動が生じず、製造工程が簡単でコスト高にならない電
子部品およびその製造方法を提供することを目的とす
る。
The present invention solves the above-mentioned problems of the prior art, can be miniaturized, and when an element used in a high frequency band is incorporated, no frequency fluctuation of electrical characteristics due to inductance fluctuation occurs, and the manufacturing process is simple. It is an object of the present invention to provide an electronic component that does not increase in cost and a manufacturing method thereof.

【0009】[0009]

【課題を解決するための手段】この目的を達成するため
に本発明の電子部品は、絶縁性基板の貫通孔に形成した
電極膜を介して設けた突起電極を有するバンプ形成基板
と、電極膜に接合し外部回路と接続する表面電極と、突
起電極と接続する取り出し電極を有する素子と、バンプ
形成基板と接合する金属もしくはセラミックもしくはガ
ラス製の中ケースとふたを備え、突起電極と取り出し電
極を接合し、中ケースとふたをバンプ形成基板に取り付
け封止接合した構成としたものである。
To achieve this object, an electronic component according to the present invention comprises a bump forming substrate having a bump electrode provided via an electrode film formed in a through hole of an insulating substrate, and an electrode film. An element having a surface electrode that is connected to the external circuit and connected to an external circuit, a lead electrode that is connected to the bump electrode, a metal, ceramic, or glass middle case that is joined to the bump forming substrate and a lid are provided. The structure is such that the inner case and the lid are attached to the bump forming substrate and then sealed and joined.

【0010】また、その製造方法は、絶縁性基板の素子
の取り出し電極と一致する位置に貫通孔を設け、この貫
通孔を含む絶縁性基板の片面に電極膜を形成し、つい
で、絶縁性基板の貫通孔以外の電極膜を形成した面を絶
縁体で覆い、貫通孔のみにメッキを行い貫通孔を埋める
とともに、絶縁性基板よりも突出した形状の突起電極を
設けたバンプ形成基板を作成し、このバンプ形成基板上
に取り出し電極を突起電極と一致させて位置合わせした
後、加圧と加熱して合金接続を行い、ついで、中ケース
とふたで封止する方法である。
Further, in the manufacturing method, a through hole is provided at a position corresponding to the extraction electrode of the element of the insulating substrate, an electrode film is formed on one surface of the insulating substrate including the through hole, and then the insulating substrate is formed. The surface with the electrode film other than the through holes is covered with an insulator, and only the through holes are plated to fill the through holes, and a bump forming substrate is provided that has a protruding electrode protruding more than the insulating substrate. After aligning the extraction electrode with the bump electrode on the bump forming substrate so as to be aligned with each other, the alloy connection is performed by applying pressure and heat, and then the middle case and the lid are sealed.

【0011】[0011]

【作用】この構成および方法において、素子と外部への
リードとの接続をAuやAl製のリード線を用いずに行
っているので、大きさを小さくでき、リード線によるイ
ンダクタンスの発生がなくて周波数の変動が生じず、基
板の構造も単純となる。
In this structure and method, since the element and the lead to the outside are connected without using the lead wire made of Au or Al, the size can be reduced and the inductance is not generated by the lead wire. The frequency does not fluctuate and the structure of the substrate becomes simple.

【0012】[0012]

【実施例】【Example】

(実施例1)以下本発明の一実施例について、図面を参
照しながら説明する。
(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

【0013】図1に示すように、絶縁性基板1に形設し
た貫通孔2の電極膜3を介して設けた突起電極4を有す
るバンプ形成基板5と、電極膜3に接合し外部回路に接
続する表面電極6と、突起電極4と合金接合する取り出
し電極7を有する素子8と、バンプ形成基板5と接合す
る中ケース9とふた10を備えた構成である。本実施例
では素子8に表面弾性波を励振・受信するインターディ
ジタルトランスデューサ電極8aを有する表面弾性波素
子を用いた。
As shown in FIG. 1, a bump forming substrate 5 having a protruding electrode 4 provided through an electrode film 3 of a through hole 2 formed in an insulating substrate 1 and an electrode film 3 are joined to an external circuit. This is a configuration including a surface electrode 6 to be connected, an element 8 having a lead-out electrode 7 to be alloy-bonded to the bump electrode 4, an inner case 9 to be bonded to the bump forming substrate 5, and a lid 10. In this embodiment, the element 8 is a surface acoustic wave element having an interdigital transducer electrode 8a for exciting and receiving surface acoustic waves.

【0014】以下、上記構成の電子部品の製造方法につ
いて説明する。まず、バンプ形成基板5の製造方法につ
いて図2を用いて説明する。
A method of manufacturing the electronic component having the above structure will be described below. First, a method of manufacturing the bump forming substrate 5 will be described with reference to FIG.

【0015】図2(a)に示すように、ソーダガラス製
の絶縁性基板1の所定の位置に貫通孔2をサンドブラス
トにより形設し、ついで、図2(b)に示すように、絶
縁性基板1の片側面の全面およびその反対面の電極膜3
を形成しない領域にマスク治具(1)11およびマスク
治具(2)12をセットした後に、電極膜3を貫通孔2
を含む領域に形成する。電極膜3の形成は、真空蒸着や
スパッタリングで可能であり、本実施例ではスパッタリ
ングを用い、下層にCr膜(膜厚:30nm)、上層に
Cu膜(膜厚:2μm)を形成する。ついで、図2
(c)に示すように、絶縁性基板1の片側面に形成した
電極膜3を覆うようにメッキ防止用カバー13を張り付
け、Auメッキ液につけてAuメッキ膜を形成する。絶
縁性基板1の電極膜3は、貫通孔2の部分のみしかメッ
キ液に露出していないことから、貫通孔2のみにメッキ
され、メッキ時間の経過とともに貫通孔2はAuメッキ
膜で満たされ、さらにメッキを継続することにより、図
2(d)に示すように、突出した状態のAu製の突起電
極4が形成される。この後、メッキ防止用のカバー13
を取り外すと、図2(e)に示すように、バンプ形成基
板5が得られる。
As shown in FIG. 2 (a), a through hole 2 is formed by sandblasting at a predetermined position of an insulating substrate 1 made of soda glass, and then, as shown in FIG. Electrode film 3 on one side of substrate 1 and on the opposite side
After setting the mask jig (1) 11 and the mask jig (2) 12 in the region where the holes are not formed, the electrode film 3 is formed in the through hole 2
Is formed in a region including. The electrode film 3 can be formed by vacuum vapor deposition or sputtering. In this embodiment, sputtering is used to form a Cr film (thickness: 30 nm) in the lower layer and a Cu film (thickness: 2 μm) in the upper layer. Then, Figure 2
As shown in (c), a plating prevention cover 13 is attached so as to cover the electrode film 3 formed on one side surface of the insulating substrate 1 and is immersed in an Au plating solution to form an Au plating film. Since the electrode film 3 of the insulating substrate 1 is exposed to the plating solution only in the portion of the through hole 2, it is plated only in the through hole 2 and the through hole 2 is filled with the Au plating film as the plating time elapses. Further, by continuing the plating, the protruding electrode 4 made of Au in a protruding state is formed as shown in FIG. After this, the cover 13 for preventing plating
By removing, the bump forming substrate 5 is obtained as shown in FIG.

【0016】図3に示すように、バンプ形成基板5の突
起電極4に素子8の取り出し電極7を位置合わせしてか
ら、素子8を加圧と加熱を行うことで取り出し電極7と
突起電極4の合金接合を行い、この後、中ケース9とふ
た10をセットして封止接続した後に、外部回路のプリ
ント基板に半田付けするための電極として表面電極6を
スクリーン印刷により形成して電子部品を完成させる。
As shown in FIG. 3, the extraction electrode 7 of the element 8 is aligned with the projection electrode 4 of the bump forming substrate 5, and then the element 8 is pressed and heated to thereby extract the extraction electrode 7 and the projection electrode 4. After the inner case 9 and the lid 10 are set and sealed and connected, the surface electrode 6 is formed by screen printing as an electrode for soldering to the printed circuit board of the external circuit to form an electronic component. To complete.

【0017】本実施例では、素子8として表面弾性波素
子を用い、取り出し電極7の材料はAlとしたので、突
起電極4のAuとはAu−Alの合金接合により接続し
た。
In this embodiment, since the surface acoustic wave element was used as the element 8 and the material of the extraction electrode 7 was Al, it was connected to Au of the protruding electrode 4 by Au-Al alloy bonding.

【0018】また、バンプ形成基板5と中ケース9とふ
た10は同一材料であるソーダガラス製としたので、ソ
ーダガラス同士の直接接合技術を用いて、封止接合は3
00℃、5分間で完了した。
Further, since the bump forming substrate 5, the middle case 9 and the lid 10 are made of soda glass which is the same material, the direct joining technique of the soda glasses is used and the sealing joining is 3
Completed in 5 minutes at 00 ° C.

【0019】以上のように本実施例によれば、素子8の
取り出し電極7をバンプ形成基板5の突起電極4と直接
接合させているので、大きさを小型化でき、高周波帯域
で使用する素子8を組み込んだときはインダクタンス変
動による電気的特性の周波数変動が生じず、製造工程が
簡単で製造コストを低減できる。
As described above, according to this embodiment, since the extraction electrode 7 of the element 8 is directly bonded to the bump electrode 4 of the bump forming substrate 5, the size can be reduced and the element used in a high frequency band can be used. When No. 8 is incorporated, the frequency variation of the electrical characteristics due to the inductance variation does not occur, the manufacturing process is simple and the manufacturing cost can be reduced.

【0020】なお、本実施例では、素子8を表面弾性波
素子としたが、半導体素子等の他の素子としてもよい。
また、突起電極4のメッキ材料としてAuを用いたが、
Auに限定されるものではなく、素子8の取り出し電極
7の材料を適当に選択することにより、各種メッキ材料
も使用可能である。たとえば、素子8の取り出し電極7
の表面を半田とするときには、突起電極4としてはA
u,Sn,半田が使用可能であり、取り出し電極7の表
面をAuとしたときには、突起電極4としてはAu,S
n,半田が少なくとも表面に形成されていれば使用可能
であり、取り出し電極7の表面がSnであるときには、
突起電極4としてはAuが使用可能である。
Although the element 8 is a surface acoustic wave element in this embodiment, it may be another element such as a semiconductor element.
Further, Au is used as the plating material for the bump electrodes 4,
The material is not limited to Au, and various plating materials can be used by appropriately selecting the material of the extraction electrode 7 of the element 8. For example, the extraction electrode 7 of the element 8
When soldering the surface of the
u, Sn, or solder can be used, and when the surface of the take-out electrode 7 is Au, Au, S is used as the protruding electrode 4.
n, the solder can be used as long as it is formed on at least the surface, and when the surface of the extraction electrode 7 is Sn,
Au can be used as the protruding electrode 4.

【0021】また、本実施例では電極膜3として、Cu
/Cr2層積層膜を用いたが、メッキ可能な金属であれ
ばよく、Cu/Cr2層積層膜に限定されるものではな
い。
In this embodiment, the electrode film 3 is made of Cu.
Although the / Cr two-layer laminated film is used, it is not limited to the Cu / Cr two-layer laminated film as long as it is a metal that can be plated.

【0022】また、取り出し電極7と突起電極4の合金
接合には、加圧と加熱に超音波加工を併用してもよい。
For the alloy joining of the extraction electrode 7 and the protruding electrode 4, ultrasonic processing may be used together with pressurization and heating.

【0023】さらに、本実施例の中ケース9とふた10
に代えて、中ケース9とふた10を一体化したカバー
(図示せず)に用いてもよい。
Further, the middle case 9 and the lid 10 of the present embodiment.
Instead of this, a cover (not shown) in which the middle case 9 and the lid 10 are integrated may be used.

【0024】(実施例2)以下本発明の第2の実施例に
ついて、図面を参照しながら説明する。
(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

【0025】図4に示すように、アルミナ板製の絶縁性
基板21に形設した貫通孔22とその周辺の両面部とに
設けた電極膜23を有するパッケージ基板24と、電極
膜23と合金接合する取り出し電極25を有する素子2
6と、パッケージ基板24と接合する金属ふた27を備
えた構成である。本実施例では、素子26に電極26a
を有する半導体素子を用いた。
As shown in FIG. 4, a package substrate 24 having a through hole 22 formed in an insulating substrate 21 made of an alumina plate and electrode films 23 provided on both sides around the through hole 22, an electrode film 23 and an alloy. Element 2 having extraction electrode 25 to be joined
6 and a metal lid 27 joined to the package substrate 24. In this embodiment, the element 26 has an electrode 26a.
A semiconductor element having

【0026】以下、上記構成の電子部品の製造方法につ
いて説明する。まず、図5に示したパッケージ基板24
は、以下のようにして作成した。アルミナ板製の絶縁性
基板21の所定の位置にサンドブラストにより貫通孔2
2を形設し、絶縁性基板21の両面部で電極膜23を形
成しない領域にメタルマスクを設置した後に、真空蒸着
やスパッタリングにより、貫通孔22を含むその周辺の
両面部に電極膜23を形成して、パッケージ基板24を
作成した。本実施例では、電極膜23をスパッタリング
により成膜し、下層にTi膜(膜厚:50nm)、上層
にAu膜(膜厚:7μm)を形成した。次に、図6に示
すように、パッケージ基板24上に素子26の取り出し
電極25を貫通孔22と一致するように素子26を位置
合わせして、素子26を加圧と加熱して取り出し電極2
5のAlと電極膜23のAuとを合金接合する。このと
き、貫通孔22の大きさは取り出し電極25の大きさに
比べて小さく構成してあり、取り出し電極25と電極膜
23との接合領域で周辺を覆われることで外気との封止
も達成される。この後、金属ふた27をパッケージ基板
24と位置合わせして半田付けにより接合して、電子部
品を完成させる。
Hereinafter, a method of manufacturing the electronic component having the above structure will be described. First, the package substrate 24 shown in FIG.
Was created as follows. A through hole 2 is formed by sandblasting at a predetermined position of an insulating substrate 21 made of an alumina plate.
2 is formed, and after a metal mask is placed on the regions of the insulating substrate 21 where the electrode film 23 is not formed, the electrode film 23 is formed on both sides of the periphery including the through hole 22 by vacuum deposition or sputtering. Then, the package substrate 24 was formed. In this example, the electrode film 23 was formed by sputtering, a Ti film (film thickness: 50 nm) was formed in the lower layer, and an Au film (film thickness: 7 μm) was formed in the upper layer. Next, as shown in FIG. 6, the element 26 is aligned on the package substrate 24 so that the lead-out electrode 25 of the element 26 is aligned with the through hole 22, and the element 26 is pressurized and heated to take out the lead-out electrode 2.
5 and Al of the electrode film 23 are alloy-bonded. At this time, the size of the through hole 22 is smaller than the size of the extraction electrode 25, and the periphery thereof is covered with the bonding region between the extraction electrode 25 and the electrode film 23, thereby achieving sealing with the outside air. To be done. After that, the metal lid 27 is aligned with the package substrate 24 and joined by soldering to complete the electronic component.

【0027】以上のように本実施例によれば、電極膜2
3の段差により突起させた電極を形成し、電極膜23と
取り出し電極25の接合部が貫通孔22を囲うようにす
ることで貫通孔22を封止した構成により、前述実施例
1の効果に加えて、メッキ加工が不要となるので、パッ
ケージ基板24の作成が簡単となり、製造コストがより
低減できる。なお、本実施例では、素子26を半導体素
子としたが、表面弾性波素子等の他の素子であってもよ
い。また、パッケージ基板24の電極膜23としてAu
/Ti積層膜を用いたが、取り出し電極25の材料との
組み合わせで最適な構成を選択できることはいうまでも
ない。また、金属ふた27に代えて、前述実施例1の中
ケース9とふた10もしくは中ケース9とふた10を一
体化したカバーを用いてもよい。
As described above, according to this embodiment, the electrode film 2
By forming a projecting electrode by the step of No. 3 and sealing the through hole 22 by making the bonding portion of the electrode film 23 and the extraction electrode 25 surround the through hole 22, the effect of the first embodiment can be obtained. In addition, since the plating process is unnecessary, the package substrate 24 can be easily manufactured and the manufacturing cost can be further reduced. Although the element 26 is a semiconductor element in this embodiment, it may be another element such as a surface acoustic wave element. Further, Au is used as the electrode film 23 of the package substrate 24.
Although the / Ti laminated film was used, it is needless to say that the optimum configuration can be selected by combining it with the material of the extraction electrode 25. Further, instead of the metal lid 27, a cover in which the inner case 9 and the lid 10 or the inner case 9 and the lid 10 are integrated may be used.

【0028】[0028]

【発明の効果】以上の説明からも明らかなように本発明
は、絶縁性基板の貫通孔に形成した電極膜を介して設け
た突起電極を有するバンプ形成基板と、表面電極と、取
り出し電極を有する素子と、中ケースとふたを備え、突
起電極と取り出し電極を接合し、ふたをバンプ形成基板
に取り付け封止接合した構成、また、絶縁性基板の素子
の取り出し電極と一致する位置に、貫通孔を設け、この
貫通孔を含む絶縁性基板の片面に電極層を形成し、つい
で絶縁性基板の貫通孔以外の電極膜を形成した面を絶縁
体で覆い、貫通孔のみにメッキを行い貫通孔を埋めると
ともに、絶縁性基板よりも突出した形状の突起電極を設
けたバンプ形成基板を作成し、バンプ形成基板上に取り
出し電極を突起電極と一致させて位置合わせした後、加
圧と加熱して合金接続を行い、中ケースとふたで封止す
る方法により、小型化でき、高周波帯域で使用する素子
を組み込んだときに、インダクタンス変動による電気的
特性の周波数変動が生じず、製造工程が簡単でコスト高
にならない優れた電子部品およびその製造方法を実現で
きるものである。
As is apparent from the above description, according to the present invention, a bump forming substrate having a bump electrode provided via an electrode film formed in a through hole of an insulating substrate, a surface electrode, and an extraction electrode are provided. The device has an element, a middle case, and a lid, and the protruding electrode and the lead-out electrode are joined together, and the lid is attached to the bump forming substrate and sealed and joined. A hole is provided, an electrode layer is formed on one surface of the insulating substrate including the through hole, then the surface of the insulating substrate on which the electrode film is formed other than the through hole is covered with an insulator, and only the through hole is plated and penetrated. Create a bump-formed substrate that fills the holes and is provided with protruding electrodes that are more protruding than the insulating substrate, align the extraction electrodes on the bump-formed substrate with the protruding electrodes, and then apply pressure and heat. Alloy Continuing, and by encapsulating with a middle case and lid, it can be miniaturized, and when incorporating an element used in the high frequency band, the frequency variation of the electrical characteristics does not occur due to inductance variation, the manufacturing process is simple and the cost is low. It is possible to realize an excellent electronic component that does not become expensive and a manufacturing method thereof.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の電子部品の断面図FIG. 1 is a sectional view of an electronic component according to a first embodiment of the present invention.

【図2】同電子部品のバンプ形成基板の製造方法を工程
順に示した断面図
FIG. 2 is a sectional view showing a method of manufacturing a bump-formed substrate of the electronic component in the order of steps.

【図3】同電子部品のバンプ形成基板に素子を接合した
状態の断面図
FIG. 3 is a cross-sectional view showing a state in which an element is bonded to a bump forming substrate of the electronic component.

【図4】本発明の第2の実施例の電子部品の断面図FIG. 4 is a sectional view of an electronic component according to a second embodiment of the present invention.

【図5】同電子部品のパッケージ基板の断面図FIG. 5 is a sectional view of a package substrate of the electronic component.

【図6】同電子部品のパッケージ基板に素子を接合した
状態の断面図
FIG. 6 is a cross-sectional view showing a state where an element is bonded to a package substrate of the electronic component.

【図7】従来の電子部品の一部を欠載して内部を示した
外観斜視図
FIG. 7 is an external perspective view showing the inside by partially omitting a conventional electronic component.

【図8】図7のA−A断面図8 is a sectional view taken along line AA of FIG.

【符号の説明】[Explanation of symbols]

1 絶縁性基板 2 貫通孔 3 電極膜 4 突起電極 5 バンプ形成基板 6 表面電極 7 取り出し電極 8 素子 9 中ケース 10 ふた 1 Insulating Substrate 2 Through Hole 3 Electrode Film 4 Projection Electrode 5 Bump Forming Substrate 6 Surface Electrode 7 Extraction Electrode 8 Element 9 Middle Case 10 Lid

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板に形設した貫通孔に形成した
電極膜を介して設けた突起電極を有するバンプ形成基板
と、前記電極膜に接合し外部回路と接続する表面電極
と、前記突起電極と一致する位置に配設した前記バンプ
形成基板と接合する取り出し電極を有する素子と、金属
もしくはセラミックもしくはガラス製の中ケースとふた
を備え、前記突起電極と前記取り出し電極を接合し、前
記中ケースとふたを前記バンプ形成基板に取り付け封止
接合した電子部品。
1. A bump forming substrate having a bump electrode provided via an electrode film formed in a through hole formed in an insulating substrate, a surface electrode bonded to the electrode film and connected to an external circuit, and the protrusion. An element having a lead-out electrode to be joined to the bump forming substrate disposed at a position corresponding to the electrode, a middle case made of metal, ceramic, or glass and a lid are provided, and the protruding electrode and the lead-out electrode are joined to each other. An electronic component in which a case and a lid are attached to the bump forming substrate and sealed and joined.
【請求項2】 取り出し電極を有する素子と、絶縁性基
板に形設した貫通孔とその周辺の両面部とに形成した電
極膜を有し、かつ前記素子の取り出し電極と接続する面
側の前記電極膜の形成領域を前記取り出し電極の領域よ
りは大きくしない構成としたパッケージ基板と、封止す
るふたを備え、前記電極膜と前記取り出し電極を接合
し、前記ふたを前記パッケージ基板に取り付け封止接合
した電子部品。
2. An element having a lead-out electrode, an electrode film formed on a through-hole formed in an insulating substrate and both side portions around the through-hole, and the surface side of the element being connected to the lead-out electrode. A package substrate having a structure in which an electrode film formation region is not larger than the extraction electrode region and a lid for sealing are provided, the electrode film and the extraction electrode are joined, and the lid is attached to the package substrate for sealing. Bonded electronic components.
【請求項3】 絶縁性基板の素子の取り出し電極と一致
する位置に貫通孔を設け、前記貫通孔を含む前記絶縁性
基板の片面に電極膜を形成し、ついで前記絶縁性基板の
貫通孔以外の電極膜を形成した面を絶縁体で覆い、前記
貫通孔のみにメッキを行い、前記貫通孔を埋めるととも
に前記絶縁性基板よりも突出した形状の突起電極を設け
たバンプ形成基板を作成する工程と、前記バンプ形成基
板上に前記素子の取り出し電極が前記突起電極と一致す
るように位置合わせした後、加圧と加熱またはさらに超
音波加工を併用して合金接続を行う工程と、ついで、金
属もしくはセラミックもしくはガラス製の中ケースとふ
たで封止する工程とを有する電子部品の製造方法。
3. An insulating substrate is provided with a through hole at a position corresponding to a lead-out electrode of an element, an electrode film is formed on one surface of the insulating substrate including the through hole, and then a portion other than the through hole of the insulating substrate is formed. A step of covering the surface on which the electrode film is formed with an insulator, plating only the through-holes, filling the through-holes, and forming a bump-forming substrate provided with a protruding electrode projecting from the insulating substrate. And a step of aligning the extraction electrode of the element on the bump formation substrate so as to be coincident with the protruding electrode, and then performing alloy connection by using pressure and heating or ultrasonic processing in combination, and then, metal Alternatively, there is provided a method of manufacturing an electronic component, which includes a ceramic or glass middle case and a step of sealing with a lid.
【請求項4】 絶縁性基板とふたとの接合を半田付けま
たはガラスによる溶着または樹脂接着剤による接合とし
た請求項3記載の電子部品の製造方法。
4. The method of manufacturing an electronic component according to claim 3, wherein the insulating substrate and the lid are joined by soldering, welding with glass, or joining with a resin adhesive.
【請求項5】 ガラス製の絶縁性基板とそれと同じガラ
ス製のふたとの接合をガラス同士の直接接合とした請求
項3記載の電子部品の製造方法。
5. The method of manufacturing an electronic component according to claim 3, wherein the glass-made insulating substrate and the same glass lid are bonded directly to each other.
【請求項6】 絶縁性基板の素子の取り出し電極と一致
する位置に前記取り出し電極の領域よりも小さな形状の
貫通孔を設け、前記絶縁性基板の貫通孔とその周辺の両
面部とに電極膜を形成し、かつ前記素子の取り出し電極
と接触する面側の前記電極膜の形成領域を前記取り出し
電極の領域よりは大きくしない構成としたパッケージ基
板を作成する工程と、前記パッケージ基板上に前記素子
の取り出し電極が前記貫通孔の電極膜と一致するように
位置合わせした後、加圧と加熱またはさらに超音波加工
を併用して合金接合を行う工程と、ついで、ふたで封止
する工程とを有する電子部品の製造方法。
6. A through-hole having a shape smaller than the area of the lead-out electrode is provided at a position corresponding to the lead-out electrode of the element of the insulating substrate, and an electrode film is formed on the through-hole of the insulating substrate and both side portions around the through-hole. And forming a package substrate having a structure in which the formation region of the electrode film on the surface side of the device that contacts the extraction electrode is not larger than the region of the extraction electrode, and the device on the package substrate. After aligning the extraction electrode so that it coincides with the electrode film of the through-hole, a step of alloy joining using pressure and heating or ultrasonic processing in combination, and then a step of sealing with a lid are performed. A manufacturing method of an electronic component having
【請求項7】 絶縁性基板とふたとの接合を半田付けま
たはガラスによる溶着または樹脂接着剤による接合とし
た請求項6記載の電子部品の製造方法。
7. The method of manufacturing an electronic component according to claim 6, wherein the insulating substrate and the lid are joined by soldering, welding with glass, or joining with a resin adhesive.
【請求項8】 ガラス製の絶縁性基板とそれと同じガラ
ス製のふたとの接合をガラス同士の直接接合とした請求
項6記載の電子部品の製造方法。
8. The method of manufacturing an electronic component according to claim 6, wherein the glass-made insulating substrate and the same glass lid are bonded directly to each other.
JP1685395A 1995-02-03 1995-02-03 Electronic component and method of manufacturing the same Expired - Fee Related JP3546506B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1685395A JP3546506B2 (en) 1995-02-03 1995-02-03 Electronic component and method of manufacturing the same

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Application Number Priority Date Filing Date Title
JP1685395A JP3546506B2 (en) 1995-02-03 1995-02-03 Electronic component and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH08213764A true JPH08213764A (en) 1996-08-20
JP3546506B2 JP3546506B2 (en) 2004-07-28

Family

ID=11927782

Family Applications (1)

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Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0951062A3 (en) * 1998-04-18 2003-10-22 TDK Corporation Electronic part and manufacturing method therefor
JP2006197554A (en) * 2004-12-17 2006-07-27 Seiko Epson Corp Surface acoustic wave device and method of manufacturing the same, ic card, and mobile electronic equipment
JP2007516602A (en) * 2003-09-26 2007-06-21 テッセラ,インコーポレイテッド Manufacturing structure and method of a capped tip containing a flowable conductive medium
JP2007201164A (en) * 2006-01-26 2007-08-09 Matsushita Electric Ind Co Ltd Method for generating glass cap for electronic component
US7436272B2 (en) 2004-06-25 2008-10-14 Murata Manufacturing Co., Ltd. Piezoelectric device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0951062A3 (en) * 1998-04-18 2003-10-22 TDK Corporation Electronic part and manufacturing method therefor
JP2007516602A (en) * 2003-09-26 2007-06-21 テッセラ,インコーポレイテッド Manufacturing structure and method of a capped tip containing a flowable conductive medium
US7436272B2 (en) 2004-06-25 2008-10-14 Murata Manufacturing Co., Ltd. Piezoelectric device
JP2006197554A (en) * 2004-12-17 2006-07-27 Seiko Epson Corp Surface acoustic wave device and method of manufacturing the same, ic card, and mobile electronic equipment
JP2007201164A (en) * 2006-01-26 2007-08-09 Matsushita Electric Ind Co Ltd Method for generating glass cap for electronic component

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