JPH0781282A - Information medium - Google Patents

Abstract

PURPOSE:To prevent electric discharge from a metallic frame, charged with static electricity, to a lower side wiring pattern without enlarging the size of an information medium, having the shape of a coin provided with the metallic frame. CONSTITUTION:A lower side wiring pattern 2 is formed at a part excluding the outer peripheral part of the lower surface of a substrate 1. As a result, an interval (t1) between the outer end surface of the lower side wiring pattern 2 and the internal peripheral surface of a metallic frame 8 can be enlarged without increasing an interval (t2) between the outer peripheral surface of the substrate 1 and the inner peripheral surface of the metallic frame 8. Accordingly, electric discharge from the metallic frame 8, charged with static electricity, to the lower side wiring pattern 2 can be prevented without increasing the size of an information medium itself whereby the electrostatic destruction of an IC chip 4 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable information medium containing an IC chip for processing or storing data.

[0002]

2. Description of the Related Art A portable information medium has a flat plate shape such as a card shape or a coin shape, and an IC chip for processing or storing data is mounted on one surface of a substrate so as to be compatible with a processing device. There is a structure in which a plurality of connection terminals, which are respectively connected to a plurality of external terminals of a processing device when data is exchanged between them, are provided on the other surface of the substrate.

2A and 2B show an example of such a conventional information medium. This information medium includes a disk-shaped substrate 1 made of resin, glass epoxy or the like. A lower wiring pattern 2 including a plurality of connection terminals is formed on the lower surface of the substrate 1, and an upper wiring pattern 3 is formed on the upper surface.
Are formed. Both wiring patterns 2 and 3 are connected to each other through a through hole conducting portion (not shown) formed on the substrate 1. EE is provided at a predetermined position on the upper surface of the substrate 1.
An IC chip 4 made of a semiconductor element such as a PROM or a mask ROM is mounted by being bonded with an adhesive (not shown). The IC chip 4 is wire-bonded to the upper wiring pattern 3 via the gold wire 5. This wire bonding portion is sealed with a sealing material 6 made of resin such as epoxy resin or silicon resin.
An insulating exterior material 7 made of a resin such as vinyl chloride is provided on the upper surface of the substrate 1 including the sealing material 6. A ring-shaped metal frame body 8 made of metal such as stainless steel is provided on the outer peripheral surface of the insulating exterior material 7.

When forming the wiring patterns 2, 3 and the like on the substrate 1, first, copper foil is laminated on both upper and lower surfaces of the substrate 1 with an adhesive or the like, and then through holes are formed at predetermined places, and then, through holes are formed. The surfaces of both copper foils and the insides of the through holes are electrolessly plated, and then unnecessary portions of the copper foils and the copper foils are etched and removed by a method such as photolithography. The wiring pattern 2 is formed and the substrate 1 is formed.
An upper wiring pattern 3 is formed on the upper surface of the above, and then copper plating, nickel plating and gold plating are applied in this order to the surfaces of both wiring patterns 2 and 3 by electrolytic plating. Therefore, the wiring patterns 2 and 3 substantially include these electrolytic platings. Here, the reason why the gold plating is performed is firstly to improve electrical connectivity when the IC chip 4 is wire-bonded to the upper wiring pattern 3 using the gold wire 5, and secondly, This is to prevent the connection terminal, which is a part of the side wiring pattern 2, from being oxidized and to ensure the electrical connection with the external terminal of the processing device. Also, the reason for applying nickel plating is that the adhesion between copper and gold is not good, so by plating nickel with good adhesion to both copper and gold, it is possible to prevent the gold plating from peeling off. . When electrolytic plating is performed, since supply wiring for supplying a plating current is required, the wiring patterns 2,
The supply wiring connected to 3 is also formed. Therefore, it should be noted that the wiring patterns 2 and 3 may include this supply wiring.

On the other hand, when mass-producing the substrate 1 on which the wiring patterns 2 and 3 are formed as described above, a plurality of upper and lower wiring patterns 3 and 2 are formed in the same pattern on the upper and lower surfaces of a relatively large substrate. And upper and lower common terminals for supplying a plating current, and further upper and lower supply wirings for connecting the upper and lower wiring patterns 3 and 2 to the upper and lower common terminals, and the upper and lower common terminals. A plating power source is connected to the plate for electrolytic plating, and then this relatively large substrate is cut along a predetermined cutting line.
In this case, since the cutting line intersects the upper and lower supply wirings, the substrate is cut together with the intersecting upper and lower supply wirings. As a result, as shown in FIG. 2B, a part of the supply wiring, which is a part of the upper and lower wiring patterns 3 and 2, remains at each end of the upper and lower surfaces of the substrate 1. And
In order to prevent the outer end surfaces of the upper and lower wiring patterns 3 and 2 and the inner peripheral surface of the metal frame 8 at the end portion of the substrate 1 from contacting each other,
An insulating exterior material 7 is interposed between the outer peripheral surface of the substrate 1 and the inner peripheral surface of the metal frame body 8.

[0006]

As described above, in the conventional information medium, the outer end surfaces of the upper and lower wiring patterns 3 and 2 at the end portion of the substrate 1 and the inner peripheral surface of the metal frame body 8 do not contact each other. In addition, the insulating exterior material 7 is interposed between the outer peripheral surface of the substrate 1 and the inner peripheral surface of the metal frame body 8. However,
Since the lower wiring pattern 2 at the end of the substrate 1 is exposed to the outside, when the metal frame 8 is charged with static electricity due to friction with the wearer's clothes or the like, this static electricity is transmitted through the air to the substrate 1 Discharge toward the lower wiring pattern 2 at the end of the, and further through-hole conducting portion, upper wiring pattern 3
Also, there is a problem that static electricity may reach the IC chip 4 through the gold wire 5, resulting in electrostatic damage to the IC chip 4. It should be noted that by increasing the distance between the outer peripheral surface of the substrate 1 and the inner peripheral surface of the metal frame body 8, it is possible to prevent the discharge of static electricity from the metal frame body 8 to the lower wiring pattern 2. Then, there is another problem that the information medium itself becomes large. An object of the present invention is to provide an information medium capable of preventing electrostatic discharge from the metal frame body to the lower wiring pattern without increasing the size.

[0007]

According to the present invention, an upper wiring pattern and a lower wiring pattern are formed on an upper surface and a lower surface, respectively, and a through-hole conducting portion for connecting these wiring patterns to each other is formed on a substrate. In an information medium including an IC chip mounted on the upper surface of the substrate and a metal frame body provided on the outer peripheral portion of the substrate in a state of being insulated from the both wiring patterns, a part of the upper wiring pattern is provided. It is formed by extending to the outer peripheral edge of the substrate, and the lower wiring pattern is formed on a portion of the substrate excluding the outer peripheral portion.

[0008]

According to the present invention, even if only the upper wiring pattern has the plating current supply wiring function, the lower wiring pattern is connected to the upper wiring pattern through the through-hole conducting portion. Plating current can also be supplied to the substrate, and as a result, the lower wiring pattern is formed on the part of the board excluding the outer periphery, so that electrostatic discharge from the metal frame to the lower wiring pattern can be achieved without increasing the size. Can be prevented.

[0009]

1 (A) and 1 (B) show an information medium in an embodiment of the present invention. In these figures, parts having the same names as those in FIGS. 2A and 2B are designated by the same reference numerals, and description thereof will be omitted as appropriate. In this information medium, a part of the upper wiring pattern 3 is formed to extend to the outer peripheral edge of the substrate 1, so that the upper wiring pattern 3 including the supply wiring is formed on the upper surface of the substrate 1. On the other hand, the supply wiring is not formed on the lower surface of the substrate 1, and only the lower wiring pattern 2 including the connection terminals is formed on the portion of the substrate 1 excluding the outer peripheral portion.

As described above, in this information medium, only the upper wiring pattern 3 has the plating current supply wiring function, but the lower wiring pattern 2 is connected to the upper wiring pattern 3 via the through-hole conducting portion. Therefore, the plating current can be supplied also to the lower wiring pattern 2. As a result, by forming the lower wiring pattern 2 on the portion of the substrate 1 excluding the outer peripheral portion, the distance t ₁ between the outer end surface of the lower wiring pattern 2 and the inner peripheral surface of the metal frame body 8 is increased. Therefore, electrostatic discharge from the metal frame body 8 to the lower wiring pattern 2 can be prevented without increasing the size of the information medium itself. Therefore, electrostatic breakdown of the IC chip 4 due to such static electricity can be prevented, and the antistatic characteristic can be improved.

Here, an example of specific dimensions of the information medium will be described. The thickness of the copper foil for forming the lower wiring pattern 2 is 0.02 mm, the thickness of copper plating by electroless plating and electrolytic plating is 0.01 mm,
The thickness of nickel plating by electrolytic plating is 0.005m
m, and the thickness of gold plating by electrolytic plating is 0.000
It was set to 5 mm. Then, the lower surface of the lower wiring pattern 2 and the lower surface of the metal frame body 8 are flush with each other, and the lower wiring pattern 2
The distance t ₁ between the outer end surface of the metal frame and the inner peripheral surface of the metal frame body 8 is 0.5 m.
When m was set, static electricity was not discharged from the metal frame body 8 to the lower wiring pattern 2. On the other hand, the substrate 1
The distance t ₂ between the outer peripheral surface of the and the inner peripheral surface of the metal frame 8 is 0.2 m.
When the lower wiring pattern 2 was extended to the outer peripheral edge of the substrate 1, static electricity was discharged from the metal frame 8 to the lower wiring pattern 2. Therefore, the distance t ₁ between the outer end surface of the lower wiring pattern 2 and the inner peripheral surface of the metal frame body 8 is 0.5.
If the thickness is equal to or larger than mm, it is possible to prevent electrostatic discharge from the metal frame 8 to the lower wiring pattern 2 without increasing the size of the information medium itself.

The method of mounting the IC chip 4 on the substrate 1 is not limited to wire bonding.
Of course, flip chip bonding or the like may be used. The number of IC chips 4 is EEPR.
The present invention is not limited to the case of mounting one chip such as OM and mask ROM, but may be the case of mounting two chips such as a memory chip such as EEPROM and mask ROM and a controller chip such as ASIC. More chips may be used.

[0013]

As described above, according to the present invention, the lower wiring pattern is connected to the upper wiring pattern through the through hole conducting portion even if only the upper wiring pattern has the plating current supply wiring function. Therefore, the plating current can be supplied also to the lower wiring pattern, and as a result, by forming the lower wiring pattern in the portion excluding the outer peripheral portion of the substrate, the plating can be performed from the metal frame without increasing the size. It is possible to prevent static electricity discharge to the side wiring pattern,
The antistatic property can be improved.

[Brief description of drawings]

FIG. 1A is a sectional view of an information medium according to an embodiment of the present invention, and FIG. 1B is an enlarged view of a part thereof.

FIG. 2A is a sectional view of an example of a conventional information medium,
(B) is an enlarged view of a part thereof.

[Explanation of symbols]

 1 substrate 2 lower wiring pattern 3 upper wiring pattern 4 IC chip 7 insulating exterior material 8 metal frame

Claims (1)

[Claims] 1. A substrate having an upper wiring pattern and a lower wiring pattern formed on an upper surface and a lower surface, respectively, and a through-hole conducting portion connecting the wiring patterns to each other, and a substrate mounted on the upper surface of the substrate. In an information medium including an IC chip and a metal frame body provided on an outer peripheral portion of the substrate in a state of being insulated from the both wiring patterns, a part of the upper wiring pattern extends to an outer peripheral end of the substrate. An information medium, wherein the lower wiring pattern is formed on a portion of the substrate other than the outer peripheral portion.