JPH0778883A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the integration degree while a necessary reverse voltage is ensured between an N-type region layer and a P-type region layer in a CMOS semiconductor device operated at a low voltage. CONSTITUTION:A semiconductor device has a P-type region layer 11, an N-type region layer 12 which is adjacent to the layer 11, P-type high-concentration region layers 13, which are formed in the surface layer of the layer 11 and are connected to an electrode for fixing a potential in the layer 11, and N-type high-concentration region layers 14, which are formed in the surface layer of the layer 12 and are connected to an electrode for fixing a potential in the layer 12, and the layers 13 and the layers 14 are adjacent to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a CMOS structure which operates at a low voltage.

[0002]

2. Description of the Related Art FIGS. 5A and 5B show a conventional CMOS.
5A is a partial sectional view and a plan view of FIG. 5, and FIG. 5A corresponds to the sectional view taken along the line AA of FIG. In the figure, reference numeral 1 denotes a P-type silicon substrate (P-type region layer), which serves as a back gate of an n-channel transistor (not shown). 2 is concentration 1 ×
An N-type well (N-type region layer) of about 10 ¹⁶ cm ⁻³ serves as a back gate of a p-channel transistor (not shown).

3 is selective to the surface layer of the P type silicon substrate 1.
1 × 10 formed on the surface¹⁹cm^-3P-type high concentration range
(Not shown) for fixing the potential of the silicon substrate 1 in the sublayer
The electrodes of are connected. 4 is selected as the surface layer of N-type well 2.
Formed density 1 × 10 ²⁰cm^-3N type high concentration
In the region layer, a voltage not shown for fixing the potential of the well 2 is fixed.
The poles are connected.

In order to separate the P-type high-concentration region layer 3 and the N-type high-concentration region layer 4, 7 has a film thickness of several thousand Å, which is formed by selective oxidation on the surface of the silicon substrate 1 in the region between them. It is an isolation insulating film made of a silicon oxide film having a width of about 5 μm.
A PN junction 8 between the well 2 and the silicon substrate 1 is terminated on the surface of the silicon substrate 1 below the isolation insulating film 7. In addition,
Reference numerals 5 and 6 in the drawing are insulating films.

In the above CMOS, the presence of the isolation insulating film 7 causes the P-type high concentration region layer 3 and the N-type high concentration region layer 4 to be P-type.
Since it is formed with a certain distance from the N-junction 8,
The PN junction 8 between the well 2 and the silicon substrate 1 ensures a relatively high reverse breakdown voltage. Therefore, it is possible to operate the transistor with a relatively high voltage corresponding to the reverse breakdown voltage, for example, 5 V or less.

[0006]

In recent years, with the demand for lower voltage and higher speed of semiconductor devices, further miniaturization has been demanded. However, with the above structure,
There is a problem that the degree of integration cannot be increased in order to secure the formation region of the isolation insulating film 7. The present invention was created in view of the problems of the conventional example, and it is possible to achieve high integration while securing a necessary reverse voltage between the N-type region layer and the P-type region layer. It is an object to provide a semiconductor device having a CMOS structure.

[0007]

The above problems are as follows. First, as shown in the principle diagrams of FIGS. 1A and 1B, the P-type region layer 1
1 and an N-type region layer 12 adjacent to the P-type region layer 11,
It is formed on the surface of the P-type region layer 11 and is formed on the surface of the P-type high-concentration region layer 13 and the N-type region layer 12 to which electrodes for fixing the potential of the P-type region layer 11 are connected. , An N-type high-concentration region layer 14 to which an electrode for fixing the potential of the N-type region layer 12 is connected, and the P-type high-concentration region layer 13 and the N-type high-concentration region layer 14 are mutually Second, the P-type region layer is a back gate of an n-channel transistor, as illustrated in FIG. 3B.
This is achieved by the semiconductor device according to the first invention, wherein the N-type region layer is a back gate of a p-channel transistor.

[0008]

[Operation] In the semiconductor device of the present invention, FIG.
As shown in (a) and (b), a P-type high-concentration region layer 13 and an N-type high-concentration region layer 13 to which electrodes for fixing the potential of the P-type region layer 11 are connected.
The N-type high concentration region layers 14 to which the electrodes for fixing the potential of the mold region layer 12 are connected are in contact with each other. Therefore, the isolation insulating film for separating the P-type high concentration region layer 13 and the N-type high concentration region layer 14 is not necessary. Therefore, the degree of integration of the semiconductor device can be increased.

In the above structure, for example, as illustrated in FIG. 3B, the P-type region layer is the back gate of the n-channel transistor and the N-type region layer is the back gate of the p-channel transistor. Applied to CMOS.
By the way, the reverse breakdown voltage of the PN junction formed by the P-type high-concentration region layer and the N-type high-concentration region layer is set to 3 V or more depending on the degree of impurity concentration required to make ohmic contact with the connection electrode. Can be held at. Therefore, even if the P-type high-concentration region layer and the N-type high-concentration region layer are formed in contact with each other, if the operating voltage of the p-channel transistor and the n-channel transistor is 3 V or less, the transistors interfere with each other. Absent.

As described above, the present invention is particularly effective for a CMOS that operates at a low voltage of 3 V or less.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 2 (a) to (d), FIG. 3 (a),
(B) is sectional drawing explaining the manufacturing method of the CMOS inverter which concerns on the Example of this invention. Figure 2 (a)
Indicates the state after the well is formed, and the reference numeral 21 in the figure
Is a P-type silicon substrate (P-type region layer), and 22 is formed selectively by thermal oxidation on the surface of the silicon substrate 21 to be an element isolation region, with the element region of the silicon substrate 21 being covered with a silicon nitride film. A field insulating film made of a silicon oxide film having a film thickness of about 3000Å, and a gate insulating film 23 made of a silicon oxide film having a film thickness of about 300Å formed in the element region surrounded by the field insulating film 22.

Numeral 24 is selectively on the surface layer of the silicon substrate 21.
Impurity concentration of about 1 × 10 ¹⁶cm^-3With N
Type well (N type region layer), 25 is a gate on the well 24
Polysilicon film with a thickness of about 3000Å formed on the insulating film 23
It is a gate electrode composed of a con-membrane. 26 is a silicon substrate
Approximately 3000Å film thickness formed on the gate insulating film 23 on 21
Is a gate electrode made of a polysilicon film. Well 2
4 and the PN junction 27 formed by the silicon substrate 21
It terminates at the surface of the recon substrate 21. The left side of the PN junction is N
It becomes the mold region layer and corresponds to the well 24. Also, PN junction
Is the P-type region layer on the right side of the
Corresponding to the remaining silicon substrate 21.

In such a state, first, as shown in FIG. 2B, the peripheral portion of the gate electrode 25 on the silicon substrate 21 and the region where the N-type high concentration region layer in contact with the PN junction 27 are to be formed. Is covered with a resist mask 28. Then, boron, which is a P-type impurity, is introduced by ion implantation. Next, after removing the resist mask 28, as shown in FIG. 2C, the peripheral portion of the gate electrode 25 on the well 24 and P
A new resist mask 29 covers the region in which the P-type high concentration region layer is to be formed, which is in contact with the N junction 27. Subsequently, phosphorus, which is an N-type impurity, is introduced by ion implantation.

Then, as shown in FIG. 2D, after removing the resist mask 29, heat treatment is performed at a temperature of about 900 ° C. to activate the implanted ions. As a result, the impurity concentration of 1 is formed in the surface layer of the N-type well 24 on both sides of the gate electrode 25.
The P-type S / D region layers 30a and 30b having × 10 ¹⁹ cm ⁻³ are formed, and the N-type high concentration region layer 33 having an impurity concentration of 1 × 10 ²⁰ cm ⁻³ is formed in the region in contact with the PN junction 27.
Is formed. At the same time, the impurity concentration of 1 × 10 ^{20 is formed on} the surface layer of the P-type silicon substrate 21 on both sides of the gate electrode 26.
N-type S / D region layers 32a and 32b having a cm ⁻³ are formed, and at the same time as the surface layer of the P-type silicon substrate 21,
Impurity concentration of 1 × 10 ¹⁹ cm in the region in contact with the PN junction 27
A P-type high concentration region layer 31 having ^-3 is formed.

Next, as shown in FIG. 3A, an interlayer insulating film 34 made of a silicon oxide film having a film thickness of about 5000 Å is formed on the substrate by a chemical vapor deposition method using a silane-based reaction gas. . Then, as shown in FIG. 3B, a P-type S / D
Region layers 30a, 30b, N-type high concentration region layer 33, N-type S / D
After forming contact holes 34a to 34f in the interlayer insulating film 34 on the region layers 32a and 32b and the P-type high concentration region layer 31,
An aluminum film is formed by covering the contact holes 34a to 34f. Next, the aluminum film is patterned to connect the P-type S / D region layers 30a and 30b to the S / D electrodes.
35a and 35b are formed, a back gate electrode 37a connected to the N-type high concentration region layer 33 is formed, and the N-type S / D region layer 32 is formed.
forming S / D electrodes 36a and 36b connected to a and 32b, and
A back gate electrode 37b connected to the high-concentration region layer 31 is formed. As a result, a p-channel transistor is completed in the well 24 and an n-channel transistor is completed in the silicon substrate 21.

The CMO created as described above
In the S inverter, since the N-type high-concentration region layer 33 and the P-type high-concentration region layer 31 are in contact with each other, the reverse breakdown voltage of the PN junction 27 becomes 3 to 4 V, but the p-channel transistor and the n-channel When the operating voltage of the transistors is 3 V or less, a reverse voltage is ensured so that the transistors do not interfere with each other.

FIG. 4 shows a CMO prepared as described above.
It is a circuit wiring diagram which shows the equivalent circuit when S is used as an inverter. In FIG. 4, Tr1 and Tr2 are a p-channel transistor and an n-channel transistor, respectively. The S / D electrodes 35a and 36a are short-circuited, and the gate electrodes 25 and 26 are short-circuited to be connected in series. The back gate electrodes 33 and 31 of Tr1 and Tr2 are connected to the other S / D electrodes 35b and 36b of Tr1 and Tr2, respectively.
The other S / D electrode 36b of Tr2 is grounded.

The CMOS inverter is constituted by such connection, and the other S / D electrode 35b of Tr1 and the other S / D electrode of Tr2 are formed.
A voltage of 3 V or less is applied between the / D electrode 36b. Now, since the N-type high-concentration region layer 33 and the P-type high-concentration region layer 31 are in contact with each other, the reverse breakdown voltage of the PN junction 27 is 3 to 4 V, but the maximum applied voltage is 3 V or less, so that the transistor is a transistor. Tr1 and Tr2 do not interfere with each other.

As described above, the CM according to the embodiment of the present invention
In the OS inverter, the P-type high concentration region layer 31 and the N-type high concentration region layer 33 are formed in contact with each other.
Therefore, unlike the conventional example, an isolation insulating film for separating the P-type high concentration region layer 31 and the N-type high concentration region layer 33 is not required. Therefore, the degree of integration of the semiconductor device can be increased.
This is particularly effective when the transistor is operated at a low voltage of 3V or less.

[0020]

As described above, in the semiconductor device of the present invention, the electrode for fixing the potential of the P-type high concentration region layer and the N-type region layer to which the electrode for fixing the potential of the P-type region layer is connected. The N-type high concentration region layers connected to each other are in contact with each other. Therefore, the isolation insulating film for separating the P-type high concentration region layer and the N-type high concentration region layer is not necessary. For this reason,
High integration of semiconductor devices can be achieved.

In the above structure, the CMOS is such that the P-type region layer is the back gate of the n-channel transistor and the N-type region layer is the back gate of the p-channel transistor.
However, the present invention is particularly effective for a CMOS that operates at a low voltage of 3 V or less.

[Brief description of drawings]

FIG. 1 is a principle cross-sectional view showing a semiconductor device having a CMOS of the present invention.

FIG. 2 is a sectional view (1) showing the method for manufacturing the CMOS inverter according to the embodiment of the present invention.

FIG. 3 is a sectional view (2) showing the method for manufacturing the CMOS inverter according to the embodiment of the present invention.

FIG. 4 is a circuit wiring diagram showing an equivalent circuit of a CMOS inverter according to an embodiment of the present invention.

FIG. 5 is a sectional view showing a semiconductor device having a CMOS according to a conventional example.

[Explanation of symbols]

 11 P-type region layer, 12 N-type region layer, 13,31 P-type high concentration region layer, 14,33 N-type high concentration region layer, 15,16 Insulating film, 21 Silicon substrate (P-type region layer), 22 fields Insulating film, 23 gate insulating film, 24 well (N type region layer), 25,26 gate electrode, 27 PN junction, 28,29 resist mask, 30a, 30b P type S / D region layer, 32a, 32b N type S / D region layer, 34 interlayer insulating film, 34a to 34f contact hole, 35a, 35b, 36a, 36b S / D electrode, 37a, 37b back gate electrode, Tr1 p-channel transistor, Tr2 n-channel transistor.

Claims (2)

[Claims] 1. A P-type region layer, an N-type region layer adjacent to the P-type region layer, and an electrode formed on a surface layer of the P-type region layer for fixing a potential of the P-type region layer. P connected
A high-concentration type region layer and a surface layer of the N-type region layer,
An N-type high-concentration region layer to which an electrode for fixing the potential of the N-type region layer is connected, wherein the P-type high-concentration region layer and the N-type high-concentration region layer are in contact with each other. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the P-type region layer is a back gate of an n-channel transistor, and the N-type region layer is a back gate of a p-channel transistor.