JPH0777964A - Device for correcting synchronizing signal polarity and computer system - Google Patents

Abstract

PURPOSE:To correctly discriminate the polarity of a synchronizing signal regardless of the frequency of the synchronizing signal and to correct the polarity of the synchronizing signal. CONSTITUTION:A count value N is obtained by counting a period when synchronizing signals VSPC, HSPC are a (0) level, and the count value M is obtained by counting the period when the synchronizing signals are a (1) level. Then, the count value N is compared with the count value M, and when N<M, the value of the polarity instruction data K is set to zero, and when N>M, the value of K is set to K=1. The polarity instruction data K is written in a register in a synchronizing signal logical correction part 7. Regardless of the case the polarity of the synchronizing signals outputted from a first display control part 1 is positive logic or negative logic, the period when the synchronizing signals are the (0) level is compared with the period of (1), and the polarity of the synchronizing signals are corrected automatically. The synchronizing signals VXPC, HSPC after polarity correction are imparted to a second display control part 2, and thus, the second display control part 2 is operated normally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal polarity correction device for discriminating the polarity of a sync signal and correcting it to a desired polarity, and a computer system equipped with the same.

[0002]

2. Description of the Related Art Generally, a personal computer is equipped with a display control unit for controlling the display of images, but it is also called a video board or a video card for displaying color still images and moving images at high speed. The second display controller is often mounted. FIG. 15 is a block diagram showing the configuration of a conventional personal computer system equipped with a second display control unit. The personal computer main body 40 includes a CPU 4, a CPU bus 5, and a first display control unit 1 that controls image display of characters and graphics. In addition, the second display control unit 2 is mounted on the personal computer in the form of a video board.

The first display control unit 1 uses the vertical synchronization signal VS.
The PC and the horizontal synchronizing signal HSPC are supplied to the color monitor 3 and the second display control unit 2, and the component video signal LSPC representing a character or graphic image is supplied to the second display control unit 2. The second display control unit 2
The video signal of a color still image or a moving image is combined with the video signal LSPC to generate a component video signal LSMON, and the video signal LSMON is supplied to the color monitor 3. That is, the second display control unit 2 has a function of embedding a color still image or a moving image in a character or graphic image controlled by the first display control unit 1 and displaying it on the color monitor 3. There is.

In recent years, personal computers are usually designed so that the first display control section 1 can be easily replaced, and in some cases, a video board as the first display control section 1 has several tens of video boards. There are more than one type on the market. However, there are various combinations of logic polarities of the vertical synchronizing signal VSPC and the horizontal synchronizing signal HSPC output from these video boards, and they are not necessarily unified. That is, depending on the video board, 2
There are cases where both sync signals are positive logic, one is positive logic and the other is negative logic, and both are negative logic. Therefore, when the second display control unit 2 receives such a synchronization signal, it may not operate normally.

[0005]

By the way, some so-called multi-scan monitors are provided with a polarity discriminating circuit which automatically discriminates the polarity of the synchronizing signal and responds thereto.
However, in recent years, the number of types of video boards has increased, and in reality, not only the polarity of the sync signal but also the frequency of each sync signal varies considerably depending on the video board. For example,
The screen size (number of horizontal dots x number of scanning lines) is (640 x
640), (800 × 600), (1024 × 768), etc., and the frequencies of the sync signals corresponding to these screen sizes are different from each other. As described above, since there is a considerable difference in the frequency of the sync signal, there is a case where the polarity of the sync signal cannot be correctly discriminated by the conventional polarity discriminating circuit.

The present invention has been made in order to solve the above-mentioned problems in the prior art, and corrects the polarity of the synchronization signal regardless of the frequency of the synchronization signal and corrects the polarity of the synchronization signal. To aim.

[0007]

In order to solve the above-mentioned problems, the sync signal polarity correction device of the present invention is characterized in that the sync signal is at the first level and the length of the first period is
The period comparison means for measuring the length of the second period in which the synchronization signal is at the second level and comparing the length of the first period with the length of the second period, and the period comparison means. Polarity correction means for correcting the polarity of the synchronization signal to a desired polarity according to the comparison result.

Since the polarity of the synchronizing signal is corrected according to the comparison between the length of the period of the first level and the period of the second level of the synchronizing signal, the polarity of the synchronizing signal is irrespective of the frequency of the synchronizing signal. Can be correctly determined and the polarity of the synchronization signal can be corrected.

The period comparison means measures the lengths of the first and second periods, respectively, to obtain the first and second periods.
A digital computer having a program for comparing the lengths of the periods and outputting a polarity indicating signal representing the comparison result; and a signal transmitting means for giving the polarity indicating signal from the digital computer to the polarity correcting means.
May be provided. In this way, it is not necessary to provide a new hardware circuit as the period comparison means.

The measurement of the lengths of the first and second periods may be carried out by repeating an addition operation for adding predetermined values.

The period comparing means includes first measuring means for measuring the length of the first period, second measuring means for measuring the length of the second period, and the first measuring means. Comparing means for comparing the length of the period and the length of the second period may be provided.

Further, the first measuring means includes a first counter for counting the number of pulses of a predetermined clock signal in the first period, and the second measuring means in the second period. A second counter for counting the number of pulses of the predetermined clock signal may be included. The count values of the first and second counters indicate the lengths of the first and second periods, respectively.

The first and second counters may be up counters.

On the other hand, the period comparing means measures the difference between the length of the first period and the length of the second period, and the difference measured by the measuring means to a predetermined reference value. It may be provided with a comparison means for comparing with. In this way, the polarity can also be determined by measuring the difference between the length of the first period and the length of the second period.

The measuring means includes an up-down counter that counts up the number of pulses of the predetermined clock signal in the first period and counts down the number of pulses of the predetermined clock signal in the second period. You may stay. If the up / down counter is used, the difference in the length of the period can be measured by one counter.

The sync signal polarity correction device may further include display control means for outputting a video signal in synchronization with the sync signal whose polarity is corrected by the polarity correction means.

If the sync signal is modified to have a polarity suitable for the display control means, a sync signal suitable for the display control means is provided regardless of the polarity of the sync signal supplied to the sync signal polarity modification device. be able to.

The computer system according to the present invention comprises:
Display means for displaying an image, first display control means for generating a sync signal given to the display means, and a sync signal polarity for discriminating the polarity of the sync signal and correcting the sync signal to a desired polarity. Correction means, and a second display control means for outputting to the display means a video signal synchronized with the sync signal whose polarity has been corrected by the polarity correction means. The length of the first period at the first level and the synchronization signal
According to the comparison result by the period comparison means for measuring the length of the second period at the level of, and comparing the length of the first period with the length of the second period, Polarity correcting means for correcting the polarity of the synchronization signal to a desired polarity.

Since the polarity of the synchronization signal output from the first display control means can be corrected to the polarity suitable for the second display control means by the synchronization signal polarity correction means, the first display control means An image can be displayed on the display means regardless of the polarity of the sync signal output.

[0020]

【Example】

A. First Embodiment: FIG. 1 is a perspective view showing a computer system as a first embodiment of the present invention. This computer system includes a personal computer main body 4
0, color monitor 3, keyboard 50, mouse 5
2 and a video player 60. An expansion board 41 is inserted in the expansion slot of the personal computer main body 40. This expansion board 41
The personal computer main body 40, the color monitor 3, and the video player 60 are connected to each other by a cable (not shown). The expansion board 41 has a function of combining the first image created by the personal computer main body 40 and the second image created by the video player 60 and displaying the combined image on the color monitor 3. .

FIG. 2 is a block diagram showing the internal structure of the computer system shown in FIG. The personal computer main body 40 includes a CPU 4, a CPU bus 5, and a first display control unit 1 for controlling image display of characters and graphics. The CPU bus 5 includes an address bus, a data bus, and a control bus.

The expansion board 41 includes a second display control unit 2
A synchronization signal monitor unit 6 and a synchronization signal logic correction unit 7. Each of these units 2, 6 and 7 has a CPU bus 5
It is connected to the CPU 4 via.

The first display control section 1 is provided with a first video RAM (not shown), and the first video including characters and graphics created by the CPU 4 is stored in the first video RAM. The first display control unit 1 is the first
It outputs the component video signal (RGB signal) LSPC representing the first video stored in the video RAM, and outputs the vertical sync signal VSPC and the horizontal sync signal HSPC synchronized with the component video signal LSPC. The component video signal LSPC is provided from the first display control unit 1 to the second display control unit 2.
Further, the synchronization signals VSPC and HSPC are supplied to the color monitor 3
To the sync signal monitor unit 6 and the sync signal logic correction unit 7.

The second display controller 2 has a second video RAM (not shown), and stores the second video image supplied from the video player 60 in the second video RAM.
The second display control unit 2 creates the component video signal LSMON by synthesizing the component video signal LSPC supplied from the first display control unit 1 with the video signal representing the second video, and the video signal LSMON
Is output to the color monitor 3. As the second display control unit 2, for example, Japanese Patent Laid-Open No.
The circuit described in FIG. 4 of the -298176 publication (excluding the CPU 620 in that figure) can be used. The second display control unit 2 has a function of superimposing the second video on a part of the first video, and further superimposing the first video on a part of the superimposed second video. It has various image processing functions such as a multiple superimpose function of imposing and a function of arbitrarily enlarging / reducing an image horizontally and vertically.

The sync signal monitor unit 6 has a function of receiving the two sync signals VSPC and HSPC given from the first display control unit 1 and supplying them to the CPU 4 via the CPU bus 5. When the polarities of the synchronization signals VSPC and HSPC output from the first display control unit 1 are not suitable for the second display control unit 2, the synchronization signal logic correction unit 7 outputs the synchronization signals VSPC and HSPC. It has the function of correcting the polarity.

FIG. 3 is a block diagram showing the internal structure of the synchronization signal monitor unit 6. The sync signal monitor unit 6 includes two 3-state buffers 8a and 8b and an address decoder 9
It has and. The address decoder 9 is the CPU bus 5
The address and the control signal given from the CPU 4 via the CPU 4 are decoded to decode the two 3-state buffers 8a and 8b.
One of them is sequentially set to the low impedance state. First three
The state buffer 8a outputs the vertical synchronizing signal VSPC on a predetermined line of the data bus in the CPU bus 5, and the second 3-state buffer 8b outputs the horizontal synchronizing signal HSPC on the same line. CPU4 is the first
The three-state buffer 8a is set to a low impedance state to take in the vertical synchronizing signal VSPC, and its polarity is determined by the processing described later. After that, the first 3-state buffer 8a is set to the high impedance state, and the second 3-state buffer 8b is set to the low impedance state to take in the horizontal synchronizing signal HSPC and determine its polarity.

FIG. 4 is a block diagram showing the internal structure of the synchronization signal logic correction section 7. The synchronization signal logic correction unit 7 has 2
It is provided with one register 10a, 10b and two EXOR gates 11a, 11b. Two registers 10
1-bit polarity designation data KV and KH indicating whether or not to invert the polarities of the two synchronization signals VSPC and HSPC are stored in a and 10b, respectively. The values of the polarity designation data KV and KH are determined in the polarity determination process (described later) executed by the CPU 4, and the register 10
a and 10b, respectively.

The first EXOR gate 11a outputs the result of the exclusive OR of the polarity designation data KV and the vertical synchronizing signal VSPC as the corrected vertical synchronizing signal VXPC. That is, when KV = 0, the vertical synchronizing signal V
The SPC is directly output as the corrected vertical synchronizing signal VXPC. On the other hand, when KV = 1, the polarity of the vertical synchronization signal VSPC is inverted, and the corrected vertical synchronization signal VPC is inverted.
It is output as XPC.

The polarity of the horizontal synchronizing signal HSPC is also the second E
By the XOR gate 11b, the above-mentioned vertical synchronization signal V
It is corrected similarly to SPC. The sync signals VXPC, HXP whose polarities are corrected by the sync signal logic correction unit 7
C is given to the second display control unit 2 (FIG. 2).

FIG. 5 is a flow chart showing the procedure of the polarity discrimination processing performed by the CPU 4. Further, FIG. 6 is an explanatory diagram showing the content of the polarity determination processing when the vertical synchronization signal VSPC has a negative logic.

In step 30, the CPU 4 monitors that the sync signal to be processed reaches a predetermined first level, and counts in step 31 from the time when the sync signal reaches the first level. Start. In the example of FIG. 6, the vertical synchronization signal VSPC is the processing target, and the predetermined first level is the “0” level. Vertical sync signal VSP
The counting in step 31 is started from the falling edge 20 of C to the 0 level. To be exact, the falling edge 20
Vertical sync signal VS in the first machine cycle thereafter
After the CPU 4 detects that the PC is at "0" level, the counting in step 31 is started.

In step 31, the addition operation of adding 1 to the count value N is repeatedly executed over the period in which the synchronization signal VSPC is at the first level ("0" level), and thereby the first count value N is obtained. . The first count value N indicates the length of the period during which the synchronization signal VSPC is kept at "0" level. The initial value of the first count value N is set to 0.

The sync signal VSPC is at the second level ("1").
Level), the counting calculation in step 31 is ended, and the adding calculation for obtaining the second count value M is repeatedly executed. This addition operation is also the same as the addition operation for the first count value N described above. The second count value M indicates the length of the period in which the synchronization signal VSPC is kept at the "1" level.

The synchronization signal VSPC is at the second level ("1").
When returning from the (level) to the first level (“0” level) again, step 32 ends, and in step 33, the first and second count values N and M are compared. When N <M, the value of the polarity designation data K (KV or KH) for the synchronization signal to be processed is set to 0 in step 34, and when N> M, the polarity designation data K is set in step 35. Is set to 1. The polarity designation data K thus set is written in the register 10a or 10b in the synchronization signal logic correction unit 7 (FIG. 4).

Since N <M in the example of FIG. 6, the value of the polarity designation data KV relating to the vertical synchronizing signal VSPC is set to 0 (step 34 in FIG. 5). Therefore, the first EXOR gate 11a of the synchronization signal logic correction unit 7 outputs the vertical synchronization signal VSPC as it is as the corrected vertical synchronization signal VXPC. That is, as shown in FIG. 6, the vertical synchronization signal VS
When PC is a negative logic, the polarity of the vertical synchronizing signal VSPC is maintained as it is.

In the example of FIG. 7, since N> M, the value of the polarity designation data KV relating to the vertical synchronizing signal VSPC is set to 1 (step 35 in FIG. 5). Therefore, the first EXOR gate 11a of the synchronization signal logic correction unit 7 inverts the vertical synchronization signal VSPC and outputs it as the corrected vertical synchronization signal VXPC. That is, as shown in FIG. 7, the vertical synchronization signal VS
When PC is a positive logic, the polarity of the vertical synchronization signal VSPC is inverted.

When the determination and correction of the polarity of the vertical synchronizing signal VSPC are completed, the first three-state buffer 8a of the synchronizing signal monitor 6 (FIG. 3) is switched to the high impedance state and the second three-state buffer 8b. Is switched to the low impedance state. And CPU4
Performs the polarity determination process with the horizontal synchronization signal HSPC as the processing target.

FIG. 8 shows two synchronization signals VSPC and HSP.
7 is a timing chart showing corrected synchronization signals VXPC and HXPC generated when both C have negative logic. In addition, FIG. 9 shows two synchronization signals VSPC and HSPC.
6 is a timing chart showing corrected synchronization signals VXPC and HXPC generated when both are positive logic. As can be seen from these figures, in this embodiment, the two sync signals VSP output from the first display controller 1 are used.
Regardless of the polarities of C and HSPC, negative logic synchronization signals VXPC and HXPC are always generated, and the second display control unit 2
Given to.

In the first embodiment described above, the case where the polarity of the synchronization signal suitable for the second display control unit 2 is negative logic has been described. However, the synchronization signal suitable for the second display control unit 2 is If the polarity is positive logic, step 3 in FIG.
In step 4, K = 1 is set, and in step 35, K =
You can set it to 0.

In the above-described embodiment, the count values N and M are obtained by repeatedly executing the addition operation in steps 31 and 32 of FIG. 5, but other operations other than addition are used to calculate the count values N and M. The count values N and M indicating the length may be obtained. For example, a predetermined large value is used as the count value N, M
May be set as the initial value of, and the operation of subtracting one by one may be repeatedly executed.

Since the polarity discrimination process shown in FIG. 5 may be executed once when the personal computer is started, it is stored in the ROM (not shown) as a part of the program that is started at the power-on reset of the personal computer. You may leave it. Further, the polarity determination process may be realized by the CPU 4 executing the polarity determination program stored in the RAM (not shown) in response to a command from the operator.

In the above-described first embodiment, as shown in FIG. 2, the sync signal monitor unit 6 and the sync signal logic correction unit 7 are installed on the expansion board 41 on which the second display control unit 2 is arranged. Therefore, without changing the internal configuration of the personal computer main body 40,
It is possible to change the polarities of the synchronization signals VSPC and HSPC output from the second display control unit 2 to those suitable for the second display control unit 2. Further, since the polarities of the two synchronization signals VSPC and HSPC are determined and corrected separately,
Regardless of the combination of polarities of the two sync signals VSPC and HSPC, each can be corrected to a desired polarity. Further, since each sync signal is discriminated by comparing the period of the first level and the period of the second level, the polarity can be surely discriminated regardless of the frequency of each sync signal.

It is to be noted that the CPU is connected via the sync signal monitor unit 6.
The synchronization signals VSPC and HSPC supplied to the CPU 4 may be given to the CPU 4 as data or may be given as an interrupt signal.

B. Second Embodiment: FIG. 10 is a block diagram showing an internal configuration of a computer system as a second embodiment of the present invention. This computer system includes a synchronization signal logic correction unit 70 in place of the synchronization signal logic correction unit 7 of FIG.
2 has the same configuration as that of the computer system shown in FIG. The synchronization signal logic correction unit 70 according to the second embodiment itself has the synchronization signals VSPC and HSPC.
It has a function of discriminating and correcting the polarity of.

FIG. 11 is a block diagram showing the internal structure of the synchronization signal logic correction unit 70. In particular, the vertical synchronization signal VS is shown.
The circuit which corrects PC is shown. The synchronization signal logic correction unit 70 further includes a circuit having the same configuration as that of FIG. 11 as a circuit for correcting the horizontal synchronization signal HSPC.

The vertical synchronizing signal VSPC is input to the clock input terminals of the toggle flip-flop 74 and the two D flip-flops 76 and 78. The T input terminal of the toggle flip-flop 74 is pulled up. The output Q74 of the toggle flip-flop 74 is given to the D input terminal of the first D flip-flop 76, and the output of the first D flip-flop 76 is given to the D input terminal of the second D flip-flop 78. Q76 is given. The first AND gate 80 outputs the output Q74 of the toggle flip-flop 74 and the first D flip-flop 7
The inversion output of 6 / Q76 (“/” indicates inversion) is ANDed and the output is given to the enable terminal of the first counter 90. The second AND gate 82 takes the logical product of the output Q76 of the first D flip-flop 76 and the inverted output / Q78 of the second D flip-flop 78, and outputs that output to the enable terminal of the second counter 92. Is given to. The clock signal CLK generated by the clock generation circuit 100 is applied to the clock input terminals of the first and second counters 90 and 92.

The count value N of the first counter 90 and the second value
The count value M of the counter 92 is compared by the comparator 94. The output Q94 of the comparator 94 becomes L level when N <M, and becomes H level when N> M. The output terminal Q78 of the second D flip-flop 78 is applied to the enable terminal of the comparator 94.

The output Q94 of the comparator 94 is applied to the clock input terminal of the third D flip-flop 96. The D input terminal of the D flip-flop 96 is pulled up. The EXOR gate 98 generates the vertical synchronization signal VXPC with the polarity corrected by taking the exclusive OR of the output Q96 of the D flip-flop 96 and the vertical synchronization signal VSPC.

The address decoder 72 decodes the address and the control signal supplied from the CPU 4 via the CPU bus 5 and generates a reset signal RES for resetting the flip-flop and the counter in the synchronization signal logic correction unit 70. . That is, the reset signal RES is output to the toggle flip-flop 74 and the three D flip-flops 7.
6, 78, 96 and the reset input terminals of the two counters 90, 92, respectively.

FIG. 12 is a timing chart showing the operation of the sync signal logic correction unit 70 when the vertical sync signal VSPC has a negative logic.

First, when the reset signal RES (FIG. 12A) output from the address decoder 72 falls to the L level, the elements 74, 76, and
78, 90, 92 and 96 are reset. Then, in response to the first falling edge (time t1) of the vertical synchronizing signal VSPC after reset, the output Q of the toggle flip-flop 74
74 rises to the H level (FIG. 12 (c)). Since the output Q76 of the first D flip-flop 76 is at L level at this time, the output of the first AND gate 80 becomes H level, and the first counter 90 is enabled. That is, the first counter 90 starts counting up the number of pulses of the clock signal CLK from time t1.

After that, the vertical synchronizing signal VSPC changes to the time t2.
Rises to the H level at, the output Q76 of the first D flip-flop 76 rises to the H level (FIG. 12).
(D)). When this output Q76 becomes H level, the first A
Since the output of the ND gate 80 falls to the L level, counting up of the first counter 90 is stopped. Therefore, the count value N of the first counter 90 is the clock signal CLK in the period from time t1 to time t2 (that is, the period in which the vertical synchronization signal VSPC is kept at the L level).
Shows the number of pulses. At time t2, the output of the second AND gate 82 also becomes H level, and as a result,
The second counter 92 is enabled. That is, the second counter 92 starts the clock signal C from the time t2.
Start counting up the number of LK pulses.

When the vertical synchronizing signal VSPC falls to L level again at time t3, the output Q78 of the second D flip-flop 78 rises to H level (FIG. 12).
(E)). When this output Q78 becomes H level, the second A
Since the output of the ND gate 82 falls to the L level, the counting up of the second counter 92 is stopped. Therefore, the count value M of the second counter 92 is the clock signal CLK in the period from time t2 to time t3 (that is, the period in which the vertical synchronization signal VSPC is kept at the H level).
Shows the number of pulses.

At time t3, when the output Q78 of the second D flip-flop 78 becomes H level, the comparator 94 is enabled, and the comparator 94 has the first counter 90.
And the count value M of the second counter M are compared. In the case of FIG. 12, since N <M, the comparator 94
Output Q94 of L level. In this case, the output Q96 of the third D flip-flop 96 is maintained at the L level, so that the EXOR gate 98 outputs the vertical synchronizing signal V
The SPC is directly output as the corrected vertical synchronizing signal VXPC.

Note that the reset signal RES falls to the L level only when the personal computer is started or when the operator designates the polarity discriminating process. Therefore, in the normal operation state, the output Q96 of the third D flip-flop 96 is kept constant after time t3.

FIG. 13 is a timing chart showing the operation of the sync signal logic correction unit 70 when the vertical sync signal VSPC is positive logic. Also in FIG. 13, as in the case of FIG. 12, the first counter in the period from the first falling edge (time t4) to the next rising edge (time t5) of the vertical synchronizing signal VSPC after the reset signal RES is applied. 90 counts up to obtain the first count value N, and second counter 92 counts up during the period from time t5 to the next falling edge of vertical synchronization signal VSPC (time t6). The second count value M is determined. When the comparator 94 is enabled at time t6, its output Q94 rises to H level (FIG. 13 (g)), and the third D flip-flop 96
The output Q96 of the IC also rises to the H level accordingly (FIG. 13).
(H)). As a result, the EXOR gate 98 inverts the vertical synchronization signal VSPC and corrects the vertical synchronization signal VXPC.
Output as. That is, the corrected vertical synchronization signal VX
PC has a negative logic.

As described above, the sync signal logic correction unit 70 shown in FIG. 11 outputs the negative logic vertical sync signal VXPC regardless of the polarity of the vertical sync signal VSPC. This also applies to the horizontal synchronizing signal HSPC.

The synchronization signal logic correction unit 7 shown in FIG.
The configuration of 0 can be modified in various ways as needed. For example, when the polarity of the synchronization signal suitable for the second display control unit 2 (FIG. 10) is positive logic, the synchronization signal VXPC in FIG. 11 may be inverted and supplied to the second display control unit 2. Good.

Further, down counters may be used as the counters 90 and 92 in FIG. 11, and a predetermined large value may be set as a preset value.

Further, one up / down counter may be used instead of the two counters 90 and 92. Figure 1
4 replaces the two up counters 90 and 92 of the synchronization signal logic correction unit 70 shown in FIG. 11 with one up / down counter 93, and also has a two-input AND gate 80,
It is a block diagram which shows the circuit which replaced 82 with 3 input AND gates 84 and 86. First 3-input AND gate 8
4 has an output Q74 of the toggle flip-flop 74,
An inverted output / Q76 of the first D flip-flop 76,
The clock signal CLK is input. On the other hand, the second 3-input AND gate 86 has an output Q76 of the first D flip-flop 76 and a second D flip-flop 78.
The inverted output / Q78 and the clock signal CLK are input. The output of the first 3-input AND gate 84 is supplied to the up-count input terminal of the up-down counter 93, and the output of the second 3-input AND gate 86 is supplied to the down-count input terminal. The output terminal Q74 of the toggle flip-flop 74 is applied to the enable terminal of the up / down counter 93.

For example, when the negative logic vertical synchronizing signal VSPC shown in FIG. 12B is input, the up / down counter 93 counts up the number of pulses of the clock signal CLK from the time t1 to the time t2. During the period from time t2 to time t3, the number of pulses of the clock signal CLK is counted down. Therefore, the count value output by the up / down counter 93 is (N−M). The comparator 94 compares this count value (NM) with "0". A predetermined preset value Z may be set in the up / down counter 93 and the preset value Z may be compared with the count value (Z + N−M).

The present invention can be applied not only to a computer system but also to a device for displaying an image in general, and for example, a still image display device, a moving image display device, a video printer, a video communication device, an image signal. It can be applied to a converter or the like.

The present invention is not limited to the above-mentioned embodiments, but can be carried out in various modes without departing from the scope of the invention.

[0064]

As described above, according to the invention described in claim 1, the synchronization signal is generated in accordance with the comparison between the length of the period of the first level and the length of the period of the second level of the synchronization signal. Since the polarity of the sync signal is corrected, the polarity of the sync signal can be correctly determined regardless of the frequency of the sync signal, and the polarity of the sync signal can be corrected.

According to the invention described in claim 2, there is an effect that it is not necessary to provide a new hardware circuit as the period comparison means.

According to the invention described in claim 5, there is an effect that the lengths of the first and second periods can be indicated by the count values of the first and second counters, respectively.

According to the invention described in claim 7, there is an effect that the polarity can be discriminated by measuring the difference between the length of the first period and the length of the second period.

According to the invention described in claim 8, there is an effect that the difference in the length of the period can be measured by one up / down counter.

According to the invention described in claim 9, there is an effect that a sync signal suitable for the display control means can be given no matter what polarity the sync signal is given to the sync signal polarity correcting device. .

According to the invention described in claim 10, the first
There is an effect that an image can be displayed on the display means by the second display control means regardless of the polarity of the sync signal output from the display control means.

[Brief description of drawings]

FIG. 1 is a perspective view showing a computer system as a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a computer system according to the first embodiment.

FIG. 3 is a block diagram showing an internal configuration of a synchronization signal monitor unit 6.

FIG. 4 is a block diagram showing an internal configuration of a synchronization signal logic correction unit 7.

FIG. 5 is a flowchart showing a procedure of polarity determination processing.

FIG. 6 is an explanatory diagram showing the contents of polarity determination when the vertical synchronization signal VSPC has a negative logic.

FIG. 7 is an explanatory diagram showing the contents of polarity determination when the vertical synchronization signal VSPC has a positive logic.

FIG. 8 is a timing chart showing a polarity correction operation when both two synchronization signals are negative logic.

FIG. 9 is a timing chart showing a polarity correction operation when both of the two synchronization signals are positive logic.

FIG. 10 is a block diagram showing an internal configuration of a computer system according to a second embodiment.

11 is a block diagram showing the internal configuration of a synchronization signal logic correction unit 70. FIG.

FIG. 12 is a timing chart showing the operation of the sync signal logic correction unit 70 when the vertical sync signal VSPC has a negative logic.

FIG. 13 is a timing chart showing the operation of the sync signal logic correction unit 70 when the vertical sync signal VSPC is positive logic.

FIG. 14 is a block diagram showing an internal configuration of a modified example of the synchronization signal logic correction unit.

FIG. 15 is a block diagram showing the configuration of a conventional personal computer system equipped with a second display control unit.

[Explanation of symbols]

 1 ... 1st display control part 2 ... 2nd display control part 3 ... Color monitor 4 ... CPU 5 ... CPU bus 6 ... Sync signal monitor part 7 ... Sync signal logic correction part 8a, 8b ... 3 state buffer 9 ... Address Decoders 10a, 10b ... Registers 11a, 11b ... EXOR gates 40 ... Personal computer main body 41 ... Expansion board 50 ... Keyboard 52 ... Mouse 60 ... Video player 70 ... Sync signal logic correction unit 72 ... Address decoder 74 ... Toggle flip-flops 76, 78 ... D flip-flop 80, 82 ... AND gate 90, 92 ... Counter 94 ... Comparator 96 ... D flip-flop 98 ... EXOR gate 100 ... Clock generation circuit CLK ... Clock signal HSPC ... Horizontal sync signal HXPC ... Horizontal sync after polarity correction Signal KH: Horizontal sync signal pole Specified data KV ... Vertical sync signal polarity designation data LSMON ... Component video signal LSPC ... Component video signal M ... Count value during period when sync signal is at H level N ... Count value during sync signal at L level RES ... Reset signal VSPC ... Vertical sync signal VXPC ... Vertical sync signal after polarity correction

Claims (10)

[Claims] 1. A synchronization signal polarity correction device for determining the polarity of a synchronization signal and correcting the synchronization signal to a desired polarity, wherein the synchronization signal has a length of a first period in which the synchronization signal is at a first level. , Measuring the length of a second period during which the synchronization signal is at a second level, and measuring the length of the first period and the second period.
And a polarity correction unit that corrects the polarity of the synchronization signal to a desired polarity according to the comparison result by the period comparison unit. 2. The synchronization signal polarity correction device according to claim 1, wherein the period comparison means measures the lengths of the first and second periods, respectively, to obtain the first and second periods. And a signal transmitting means for giving the polarity instructing signal from the digital computer to the polarity correcting means, and a digital computer having a program for outputting a polarity instructing signal representing the comparison result. Polarity correction device. 3. The synchronization signal polarity correction device according to claim 2, wherein the measurement of the lengths of the first and second periods is performed by repeating an addition operation for adding a predetermined value. Sync signal polarity correction device. 4. The synchronization signal polarity correction device according to claim 1, wherein the period comparison unit measures the length of the first period and the length of the second period. A synchronization signal polarity correction device comprising: a second measuring unit that measures the length; and a comparing unit that compares the length of the first period with the length of the second period. 5. The synchronization signal polarity correction device according to claim 4, wherein the first measuring unit includes a first counter that counts the number of pulses of a predetermined clock signal in the first period, The said 2nd measuring means is a synchronizing signal polarity correction apparatus containing the 2nd counter which counts the pulse number of the said predetermined clock signal in the said 2nd period. 6. The synchronization signal polarity correction device according to claim 5, wherein the first and second counters are up counters. 7. The synchronization signal polarity correction device according to claim 1, wherein the period comparison unit measures a difference between the length of the first period and the length of the second period, Comparing means for comparing the difference measured by the measuring means with a predetermined reference value. 8. The synchronization signal polarity correction device according to claim 7, wherein the measuring unit counts up the number of pulses of a predetermined clock signal in the first period and the measuring unit in the second period. A synchronization signal polarity correction device including an up-down counter that counts down the number of pulses of a predetermined clock signal. 9. The sync signal polarity correction device according to claim 1, further comprising display control means for outputting a video signal synchronized with the sync signal whose polarity is corrected by the polarity correction means. apparatus. 10. A computer system comprising: display means for displaying an image; first display control means for generating a sync signal applied to the display means; determining the polarity of the sync signal; Sync signal polarity correcting means for correcting the signal to a desired polarity, and second display control means for outputting to the display means a video signal in synchronization with the sync signal whose polarity is corrected by the polarity correcting means, The sync signal polarity correcting means measures a length of a first period in which the sync signal is at a first level and a length of a second period in which the sync signal is at a second level, and Period comparison means for comparing the length of the period and the length of the second period, and polarity correction means for correcting the polarity of the synchronization signal to a desired polarity according to the comparison result by the period comparison means. Obtain computer system.