JPH08339174A - Polarity discrimination circuit for synchronizing signal - Google Patents

Abstract

PURPOSE: To discriminate polarity of a vertical synchronizing signal without using capacitor. CONSTITUTION: A frequency divider circuit 1 frequency-divides a horizontal synchronizing signal H1 and outputs frequency-divided pulse H2. A counter 2 detects and counts up the rising of the frequency-divided signal H2 inputted to a clock input terminal (CK) when a vertical synchronizing signal V1 inputted to an enable terminal (ENA) is at a level 'H', and outputs the counted value (A3-A0). A counter 3 receives to the enable terminal (ENB) a vertical synchronizing signal V3 of which the polarity is inverted by an inverter 6, and detects and counts up the frequency-divided signal 82 and outputs the counted value (B3-BO) when the vertical synchronizing signal V3 is at the level 'H'. A Comparator 4 performs a comparison between the counted value of the counter 2 and that of the counter 3 and outputs a signal Sc. A latch circuit 5 latches the signal Sc from the comparator 4 and outputs a polarity indicating signal Sp.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal polarity discriminating circuit applied to a multi-frequency display device, and more particularly to a sync signal polarity discriminating circuit for discriminating the polarity of a vertical sync signal.

[0002]

2. Description of the Related Art A multi-frequency display device capable of scanning at different frequencies has a circuit for discriminating the polarities of an input vertical synchronizing signal and horizontal synchronizing signal. Even if there is, I am trying to cope.

In a conventional sync signal polarity discriminating circuit, as described in Japanese Patent Application Laid-Open No. 61-255165, a sync signal is integrated by an integrator composed of a resistor and a capacitor, and is preset. The polarity is determined by comparing it with the reference voltage value.

Further, as described in Japanese Patent Laid-Open No. 5-181445, a circuit for discriminating the polarity of a horizontal synchronizing signal without using a capacitor by paying attention to the relationship between the vertical synchronizing signal and the horizontal synchronizing signal. is there.

[0005]

However, in the sync signal polarity discriminating circuit described in Japanese Patent Laid-Open No. 61-255165, a capacitor is used, so that the IC of the circuit is used.
Is difficult to convert. Further, the circuit described in Japanese Patent Laid-Open No. 5-181445 cannot determine the polarity of the vertical synchronizing signal.

It is an object of the present invention to provide a sync signal polarity discriminating circuit capable of discriminating the polarity of a vertical sync signal without using a capacitor.

[0007]

A sync signal polarity discriminating circuit according to the present invention is a sync signal polarity discriminating circuit which receives a horizontal sync signal and a vertical sync signal to discriminate the polarity of a vertical sync signal. A first pulse counting means for counting the number of pulses of the horizontal synchronizing signal in each period of the vertical synchronizing signal in a period in which the level becomes "H", and a polarity inverting means for inverting the polarity of the vertical synchronizing signal. Second pulse counting means for counting the number of pulses of the horizontal synchronizing signal in the period in which the polarity-reversed vertical synchronizing signal output by the polarity inverting means is at the “H” level for each cycle of the vertical synchronizing signal. And the count value of the first pulse counting means and the count value of the second pulse counting means are compared, and an "H" level or "L" level signal is output based on the comparison result. It comprises a comparison unit that, a latch circuit for outputting a determination signal indicating the polarity holds the signal output from the comparison means.

In the above structure, the horizontal synchronizing signal is frequency-divided to output a frequency-divided output pulse, and the first and second pulse counting means count the frequency-divided output pulse, respectively. It may be configured as follows.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a frequency dividing circuit 1 for dividing a horizontal synchronizing signal H1 and a rising edge of an output signal H2 of the frequency dividing circuit 1 are detected and counted up. Counters 2 and 3, count value of counter 2 (A3 to A0) and count value of counter 3 (B3 to B0
0)), a latch circuit 5 that latches the output signal Sc of the comparator 4 and outputs it as a signal Sp indicating the polarity, and an inverter 6 that inverts the polarity of the vertical synchronization signal V1.

If the vertical synchronizing signal has a positive polarity, the vertical synchronizing pulse portion becomes "H" level.
The “H” level period is shorter than the “L” level period. On the contrary, if the vertical synchronizing signal has a negative polarity, the “H” level period is longer than the “L” level period. The present invention pays attention to this point and determines the polarity of the vertical synchronizing signal.

Next, the operation will be described.

FIG. 2 is a timing chart showing the operation when the negative horizontal sync signal H1 and the positive vertical sync signal V1 are input.

The horizontal synchronizing signal H1 is frequency-divided by the frequency dividing circuit 1 into 1/2, and is input to the clock input terminals (CK) of the counters 2 and 3 as frequency-divided output pulses H2. Although the negative horizontal sync signal is used in the present embodiment, the divided output pulse H is generated even for the positive horizontal sync signal.
The rising position of 2 is only slightly shifted by the pulse width,
It may be positive or negative. Further, the frequency dividing ratio in the frequency dividing circuit 1 may be other than 1/2.

The vertical synchronizing signal V1 is input to the enable end (ENA) of the counter 2. The vertical synchronizing signal V3 whose polarity is inverted by the inverter 6 is input to the enable end (ENB) of the counter 3. Counters 2 and 3 are
When the enable ends (ENA, ENB) are at “H” level, the rising edge of the signal H2 at the clock input end (CK) is detected and counted up, and the count values (A3 to A0, B3) are detected.
~ B0) is output. Further, the counters 2 and 3 clear the count value when the reset signal V2 input to the reset end (RST) is at "H" level.

That is, as shown in FIG. 2, the counter 2 detects the rising edge of the divided output pulse H2 and counts when the positive vertical synchronizing signal V1 is at the "H" level. On the other hand, the counter 3 detects the rising edge of the divided output pulse H2 and counts when the vertical synchronizing signal V1 is at the "L" level. Since the vertical synchronizing signal V1 is counted in units of one cycle, a signal indicating the cycle of the vertical synchronizing signal V1 generated by the latch circuit 5 is used as the reset signal V2.

The count value (A3 to A0) of the counter 2 and the count value (B3 to B0) of the counter 3 are compared by the comparator 4. The comparator 4 outputs the “L” level output signal Sc when the count value (A3 to A0) is larger than the count value (B3 to B0), and the count value (A3 to A0) is the count value (B3 to B0). When it is smaller than the value of (), the output signal Sc of "H" level is output. That is, as shown in FIG. 2, the count value (A3
~ A0) is "1" and the count value (B3 to B0) is "2", the output signal Sc becomes "H" level, indicating that the polarity of the vertical synchronizing signal V1 is positive. .

The output signal Sc of the comparator 4 is latched by the latch circuit 5 at the rising edge of the vertical synchronizing signal V1 and output as the signal Sp indicating the polarity of the vertical synchronizing signal. As shown in FIG. 2, if the vertical synchronizing signal has a positive polarity, the signal Sp indicating the polarity becomes the “H” level.

FIG. 3 shows a case where the negative vertical synchronizing signal V1 is input.

In this case, the count value (A3 to A0) input to the comparator 4 is always the count value (B3 to B0).
Therefore, the output signal Sc of “L” level is output. Therefore, since the output signal Sc of “L” level is latched by the latch circuit 5, the signal Sp indicating the polarity of the vertical synchronizing signal becomes “L” level,
It indicates that the vertical synchronizing signal has a negative polarity.

In the case of an actual display device, the resolution is generally 640 × 400 dots to 1280 × 1024 dots. Therefore, if the frequency division ratio of the frequency dividing circuit 1 is set to 1/128, for example, 1280 × The maximum count value at a resolution of 1024 dots is 1024/128 =
Therefore, a counter having a 4-bit output can be used.

[0022]

As described above, according to the present invention, the number of pulses of the horizontal synchronizing signal in the period in which the vertical synchronizing signal is at the "H" level is counted in units of one cycle of the vertical synchronizing signal. The polarity of the vertical sync signal is determined without using a capacitor by counting the number of pulses of the horizontal sync signal during the period when the polarity-reversed vertical sync signal is at “H” level and comparing these count values. Therefore, the circuit can be easily integrated into an IC.

Further, by dividing the horizontal synchronizing signal to generate a divided output pulse and counting the divided output pulse, the circuit configuration of the counter can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation when a negative horizontal sync signal and a positive vertical sync signal are input.

FIG. 3 is a timing chart showing an operation when a negative horizontal sync signal H1 and a negative vertical sync signal V1 are input.

[Explanation of symbols]

 1 Divider circuit 2, 3 Counter 4 Comparator 5 Latch circuit 6 Inverter H1 Horizontal sync signal H2 Divided output pulse V1 Vertical sync signal V2 Reset signal V3 Polarity inverted vertical sync signal Sp Signal indicating the polarity of the vertical sync signal

Claims (2)

[Claims] 1. A sync signal polarity discriminating circuit for discriminating the polarity of a vertical sync signal by receiving a horizontal sync signal and a vertical sync signal, wherein the horizontal sync signal of the horizontal sync signal is in a period in which the vertical sync signal is at "H" level. First pulse counting means for counting the number of pulses for each cycle of the vertical synchronizing signal, polarity inverting means for inverting the polarity of the vertical synchronizing signal, and polarity inverted vertical synchronizing signal output by the polarity inverting means. A second number for counting the number of pulses of the horizontal synchronizing signal in each period of the vertical synchronizing signal in the period in which the level becomes "H" level.
Pulse counting means, and the count value of the first pulse counting means and the count value of the second pulse counting means are compared in magnitude, and based on the comparison result, "H" level or "L".
A polarity determination circuit for a sync signal, comprising: a comparison unit that outputs a level signal; and a latch circuit that holds the signal output by this comparison unit and outputs it as a determination signal indicating the polarity. 2. A frequency dividing means for dividing the horizontal synchronizing signal to output a divided output pulse, wherein the first and second pulse counting means respectively count the divided output pulse. The polarity determination circuit for a sync signal according to claim 1,