JP3335621B2 - Image processing device and its interrupt control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing device and an interrupt control device thereof. More specifically, the present invention detects an horizontal position and / or a vertical position on a screen of a raster scan monitor in an image processing apparatus such as a video game machine and provides an interrupt signal to a microprocessor (CPU). Control device.

(Prior art)

An example of this type of video game machine is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-118184 published on July 7, 1984 (U.S. Pat. No. 4,824,106 issued on April 25, 1989). Corresponding).

In such a video game machine, if the parameters of the video processor are changed during the scan operation of the raster scan monitor, the image on the monitor screen is disturbed. Therefore, it is necessary to change the parameters of the video processor when blanking the raster scan monitor. Was. Conventionally, in order to obtain the blanking timing, a software timer or an interrupt for each H blank is mainly used.
We did not interrupt at specific positions on the monitor screen.

[Problems to be solved by the invention]

On the other hand, the present inventors have developed a still image processing apparatus capable of vertically scrolling an image in a part of a horizontal width on a screen by changing an offset value during a horizontal blanking period of a raster scan monitor, for example, It was proposed in Japanese Patent Application No. 2-225672 (filed on August 27, 1990).

To achieve such scrolling, it is necessary to calculate the offset value to be changed each time. In this case, the calculation of the offset value is performed by interrupting the CPU. Further, if the calculation of the offset value is performed only during the horizontal blanking period, if the time required for the calculation is long, all the calculations cannot be performed during the horizontal blanking period, and during the display period of the raster scan monitor ( (During scanning), the calculation may take place, making it impossible to change the parameters of the essential video processor during blanking. To eliminate such inconveniences,
It is necessary to interrupt during the display period of the raster scan monitor.

However, in the above-described video game machine, when an attempt is made to interrupt at a specific position on the screen of the raster scan monitor, it is necessary to detect the timing.

By configuring a loop to detect horizontal blanking by a program and counting the number of loops from vertical blanking, the timing of horizontal blanking can be known, but during that period, the CPU is Not only is it impossible, but the program needs to know the position on the screen by calculating the number of loops and the clock cycle of the instruction of the loop, so that it took a very long time to obtain the position data.

Further, in this method, when outputting position data from the counter, position data can be obtained only at every clock cycle of the instruction. Therefore, for example, in order to detect the position in units of one dot on the screen, a very high speed is required. Must use CPU.

SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide an image processing apparatus and an interrupt processing apparatus capable of easily interrupting a desired position on a screen of a raster scan monitor.

Another object of the present invention is to use a high-speed CPU without using a high-speed CPU.
It is an object of the present invention to provide an image processing apparatus and an interrupt processing apparatus capable of performing an interrupt at a desired position on a screen of a raster scan monitor.

Means for Solving the Problems A first invention is an interrupt control device in an image processing device for displaying an image on a raster scan monitor under the control of a CPU, wherein the horizontal position on the screen of the raster scan monitor is Horizontal counter means for counting the vertical position, vertical counter means for counting the vertical position on the screen of the raster scan monitor,
First storage means for temporarily storing horizontal position data and vertical position data on the screen of the raster scan monitor to be interrupted by the CPU, and interrupt condition data given by the CPU;
First comparing means for comparing the count value in the horizontal counter means with the horizontal position data in the first storage means;
Second comparing means for comparing the count value in the vertical counter means with the vertical position data in the first storage means,
And an interrupt signal generating means for generating an interrupt signal when an output of at least one of the first comparing means and the second comparing means satisfies a condition specified by the interrupt condition data. .

A second invention is an interrupt control device in an image processing device for displaying an image on a raster scan monitor under the control of a CPU, wherein the horizontal counter means counts a horizontal position on a screen of the raster scan monitor; Vertical counter means for counting the vertical position on the screen of the monitor,
First storage means for temporarily storing horizontal position data and vertical position data on a screen of a raster scan monitor to be interrupted by a CPU, a count value in a horizontal counter means and a first value;
First comparing means for comparing the horizontal position data in the storage means with the count value in the vertical counter means and the first value.
Second comparing means for comparing the vertical position data with the vertical position data in the storage means, an interrupt signal generating means for generating an interrupt signal in response to an output from the first comparing means and the second comparing means,
Second storage means for holding a count value in the horizontal counter means and a count value in the vertical count means in response to a count value holding signal output from the CPU, and respective counts held in the second storage means An interrupt control device including output means for giving a value to a CPU.

[Action]

In the first invention, the horizontal position and / or the vertical position on the screen of the raster scan monitor that interrupts the CPU are set by the program. This program is read by the CPU, and the interrupt horizontal position and / or the vertical position and the interrupt condition data are temporarily stored in the storage means. The first comparing means compares the count value of the horizontal counter means with the horizontal position data read from the storage means, and the second comparing means compares the count value of the vertical counter means with the vertical position data.
The interrupt signal generating means provides an interrupt signal to the CPU when the output from the first comparing means and / or the second comparing means satisfies the condition specified by the above-described interrupt condition data.

Also in the second invention, the horizontal position and / or the vertical position on the screen of the raster scan monitor that interrupts the CPU are set by the program. This program
The horizontal position and / or the vertical position of the interrupt are read by the CPU and temporarily stored in the storage means. Then, according to the outputs from the first comparing means and the second comparing means, the interrupt signal generating means gives the CPU an interrupt signal.
Further, the second storage means holds the count value of the horizontal counter means and the count value of the vertical count means in response to the count value holding signal output from the CPU, and the output means stores the count value in the second storage means. The stored count values are given to the CPU.

According to the present invention, it is possible to easily interrupt the CPU at a desired position on the screen of the raster scan monitor simply by setting the interrupt position data in the program. For this reason, for example, when a predetermined operation is performed by the interrupt, it is possible to calculate the timing required for the operation result and the time required for the operation and to interrupt at an appropriate position. The processing does not protrude during the display period of the raster scan monitor.

More specifically, according to the present invention, the CPU can read the count values (= current scanning position) of the horizontal counter means and the vertical counter means from the HV timer circuit,
Therefore, if the CPU obtains the count values of the horizontal counter means and the vertical counter means at the start and end of a certain data processing, the CPU calculates the time required for the data processing as a value corresponding to the count value of the horizontal and vertical counter means. You can know as. Therefore, for example, (i) the process of calculating how long before the vertical blanking period (or the horizontal blanking period) data processing should be started, and setting the vertical position / vertical position to be interrupted based on the calculated (ii) ) Vertical blanking period (horizontal blanking period)
Comparing the time required for data processing with the time required for data processing to determine whether the processing is completed within the vertical blanking period (or within the horizontal blanking period), etc. Is not required, and calculation / comparison can be performed with the values as they are. On the other hand, if the time required for data processing is determined as a value that is not related to the count values of the horizontal and vertical counter means, a process of correcting the value to a value corresponding to the count value is required. Therefore, the load on the CPU increases.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

The image processing apparatus 10 shown in FIG.
The PU 12 is connected to a PPU (Picture Processing Unit) by an address bus, a data bus, and a control bus. CPU 12 is also coupled to program storage 16 by an address bus and a data bus. CP
U12 is composed of, for example, a 16-bit microprocessor, and controls the entire image processing apparatus 10. PPU14
Is controlled by a PPU address bus, a PPU data bus and a PPU control bus.
ss Memory). PPU14
As will be described later, according to an instruction from the CPU 12, the graphic data is read from the image memory 18 and converted into a video signal, and the video signal is supplied to the raster scan monitor 20. The program storage device 16 is composed of, for example, a detachable memory cartridge, and stores in advance horizontal position data and / or vertical position data on the screen of the raster scan monitor 20 to be interrupted, program data and character data necessary for the game, and the like. are doing. Note that the character data in the program storage device 16 is transferred to the image memory 18 as needed.

The address bus of the CPU 12 is connected to an address decoder 22, which decodes an address output to the CPU address bus and sends an enable signal or a select signal / CS to the PPU 14 and the program storage device 16.
(However, “/” means inversion).

A reference clock of, for example, 21.47727 MHz from reference oscillator 24 is applied to timing signal generation circuit 26. In the timing signal generation circuit 26, a timing signal / 10M is obtained by dividing the reference clock by 1/2, and a timing signal / 5M is obtained by further dividing the frequency by 1/2.
These timing signals / 10M and / 5M are given as control clocks of the above-described PPU 14. Note that the timing signal / 5
M corresponds to one dot (pixel) on the screen of the raster scan monitor 20, and this timing signal / 5M is also given to the HV counter circuit 28. Timing signal generation circuit 26
Also create a system clock SYSTEM CK and C
PU12, address decoder 22 and HV counter circuit 28.

The HV counter circuit 28 counts a horizontal position (H position) and a vertical position (V position) on the screen of the raster scan monitor 20, based on a timing signal / 5M from the timing signal generation circuit 26, as described later. At the same time, an interrupt signal is given to the CPU 12 at the timing set in the program storage device 16.

Specifically, the HV counter circuit 28 is configured as shown in FIG. That is, the HV counter circuit 28 is an H counter
Include 30 and V counter 32, the reset input / R of the H counter 30 and V counter 32 is given a horizontal blanking signal H _B and the vertical blanking signal V _B from PPU14. Timing signal / 5
M is given, it is given a horizontal blanking signal H _B to the clock input of the V counter 32. H counter 30 counts the horizontal position on the screen of the raster scan monitor 20 by counting the timing signal / SM, V counter 32 counts the vertical position by counting the horizontal blanking signal H _B. The respective count values of the H counter 30 and the V counter 32 are provided to a comparison circuit 34.

On the other hand, the data bus of CPU 12 is coupled to data latch 36. The CPU 12 outputs the interrupt horizontal position data H-Timer read from the program storage device 16 through the data bus.
And the interrupt vertical position data V-Timer is loaded into the latch 36. The interrupt position data H-Timer and V-Timer
Is provided as the other input of the comparison circuit 34. Comparison circuit
34 outputs a horizontal (H) coincidence signal Hc when data Hp and data H-Timer match, and outputs data Vp and data V-Ti
mer and outputs the vertical (V) matching signal V _C if it matches.

The HV counter circuit 28 further includes a decoder 38, which is connected to an address bus of the CPU 12, receives address data, and receives a system clock SYSTEM.
Receives CK and read / write signal R / W. The decoder 38
It decodes address data given from the CPU address bus and outputs latch signals L1, L2, L3, L4, L5 and L6.Latch signals L1-L5 are given to a latch circuit 36, and latch signal L6 is an interrupt signal. It is provided to the generation circuit 40. When the latch signal L1 is output from the decoder 38 in accordance with the address data of the CPU address bus, the latch 36 latches the upper one bit of the interrupt position decoder H-Timer, and latches the latch signal L1.
When 2 is output, the lower 8 bits of the interrupt position data H-Timer
When the latch signal L3 is applied, the upper 1 bit of the interrupt position data V-Timer is latched, and when the latch signal L4 is applied, the lower 8 bits of the interrupt position data V-Timer are latched. . Then, when the latch signal L5 is given, the latch 36 latches the interrupt condition data.
Therefore, the horizontal interrupt position data H-Timer is latched by the latch signals L1 and L2, and the latch signals L3 and L4
Latches the vertical interrupt position data V-Timer in response to
Note that the latch signal L6 from the decoder 38 is supplied as a clock of an RS-FF80 (FIG. 6) of the interrupt signal generation circuit 40, which will be described later.

The interrupt signal generation circuit 40 outputs a signal D7, and this signal D7
Is supplied to the data bus of the CPU 12 through the gate 42.

FIG. 3 is a block diagram showing the PPU 14 shown in FIG. 1 in detail. The PPU 14 includes a CPU interface 44.
U interface 44 receives address data from the address bus of CPU 12. The CPU interface 44 is further supplied with an enable signal / CS, a timing signal / 10M, a system clock SYSTEMCK, and a read / write signal R / W. The address bus of the CPU 12 is further connected to a decoder 46 to which a system SYSTEM CK and a read / write signal R / W are supplied. CPU interface
44 supplies an enable signal to the moving image data generating circuit 48 and the still image generating circuit 50 according to the address data of the CPU address bus.

The PPU further has a 4-input O receiving the output of the decoder.
An output of the OR gate 52 is provided to a latch signal generation circuit 54. The output of latch signal generating circuit 54 is applied to latch 56. Each output of the decoder 46 is provided as a gate signal of a gate 58.

The PPU 14 further includes an H counter 60 and a V counter 62
The H counter 60 receives the timing signal / 5M from the timing signal generation circuit 26 as a clock in the same manner as the H counter 30 of the HV counter circuit 28, and
2, like the V counter 32 of the HV counter circuit 28 receives the horizontal blanking signal H _B to the clock input. The reset input of each of the H counter 60 and the V counter 62
The / R, the horizontal blanking signal H _B and V _B are respectively provided. The horizontal position data Hp from the H counter 60 and the vertical position data Vp from the V counter 62 are supplied to the above-mentioned latch 56 and also to the H blank signal generation circuit 64 and the V blank signal generation circuit 66, respectively. Then, the horizontal position data Hp and the vertical position data Vp are further provided to the above-described moving image data generation circuit 48 and still image data generation circuit 50, respectively.

Although not shown, the moving image generating circuit 48 includes an OAM (Object Attrib
The OAM stores object data consisting of a total of 34 bits shown in FIG. The object data includes 9-bit object designation data (name data), 8-bit V position data, 9-bit H position data, 3-bit color data, 2-bit priority data, 2-bit flip data, and 1-bit object. Includes size selection data. Based on the name data and the position data included in the object data read from the OAM and the V position data Vp from the V counter 62,
The character data area in the image memory 18 is addressed. Therefore, the graphic data (dot data) of the object character is output from the image memory 18.
Is output.

The still image data generating circuit 50 reads pattern data (character code) of a still image from the program memory of the program storage device 16 in accordance with the program data given from the CPU 12 (FIG. 1) through the CPU interface 44, and Based on the data, graphic data of a still image is read from the image memory 18 and is output as still image data. That is, the still image pattern data shown in FIG. 5 is stored in the pattern data area of the image memory 18 for each character. Still image character data indicating one character includes 10-bit name data (character code), 3-bit attribute data, 1-bit priority data, and 2-bit flip data. In the still image data generation circuit 50, an H counter
Based on the H position data Hp from 60 and the V position data Vp from the V counter 62, the raster scan monitor 20 (first
The address value of the still image pattern area of the image memory 18 corresponding to each line position on the screen of FIG. 7 is calculated, and a still image character represented by name data is constituted from the image memory 18 specified by the address value. Output graphic (dot data).

In this way, the dot data of the object character and the dot data of the still image character output from the moving image data generation circuit 48 and the still image generation circuit 50 are
This is given to the synthesizing circuit 68, and the synthesizing circuit 68 determines the priority as required and outputs the synthesized image data. The composite image data is supplied to a video signal conversion circuit, and the converted video signal is output to the above-described raster scan monitor 20.
It is given to.

Next, the interrupt signal generation circuit 40 shown in FIG. 2 will be described with reference to FIG. This interrupt signal generation circuit 40 includes a data selector 70, and the data selector 70 has a latch
Interrupt condition data from 36 (FIG. 2), that is, an H interrupt permission signal and / or a V interrupt permission signal is applied. The data input of the data selector 70 receives “1”, the H match signal Hc, the V match signal Vc, and the output of the OR gate 72. This OR
Gate 72 receives H match signal Hc and V match signal Vc.
The data selector 70 receives the H interrupt enable signal and / or V
One of the four data inputs is selected according to the interrupt enable signal “1” or “0”.

The output of the data selector 70 is supplied to the data input of the D-FF 74, and the clock of the D-FF 74 is a timing signal / 5M from the timing signal generation circuit 26 (FIG. 1). Then, the output Q of the D-FF74 is the D of the D-FF76.
The signal is applied to one input of the OR gate 78 as well as to the input. The timing signal / 5M is applied to the clock of the D-FF 76, and the output / Q of the D-FF 76 is applied to the other input of the OR gate 78. The output of the OR gate 78 is provided as a set input of the RS-FF80, and the output of the OR gate 82 receiving the H interrupt enable signal and the V interrupt enable signal is provided as a reset input of the RS-FF80. As described above, the latch signal L6 from the decoder 38 (FIG. 2) is supplied as the clock of the RS-FF80. The output Q of RS-FF80 is a tri-state gate 84 controlled by a latch signal L6.
And the output / Q is given to the CPU 12 (FIG. 1) as an interrupt signal / IRQ.

In the comparison circuit 34 (FIG. 2), the horizontal interrupt position data H-Timer and / or the vertical interrupt position data V-Timer from the latch 36 and the count value in the H counter 30, that is, the horizontal position data Hp and / or V count When the vertical position data Vp at 32 matches, an H match signal
Hc and / or V match signal Vc are output. When H match signal Hc and / or V match signal Vc are applied and H interrupt enable signal and / or V interrupt enable signal are applied from latch 36 (FIG. 2), a signal is output from data selector 70. You. That is, in response to the H match signal Hc when the H interrupt permission signal is given as “1”, and in response to the V match signal Vc when the V interrupt permission signal is given as “1”, Alternatively, when the H interrupt enable signal and the V interrupt enable signal are both given as “1”, in response to the input of both the H match signal Hc and the V match signal Vc,
A data input is given from the data selector 70 to the D-FF 74, respectively. This data input is latched at D-FF74 in response to the timing signal / 5M, and its output is latched at D-FF76. Therefore, the input from the OR gate 78 becomes “1”, the output / Q of the RS-FF 80, that is, the interrupt signal / IRQ becomes “0”, and the CPU 12 is interrupted.

When the CPU 12 (FIG. 1) reads a specific address, in the PPU 14, an enable signal is supplied to the latch signal generation circuit 54 and the gate 58, and a latch signal is supplied from the latch signal generation circuit 54 to the latch 56. In response to the latch signal, the latch 56 latches the horizontal position data Hp from the H counter 60 and the vertical position data Vp from the V counter 62. The position data Hp and Vp latched by the latch 56 are applied to the data bus of the CPU 12 through the gate 58. In this way, the CPU 12 is given the current luminance signal position data on the screen of the raster scan monitor 20.

When the CPU 12 reads another specific address, the signal D7 is output from the interrupt signal generation circuit 40 via the gate 42 (FIG. 2). This signal D7 is a signal indicating whether or not the CPU 12 is in the interrupt state at that time. In response to this signal, both the interrupt condition data from the latch 36 (FIG. 2) become "0", The signal from the selector 72 (FIG. 6) becomes "0", and the signal is passed through the OR gate 82.
Since this signal is given to the reset input of RS-FF80, this RS-FF
80 is reset. In this way, the CPU 12 can read the other specific address to interrupt the next frame at the same horizontal position and / or vertical position again.

Further, when specific interrupt condition data is set in the latch 36 (FIG. 2), the RS-FF 80 in the interrupt signal generating circuit 40 is reset, and the interrupt signal / IRQ to the CPU 12 is inhibited.

In the above-described embodiment, as shown in FIGS. 2 and 3, both the HV counter circuit 28 and the PPU 14 are provided with H counters 30 and 60 and V counters 32 and 62.
However, as shown in FIG.
And PPU 14 are a set of H counter 86 and V counter 88
Can be configured to be shared. In the embodiment shown in FIG. 7, the decoder 90 includes the functions of the decoder 38 of FIG. 2 and the decoder 46 of FIG. Therefore, a latch signal is applied from this decoder 90 to latch 36 and interrupt signal generation circuit 40, and the latch signal generation circuit
An enable signal is applied to 54 and a gate 58.

The other parts in FIG. 7 are the same as those in the above-described embodiment, and therefore, the same reference numerals are given here, and the duplicate description will be omitted.

In the embodiment of FIG. 7, the interrupt signal / IRQ is obtained from the interrupt signal generating circuit 40 at a desired position on the screen of the raster scan monitor 20 (FIG. 1) set by the CPU 12, and
The CPU 12 sets the position data H from the H counter and the V counter.
p and Vp can be read.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing an HV counter circuit included in the embodiment of FIG. FIG. 3 is a block diagram showing a PPU in the embodiment of FIG. FIG. 4 is an illustrative view showing one example of object data. FIG. 5 is an illustrative view showing one example of still image data. FIG. 6 is a block diagram showing the interrupt signal generating circuit shown in FIG. FIG. 7 is a block diagram showing a modification in which the H counter and the V counter are shared by the HV counter circuit and the PPU in the embodiment of FIG. In the figure, 10 is an image processing device, 12 is a CPU, 14 is a PPU, 16
Is a program storage device, 18 is an image memory, 20 is a raster scan monitor, 26 is a timing signal generation circuit, 28 is an HV counter circuit, 30, 60, and 84 are H counters, 32, 62, and 86 are V counters, and 34 is a comparison. Reference numeral 40 denotes an interrupt signal generation circuit.

Continuing from the front page (72) Inventor Satoshi Nishikai Nintendo Co., Ltd. 60, Fukuinakami Takamatsu-cho, Higashiyama-ku, Kyoto-shi, Kyoto (72) Inventor Hitoshi Yamamoto 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company, Limited (56) References JP-A-60-173580 (JP, A) JP-A-59-94135 (JP, A) JP-A-1-288897 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) G09G 5/00-5/40

Claims (3)

(57) [Claims] 1. An interrupt control device in an image processing device for displaying an image on a raster scan monitor under the control of a CPU, wherein said horizontal counter means counts a horizontal position on a screen of said raster scan monitor; Vertical counter means for counting the vertical position on the screen of the scan monitor; horizontal position data and vertical position data on the screen of the raster scan monitor to be interrupted by the CPU; and the CPU
First to temporarily store the interrupt condition data given from
Storage means for comparing a count value in the horizontal counter means with the horizontal position data in the first storage means;
Comparing means for comparing the count value in the vertical counter means with the vertical position data in the first storage means.
And an interrupt signal generating means for generating an interrupt signal when an output of at least one of the first comparing means and the second comparing means satisfies a condition specified by the interrupt condition data. , Interrupt control device. 2. The interrupt condition data includes data for setting use of an output of the first comparison means and data for setting use of an output of the second comparison means. The interrupt control device according to claim 1, further comprising: 3. An interrupt control device in an image processing device for displaying an image on a raster scan monitor under the control of a CPU, wherein said horizontal counter means counts a horizontal position on a screen of said raster scan monitor; Vertical counter means for counting the vertical position on the screen of the scan monitor; first storage means for temporarily storing horizontal position data and vertical position data on the screen of the raster scan monitor to be interrupted by the CPU; A first value comparing a count value in a horizontal counter means with the horizontal position data in the first storage means;
Comparing means for comparing the count value in the vertical counter means with the vertical position data in the first storage means.
Comparing means, an interrupt signal generating means for generating an interrupt signal in response to outputs from the first comparing means and the second comparing means, in response to a count value holding signal output from the CPU Second storage means for holding the count value in the horizontal counter means and the count value in the vertical count means, and output means for giving the respective count values held in the second storage means to the CPU. An interrupt control device.