JPH0767087B2 - Error correction device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an error correction device applied when a digital information signal is transmitted via a transmission path such as a recording medium or an optical fiber.

[Background Art and Problems] Optical digital audio discs (called compact discs) have a spiral-shaped main channel consisting of digital audio signals and a sub-channel consisting of data for control and display. It is recorded in the signal track. Error correction coding processing is performed in each of the main channel and the sub-channel. The sub-channels are defined as eight channels called P, Q, R, S, T, U, V and W. Of these, the P channel and the Q channel are used for selecting a program when reproducing the compact disc, and the display channels or audio data are inserted in the remaining 6 channels of R to W. For example, data for explaining the composer, performer, etc. of the music recorded in the main channel is recorded in the 6 channels R to W.

This sub-channel data includes control data such as an instruction for representing the type of actually recorded data and an instruction for processing the sub-channel data. This control data is necessary for correctly processing the subchannel display or audio data, and its importance is higher than that of the display or audio data. Therefore, during playback, there is an error in this control data. It is necessary to prevent inclusion as much as possible. For example, if even one bit of control data causes an error, the data for display is erroneously processed as audio data,
An abnormal sound may be generated from the speaker.

Not limited to the subchannel data of this compact disk, the type of data transmitted may not be the same. For example, in a video-text system using a home television set as a display device by using an existing telephone line network or optical transmission line, in order to transmit graphic information, control is performed as a special command in addition to a command indicating a basic element. Commands may be used.

"Object of the Invention" The present invention provides common error detection or error together with other data for more important data when different types of data are included in the data transmitted through the same transmission path. The present invention proposes an error correction device that performs correction processing and error correction decoding processing when original error detection or error correction processing is performed.

[Summary of the Invention] The present invention relates to n symbols (or bits, the same) having the first information and m symbols having the second information, and k symbols for the n symbols. A first error correction code encoding process that generates a redundant code of, and a second error detection code or error correction code encoding process that generates a redundant code of one symbol for (n + k + m) symbols. (N + k +) obtained by the error correction coding process
An error correction device for data of (m + 1) symbols, wherein (n + k + m + 1) symbols are supplied and at least a flag indicating the number of error symbols (including 0) and error location by performing error detection. A first decoder of a second error detection code or an error correction code for generating a signal and (n + k) symbols detected or corrected by the first decoder are supplied, and error correction is performed using a flag signal. And a second decoder of the first error correction code for performing the error correction.

[Embodiment] An embodiment of the present invention is one in which the present invention is applied to an error correction device for data on a sub-channel of a compact disc.

The data structure of the signal recorded on the compact disk will be described with reference to FIGS. 1 and 2.

FIG. 1 shows a data stream recorded on a compact disc. The 588 bits of the recording data are set as one frame, and the frame synchronization pulse FS of a specific bit pattern is added to the beginning of each frame. After the frame synchronization pulse FS, a 3-bit DC suppression bit RB is provided, and thereafter, each 14-bit data bit DB 0 to 32 and a 3-bit DC suppression bit RB alternate. It is provided in. This data bit DB
The 0th one among them is called a sub-coding signal or user's bit, and is used for reproduction control of a disk and display of related information. 1 to 1
The 2,17th to 28th data bit DBs are assigned to the main channel audio data, and the remaining 13th to 16th, 29th to 32nd data bit DBs are assigned to the parity data of the main channel error correction code. Each data bit DB contains 8 bit data when recorded by 8-14 conversion.
It was converted to 14 bits.

The 98 frames of the digital signal described above are called one block, and various kinds of processing are performed in units of this one block.

Fig. 2 shows each data bit DB except the DC suppression bit.
8 blocks, 1 block (98 frames) is arranged in parallel in order. The sub-coding signals P to W of the 0 and 1 frames form a sync pattern which is a predetermined bit pattern. Regarding the Q channel, the CRC code for error detection is inserted in 16 frames on the terminating side of the 98 frames.

The P-channel is a flag that indicates a pose and music. The P-channel is a low level for music, a high level for pause, and a pulse of 2 Hz cycle in the lead-out section. Therefore,
By detecting and counting this P-channel, it becomes possible to select and play the specified music. The Q-channel can perform the same kind of control in a more complicated manner. For example, the information of the Q-channel is taken into a micro computer provided in the disc reproducing device, and the music is immediately reproduced while the music is being reproduced. It is possible to select a random song. Other than this, R-channel to W-channel display the songwriter, composer, commentary, poem, etc. of the song recorded on the disc.
Used for audio commentary.

Also, the data of 69 frames excluding the sync pattern, the P channel, and the Q channel in this one block is used as the packet. As shown in FIG. 3A, this (6 × 9
6) The packet of bits is further divided into four packets of 24 symbols each. The first symbol of each pack is a command, the next 19 symbols are data,
The remaining 4 symbols are the parity of the error correction code of each pack. This command, as shown in FIG.
It's a 6-bit model consisting of a 3-bit item and a 3-bit item.

The information represented by the 3 bits of the mode is defined as follows.

(000): Zero mode (001): Graphic mode (010): Still image mode (011): Speech mode The 3 bits of the item represent detailed operation mode information of each operation mode described above. The zero mode is a case where no information is recorded for the R to W channels of the sub-coding signal. That is, in this zero mode, as shown in FIG.
All bits in the pack, including the bits, are set to 0.

Further, in the graphic mode in which the 3 bits of the mode are (001), data of each pack is arranged as shown in FIG. In this graphics mode, when performing font graphics such as characters and sentences, the 3 bits of the item are set to (001), and in the case of a full graphics that controls the data of the entire display area of the display device, 3 bits are set to (010). The second symbol of each pack in this graphics mode is an instruction. This instruction gives a command for control required in an operation mode specified by a command consisting of a mode and an item.

Error correction coding processing is performed on the two symbols of the command and the instruction in the graphic mode, and the resulting two symbols are added in the parity. The 16 symbols in the pack are used as the data area. Then, error correction coding processing is performed on a total of 20 symbols in the pack, and the resulting parity of 4 symbols is added.

Even in the still image mode or the sound mode, when the predetermined command and instruction are used, the error correction coding process is performed as described above.

To explain the font graphic in graphic mode in more detail, the area used in the display screen is
It is called the screen area, and the other area is called the border area. Also, as a display device,
Line display shown in FIG. 5A and CR shown in FIG. 5B
Use either T-Display.

The line display screen area has two row addresses (ROW) of 0 and 1 and 40 column addresses of 0 to 39 (COL
UMN) and the position of the font is specified by
Each font is defined by the pack data. One font is composed of (6 × 12) pixels. (6 × 12) pixels are sufficient for alphanumeric display, but (24 × 2) for Japanese (especially Kanji) display.
4) One character is displayed for each pixel.

The screen area of the CRT display has a size in which eight line displays are arranged. Therefore, the position is designated by the row address of 0 to 15 and the column address of 0 to 39.

The foreground color of the font displayed in the screen area of the above line display or the CRT display or the background color thereof is determined by 3 bits corresponding to the respective components of R (red), G (green) and B (blue). Specified. FIG. 6 is a color table showing the colors represented by 3 bits.

Fontgrafic instruction (RSTU
VW 6 bits) is defined as follows.

1 = 000001: Preset screen 2 = 000010: Preset border 4 = 000100: Light font (without flash) 5 = 000101: Light font (with flash) 8 = 001000: Scroll left line on line display 16 = 010000: Scroll a predetermined line on the CRT display Left 17 = 010001: Scroll a predetermined column on the CRT display 18 = 010010: Scroll left on the CRT display 19 = 010011: Scroll right on the CRT display 20 = 010100: Scroll up on CRT display In case of preset screen or preset border (instruction 1 or 2) in the above instructions, data area consisting of 4th symbol to 19th symbol in 1 pack. Is 4 as shown in FIG. 7A.
The 3 bits of (RST) in the th symbol are used as data (COLOR) for specifying the color, and all other bits are set to 0.
The preset screen (instruction 1) presets the screen area of the line display and CRT display to the specified color. The preset border (instruction 2) is a line display and
Preset the border area of the CRT display to the specified color.

In the case of the write font (instruction 4), the data area in the pack is the format shown in FIG. 7B. The 3-bit (COL0) specifies the color of the background in the font, and (COL1) specifies the color of the foreground. RL and COLUMN
-L is a font address on the line display. ROM-C and COLUMN-C are font addresses on the CRT display. (6 in the data area of the pack
× 16) Bits are the data of the pixels of the font, y is the pixel of the left top in the font, and z is the bottom pixel of the right in the font. When the pixel is 0, it is the background color, and when it is 1, it is the foreground color. In the light font (with flash) (instruction 5), the font is switched between the foreground color and the background color alternately.

In addition, instruction 8 and instruction 16
Shifts the specified line left by one address. The instruction 17 shifts the designated column right by one address. Instruction 18
Shifts all fonts on the CRT display one address to the left. Instruction 19 is a CRT
Shift all fonts on display to the right by one address. Instruction 20 shifts all fonts on the CRT display up by one address. Corresponding to these instructions,
Although not shown, the data area of the pack is a predetermined format.

The error correction code relating to the above sub-coding signal will be described. A (24,20) Reed-Solomon code is used as an error correction code for a (6 × 24) bit pack. The Reed-Solomon code, GF (2 ⁶⁾ (where, GF is Galois field) are polynomials over ^{(P (X) = X 6} + X +
1). As the parity check matrix Hp of this Reed-Solomon code, the one shown in FIG. 8 is used. GF
The primitive element a in ( ²⁶ ) is a = [000010].

Further, one pack of reproduced data is represented by a reproduced data matrix Vp as shown in FIG. The suffix attached to each of the 24 symbols indicates the symbol number of the sub-coding signal, and n in this suffix means the number of the pack. S _24n is a command and S _{24n + 1} is
_{Q24n + 2} and _{Q24n + 3} are the instruction symbols for this command and instruction, and _{P24n + 20} , _{P24n + 21} , _{P24n + 22} and _{P24n + 23} are ， It is the palacity symbol of the pack mentioned above. The parity of these four symbols satisfies (Hp · Vp = 0).

The (4,2) Reed-Solomon code is used as an error correction code for commands and instructions.
The Reed-Solomon code, polynomial over GF (2 ⁶⁾ (P
(X) = X ⁶ + X + 1). Parity check matrix
Hq and the reproduction data matrix Vq are shown in FIG.
The primitive element a on GF (2 ⁶ ) is a = [000010]. The _parity symbols Q _{24n + 2} and Q _{24n + 3} are
(Hq · Vq = 0) is satisfied. This one embodiment is the case of (n = 2) (k = 2) (m = 16) (l = 4).

The Reed-Solomon code including 4 P parity symbols can correct 1 and 2 symbol errors and detect 3 or more symbol errors. Also, the Reed-Solomon code including two Q symbols can correct one symbol error and detect two or more symbol errors.

FIG. 10 shows a basic structure for forming data recorded on the compact disk. In FIG. 10, reference numerals 1 and 2 denote input terminals to which a 2-channel audio signal such as stereo is supplied from a source such as a tape recorder. The audio signal of each channel is supplied to the sample and hold circuits 5 and 6 via the low pass filters 3 and 4, and one sample is converted into 16 bits by the A / D converters 7 and 8. The 2-channel audio PCM signal is converted into a 1-channel audio signal by the multiplexer 9 and supplied to the error correction encoder 10.

In the error correction encoder 10, the audio PCM signal is cross-interleaved and encoded by the Reed-Solomon code so that the error can be corrected. The cross interleave processing rearranges the order of data so that each symbol is included in two different error correction code sequences. The output of the error correction encoder 10 is supplied to the multiplexer 11.

Further, an encoder 12 for the P channel and Q channel of the sub-coding signal and an encoder 13 for the R channel to W channel are provided. These outputs are combined by a multiplexer 14,
Supplied to 11. The output of the multiplexer 11 is supplied to the digital modulation circuit 15 and subjected to (8 → 14) conversion modulation. In this case, the frame syncs from the sync signal generation circuit 16 are mixed and taken out to the output terminal 17. The encoder 12 for P channel and Q channel is configured to add a 16-bit CRC code to the Q channel,
Encoder 13 for R channel to W channel
It performs error correction coding using Reed-Solomon code and interleave.

Further, the clock pulse and the timing signal formed by the timing generation circuit 18 are supplied to each circuit such as the sample and hold circuits 5 and 6, the A / D converters 7 and 8, and the multiplexers 9, 11 and 14. Reference numeral 19 is an oscillator for generating a master clock.

FIG. 11 shows the structure of a reproducing system for processing the reproduced signal of the compact disc, and the signal reproduced optically from the compact disc is supplied to the input terminal 20.

This reproduction signal is supplied to the digital demodulation circuit 22, the clock reproduction circuit 23, and the synchronization detection circuit 24 via the waveform shaping circuit 21. A clock reproducing circuit 23 having a PLL structure extracts a bit clock synchronized with the reproduced data. Further, the synchronization detection circuit 24 is configured to detect a frame sync and generate a timing signal synchronized with reproduction data, and supplies a predetermined timing signal to each circuit of the reproduction system.

Of the output of the digital demodulation circuit 22, the main channel data is subjected to error detection, error correction and interpolation processing in the error correction circuit 25. Further, the sub-coding signal is subjected to error detection and error correction processing in the decoder 33.

The output of the error correction circuit 25 is supplied to the demultiplexer 26, divided into two channels, and D / A for each channel.
Reproduction audio signals of the respective channels appear at output terminals 31 and 32 via converters 27 and 28 and low-pass filters 29 and 30, respectively.

Further, the data of P-channel and Q-channel of the sub-coding signal obtained from the decoder 33 are supplied to the system control 34 by the micro computer and used for performing a cueing operation, a random music selection and the like. The time code included in the Q channel is supplied to the display unit 35 and displayed.

Further, the display data included in the R channel to the W channel is converted into an analog signal by the D / A converter 36 and taken out to the output terminal 38 via the low pass filter 37. This display signal is supplied to the CRT display. Further, audio data such as explanations of the songs included in the R channel to the W channel are taken out to the output terminal 41 via the D / A converter 39 and the low pass filter 40, and via a low frequency amplifier (not shown). Supplied to the speaker.

Encoder 13 for R channel to W channel
It is provided with the error correction encoder shown in FIG.

The error correction encoder is, as shown by the broken line, the Q parity generator 51 of the above-mentioned (4,2) Reed-Solomon code,
It is composed of a P parity generator 52 of the (24,20) Reed-Solomon code and an interleave circuit 53.
This error-correcting encoder has S _24n , S of the nth _pack .
A total of 18 symbols of _{24n + 1} , S _{24n + 4 to} S _{24n + 19} are input.

Two symbols S _24n and S _{24n + 1} are supplied to the Q parity generator 51, and parity symbols of Q _{24n + 2} and Q _{24n + 3} are generated.
Twenty symbols including this Q parity are input to the P parity generator 52, and four parity symbols are generated. The 24 symbols output from the P parity generator 52 are supplied to the interleave circuit 53.

The interleave circuit 53 is composed of a RAM and its address controller, and controls the write address and the read address to generate output data in which a predetermined delay amount is added to each symbol of the input data. 12th
In the figure, a means for giving a predetermined delay amount to each symbol is shown as a plurality of delay elements for easy understanding. The delay elements include delay elements 61, 71, 81 for giving a delay amount of 1 pack (24 symbols) and delay elements 62, 72, 82 for giving a delay amount of 2 packs, and delay amounts of 3 packs. Delay elements 63, 73, 83 and delay elements 64, 7 with a delay amount of 4 packs
Delay elements 65,75,85 with delay amounts of 4,84 and 5 packs, delay elements 66,76,86 with delay amounts of 6 packs, and delay elements 67,77,87 with delay amounts of 7 packs are used. Further, the delay amount is 0 for the symbol in which the delay element is not inserted. As described above, three sets of eight delay amounts from 0 to 7 packs are provided.

This interleave circuit 53 performs interleave as shown in FIG. Eight consecutive packs of input data series and output data series having the same length as this are shown in parallel in FIG. Focusing on the first pack (indicated by the shaded area) of the input data series,
Twenty-four symbols are dispersed in the output data sequence at positions separated by a distance of 8 symbols or 9 symbols. If the output data sequence is equally divided at intervals of 8 symbols, then the three symbols of the pack of interest as the head symbol of each set of 8 symbols from the first to the third are arranged. As the second symbol of each set of 8 symbols from the fourth to the sixth, the three symbols of the pack are arranged.

Thereafter, in the same manner, the three symbols of the pack are arranged at positions shifted by one symbol for every three symbols of the set of 8 symbols. Therefore, in the last three symbols of the output data series shown in FIG. 13, the three symbols of the pack are arranged as the eighth symbol of each set.
In the 24 symbols consisting of 3 of the set of 8 symbols, the symbols of the pack are arranged at a distance of 8 symbols each. Also, at the boundary of three sets of 8 symbols, there is a deviation of 1 symbol, so there is a distance of 9 symbols.

Further, in the set of 8 symbols, the symbols of a plurality of packs at the timings after the pack are arranged in an interleaved manner at the positions generated before the position of the pack symbol in the same manner as the pack. Further, in the set of 8 symbols, the symbols of a plurality of packs at the timing before the pack are arranged in an interleaved manner at the position after the position of the pack symbol, like the pack.

When the error condition in the reproduction sub-coding signal of the compact disk is measured, burst error of 4 symbols or more hardly occurs. Therefore, by recording the 24 symbols included in the same sequence of the (24,20) Reed-Solomon code in a distributed manner as described above, two or more symbols become error symbols and error correction is performed. It can be effectively prevented from becoming impossible.

Further, as shown in FIG. 12, the interleave circuit 53 is
Interleaving is performed so that the distance between commands, instructions, and these Q parity symbols included in the same pack is made larger than that of the other symbols. For this reason, as shown in FIG. 12, the input symbol supply lines for each of the delay elements are not all parallel, and the interleave circuit 53 includes six oblique supply lines.

In order to clarify the characteristics of this interleave, assuming that the supply lines of the input symbols are all parallel, one pack
The correspondence between 24 symbols and the data positions in the output sequence after interleaving is shown in FIG. In FIG. 14 and FIG. 15 to be described next, the time width of one pack of input data is expanded to eight times that of the original one.

As shown in FIG. 14, the first eight symbols S _24n , S _{24n + 1} , Q _{24n + 2} , Q _{24n + 3} ... S _{24n + 7} of the input symbols are respectively
A delay amount of 0, 1 pack, 2 packs, 3 packs ... 7 packs is given. Therefore, these eight symbols have symbol numbers (−24) and (−) in the output data series.
24 × 2), (-24 × 3) ... (-24 × 7). 8 symbols next to the input symbol S _{24n + 8}
S _{24n + 15} is also given a 0,1 pack delay amount of 7 packs each, and the next eight symbols S _{24n + 16} S _{24n + 16} .
_A similar delay amount is given to _{24n + 23} . As a result of such interleaving, the distances of the first four symbols of the pack from each other are equal to 24 symbols.

In one embodiment of the invention, the symbol S _{24n + 1} is _assigned to the delay element 82.
And the symbol S _{24n + 18} to the delay element 61 and the symbol Q _{24n + 2} to the delay element 65.
The symbol S _{24n + 5} is supplied to the delay element 62, and the symbol Q _{24n + 3} is supplied.
_Is supplied to the delay element 87 and the symbol P _{24n + 23} is supplied to the delay element 63. Therefore, the positions of the above-mentioned symbol pairs are interchanged, and the correspondence relationship between the input data series and the interleaved data series is as shown in FIG. As is clear from FIG. 15, the distances of the first four symbols of the pack from each other are as follows.

Distance between S _24n and S _{24n + 1} : 65 symbols Distance between S _{24n + 1} and Q _{24n + 2} : 58 symbols Distance between Q _{24n + 2} and Q _{24n + 3} : 65 symbols Can be more than doubled compared to 25 symbols, and the error correction capability for burst errors occurring in reproduced data can be further enhanced.

FIG. 16 shows a decoder 33 for reproducing sub-coding signals.
2 shows an error correction decoder for R channel to W channel provided in FIG.

As shown by the broken line, this error correction decoder is provided with a deinterleave circuit 91 to which 24 symbols of one pack of the reproduced subcoding signal are supplied, and an output of this deinterleave circuit 91 to P ₁ Decoder 92 and this
The first 4 symbols of the output of the P ₁ decoder 92 are supplied to the Q decoder 93 of the (4,2) Reed-Solomon code, and the above-mentioned four error-corrected Q decoder 93 are used. One pack of symbols consisting of 20 symbols from the symbols and the P ₁ decoder 92 is supplied to the P ₂ decoder 94 of the (24,20) Reed-Solomon code.

The P ₁ decoder 92 detects the error magnitude and calculates the error location in each case of 1-symbol error and 2-symbol error for 24 symbols of 1 pack, and a flag (P flag indicating this information). Is called) is supplied to the Q decoder 93. Q decoder 93 using this P flag
Corrects the error. Q decoder 93 performs error correction, and generates a Furatsugu (referred to as Q Furatsugu) indicating the number of error symbols (including 0), the Q Furatsugu is supplied to the P ₂ decoder 94, P ₂ decoding The flag and the Q flag indicating the number of error symbols (including 0) and error location generated in the unit 94 are used for error correction in the P ₂ decoder 94.

The input data to the deinterleave circuit 91 is the output data of the interleave circuit 53 in FIG. The delay amount given by the interleaving circuit 53 is cancelled, and deinterleaving is performed so that each symbol has a delay of 7 packs. Actually, this deinterleaving is performed by controlling the write address and read address of RAM. In FIG. 16, the deinterleave circuit 91 is shown as a configuration in which delay elements having a predetermined delay amount are arranged on the transmission line of each symbol. Delay elements of 7 packs are inserted in the transmission lines of the symbols with the delay amount of 0 in the interleave circuit 53, respectively. Further, the transmission lines of the interleave circuit 53 with the delay amount of 1 pack, 2 pack, 3 pack, 4 pack, 5 pack, 6 pack are 6 pack, 5 pack, 4 pack, 3 pack, 2 pack, respectively. The delay element of 1 pack is inserted, and the delay element is not inserted in the transmission line of the symbol whose delay amount in the interleave circuit 53 is 7 packs.

The error correction operation performed by the above P ₁ decoder 92, Q decoder 93 and P ₂ decoder 94 will be described in more detail.

The flow chart shown in FIG. 17A shows the decoding process performed by the P ₁ decoder 92, the flow chart shown in FIG. 17B shows the decoding process performed by the Q decoder 93, and FIG.
The flow chart shown in FIG. 9 shows the decoding process performed by the P ₂ decoder 94. Basically, the Q decoder 93 can correct a 1-symbol error out of 4 symbols, and the P ₂ decoder 94
It is possible to correct 1 and 2 symbol errors out of 24 symbols. The P ₁ decoder 92 first generates the syndromes S _r0 , S _r1 , S _r2 , and S _r3 (step 101).
This calculation is represented by the following equation, where i is the symbol location. In addition, all operations (mod.
2) done.

Using these four syndromes S _{r1 to} S _r3 , an operation for obtaining the error magnitude and the error location is performed.
In order to perform this operation easily and at high speed, constants A, B and C as shown in the following equations are calculated (step 102).

A = S _r0 S _r2 ＋ S ² _r1 B ＝ S _r1 S _r2 ＋ S _r0 S _r3 C ＝ S _r1 S _r3 ＋ S ² _r2 Next, using the above-mentioned syndromes and constants, the size of the error is discriminated (step 103). Is done. By this discrimination and the calculation of the error location, which will be described later, a flag of P indicating the magnitude of the error and the error location is formed. By checking whether (S _r0 ≠ 0, S _r3 ≠ 0, A ≠ 0, B ≠ 0, C ≠ 0), it is judged whether or not there is a two-symbol error (step 104).

If it is not a 2-symbol error, it can be judged whether or not there is an error (step 105). (S _r0 = 0, S _r3 = 0, A ＝
If B = C = 0) holds, it is determined that there is no error.

If there is no error, it is judged whether or not there is a 1-symbol error (step 106). (S _r0 ≠ 0, S _r3 ≠ 0, A ＝
If B = C = 0) holds, there is a 1-symbol error. If it is not a 1-symbol error, it is an error of 3 or more symbols.

In the case of a 2-symbol error, the error location is calculated (step 107). Error location i, j
Is calculated as follows.

In the case of a 1-symbol error, the error location is calculated (step 108). Error location i Required by. In this way, the P flag obtained by the P ₁ decoder 92 is transmitted to the Q decoder 93 of the next stage (step 109). That is, the error locations of the one-symbol error and the two-symbol error are stored in the memory (steps 110 and 112), and the flag indicating no error is generated (step 111).

In the Q decoder 93, as shown in FIG. 17B, first, the syndromes S _r0 and S _r1 are generated (step 121). This calculation is It is represented by. Next, the size of the error is discriminated (step 122) using these syndromes.

It is determined whether or not there is a one-symbol error (step 123), and if there is no one-symbol error, then it is determined (step 124) whether or not there is an error (ie, S _r0 = 0, S _r1 = 0). In the case of a 1-symbol error, the error location is calculated (step 125). Error location i Required by. It is determined (step 126) whether or not the error location i thus obtained is included in the range of (0≤i≤3).

If the error location i falls within this range, P
A check of the flag (step 128) is performed, and it is checked whether or not it matches with the error location by the P flag (step 129). If they match, error correction (step 130) is performed. For error correction, if the playback symbol is ▲ ▼, (▲ ▼ + S _r0 = S _ri )
Is calculated. If the calculated error location i is not included in the above range, or if the P flag and the error location do not match, this 24-symbol pack is an illegal (unusual and should not error) pack. , All symbols have been dropped (step 127). That is, the symbols of the pack when the comadon and the instruction are in error are all invalid.

In addition, the Q flag indicating that there is no error (including the case where one symbol error is corrected) is transmitted to the P decoder 94 (step 131), and the Q flag indicating that there is an error of 2 symbols or more is P ₂ decoded. To the instrument 94 (step 13
2).

In the P ₂ decoder 94, as shown in FIG. _17C , first, the syndromes S _r0 , S _r1 , S _r2 , S _r3 are calculated in the same manner as the above-mentioned step 101 (step 141). These four syndromes S _r0
Using S _r3 , an operation for finding the error magnitude and error location is performed. In order to perform this calculation easily and at high speed, constants A, B, C
Is calculated (step 142). Next, the magnitude of the error is discriminated (step 143) using the above-mentioned syndrome and constant. (S _r0 ≠ 0, S _r3 ≠ 0, A ≠ 0, B ≠ 0, C ≠
By checking whether 0) holds, it is judged whether there is a two-symbol error (step 144).

If there is no two-symbol error, it is judged whether or not there is an error (step 145). (S _r0 = 0, S _r3 = 0, A
= B = C = 0), it is determined that there is no error.

If there is no error, it is judged whether there is a 1-symbol error (step 146). (S _r0 ≠ 0, S _r3 ≠ 0, A ＝
If B = C = 0) holds, there is a 1-symbol error. If it is not a one-symbol error, it is an error of three or more symbols, so that processing as a bad pack (incorrect pack) is performed (step 147). All the symbols of the backpack are obsolete, as in the case of the illegal pack.

In the case of a 2-symbol error, the error location calculation (step 148) is performed. Error location i, j
Is obtained in the same manner as in step 107 described above.

A check as to whether or not this error location i, j is correct is made using the Q flag (step 149). Q
It is checked if the flag indicates either no error or an error of more than two symbols (step 150).

If the Q flag indicates no error, the location check (step 151) is performed. (4 ≦ i <
If j.ltoreq.23) is established, the error location is correct, and therefore a 2-symbol error is corrected (step 153). If the above relationship does not hold, it contradicts the error detection result of the Q decoder 93, so the pack is processed as an illegal pack (step 154). Therefore,
One of the error locations from 0 to 3
The symbols are corrected by the Q decoder 93, the two symbols of the error location contained in 4 to 23 are corrected by the P ₂ decoder 94, and the error of 3 symbols in one pack can be corrected. it can.

If the Q flag indicates an error of 2 symbols or more, the location check (step 152) is performed.
This localization check checks whether or not (0≤i <j≤3) is established. If this relationship is established, a 2-symbol error is corrected (step 153). If this relationship is not established, it is processed as illegal pack.

The correction of the 2-symbol error (step 153) is a process of obtaining the error patterns e _i and e _j and adding them to the reproduced symbol. I.e. ▲ ▼ ＋ e _i ＝ S _i ▲ ▼ ＋ e _j ＝ S _j P _{2 If} the error detection result in the decoder 94 is no error, the check (step 155) of whether the Q flag indicates no error is made. Done. If the Q flag is error-free, it is determined that this pack does not really include an error symbol. On the other hand, when the Q flag indicates the existence of an error of 2 symbols or more, P ₂
Since it is inconsistent with the decoding result of the decoder 94, the pack is processed as an illegal pack.

If the result of error detection by the P ₂ decoder 94 is a 1-symbol error, the error location i is calculated (step 15
6) is done. this is Is the calculation of. Next, the Q flag is checked. If the Q flag has no error, the location check (step 158) is performed. If (4 ≦ i ≦ 23) holds, there is no contradiction with the result of Q decoding, so (▲
▼ + S _r0 = S _i ) error correction (step 159) is performed. If the above relationship is not established, it is processed as illegal pack.

The result of P ₂ decoder 94 is 1 symbol error and Q flag is 2
When an error of more than a symbol is indicated, it cannot be caused by nature, and the pack is processed as an illegal pack.

Further, as a result of P ₂ decoding, when an error of 3 symbols or more is detected, the pack is processed as a bad pack (step 147). The error correction decoder processing is performed as described above.

[Other Embodiments] In the error correction decoder, the 1-symbol error or the 2-symbol error is corrected only in the case where the obtained error location is 4 to 23 in the P ₁ decoder 92 to which 24 packets of 1 pack are supplied. May be performed.

Further, in the configuration in which the P ₁ decoder 92 only detects the magnitude of the error and the error location as in the above-described embodiment or the configuration for correcting the error symbol of the error location of (4 to 23), The P ₂ decoder 94 may be omitted.

“Application Example” Different from the above-described embodiment, other codes such as adjacent codes may be used as the first and second error correction codes. Further, the second code may be a code (CRC code, simple parity) having only an error detecting function. Furthermore, a bit unit error correction code such as a BCH code may be used.

"Effect of Invention" According to the present invention, error correction coding is performed (n
Among (+ k + m + l) symbols, unique error correction coding is performed for (n + k) symbols, so the error size and error location are detected for (n + k + m + l) symbols. Then, using this detection result, error correction of (n + k) symbols can be checked. Therefore, (n + k)
It is possible to prevent the error correction operation of individual symbols from becoming erroneous, and more powerful protection of highly important data such as symbols having information on the operation mode and control contents in the sub-coding signal of the compact disk is possible. Can be

[Brief description of drawings]

1 and 2 are schematic diagrams used for explaining the data structure of the compact disk of one embodiment of the present invention, and FIGS. 3 and 4 are schematic diagrams used for explaining the sub-coding signal of the compact disk. , FIG. 5, FIG. 6 and FIG. 7 are schematic diagrams used for explaining the fontographing mode by the sub-coding signal, and FIG. 8 and FIG. 9 are the error correction code parities in the embodiment of the present invention. FIG. 10 shows a check matrix and a reproduction data matrix, FIG. 10 is a block diagram showing a configuration of a recording system of an embodiment of the present invention, and FIG. 11 is a block diagram showing a configuration of a reproduction system of an embodiment of the present invention. FIG. 12 is a block diagram showing the configuration of an error correction encoder in an embodiment of the present invention, FIGS. 13, 14 and 15 are schematic diagrams used to explain the interleave processing of the error correction encoder, and FIG. From this Block diagram showing the configuration of an error correction decoder in an embodiment of FIG. 17 is a flow chart used for explaining the error correction decoder. 10 …… Main channel error correction encoder, 12…
… Encoders for P and Q channels, 1
3 ... Encoder for R channel to W channel,
20 …… Input terminal to which playback signal of compact disk is supplied, 25 …… Main channel error correction circuit, 33 ……
Sub-coding signal decoder, 51 …… Q parity generator, 52 …… P parity generator, 53 …… Interleave circuit, 91 …… Deinterleave circuit, 92 …… P ₁ decoder, 93…
… Q decoder, 94… P ₂ decoder.

Claims (3)

[Claims] 1. An encoding process of a first error correction code for generating a first redundant code for the first information, and a second process for the first information, the first redundant code and the second information. An error correction device for data obtained by an error correction encoding process comprising a second error correction code encoding process for generating a redundant code, comprising: the first information, the first redundant code, and the first redundant code. 2 information and the second redundant code are supplied, and at least error detection is performed based on the second redundant code to generate a flag signal indicating the number of errors (including 0) and the error location. A first decoder, the first information and the first redundant code obtained through the first decoder are supplied, and an error log is supplied based on the first redundant code. Together seek Shon, when the error location matches the error location of the flag signal, the error correction device characterized by having a second decoder for error correction. 2. An encoding process of a first error correction code for generating a first redundant code for the first information, and a second process for the first information, the first redundant code and the second information. An error correction device for data obtained by an error correction encoding process comprising a second error correction code encoding process for generating a redundant code, comprising: the first information, the first redundant code, and the first redundant code. 2 information and the second redundant code are supplied, and error detection is performed based on the second redundant code to generate a first flag signal indicating the number of errors (including 0) and the error location. And a first decoder which supplies the first information and the first redundancy code obtained through the first decoder, and which is obtained based on the first redundancy code. A second decoder that performs error correction when the location matches the error location of the first flag signal and generates a second flag signal indicating the number of errors (including 0); The information, the first redundant code, the second information, and the second redundant code are supplied from the first and second decoders, and the error location obtained based on the second redundant code and the error location An error correction device comprising: a third decoder that performs an error correction process using a second flag signal. 3. The first information, the first redundancy code,
The second information and the second redundancy code are data recorded as a sub-channel of a disc in which an information signal is recorded as a main channel, and the second information is a display in the data of the sub-channel. 3. The error correction device according to claim 1, wherein the first information is control data of the sub-channel.