JPS5765937A - Split duplex interleave method - Google Patents

Split duplex interleave method

Info

Publication number
JPS5765937A
JPS5765937A JP55143497A JP14349780A JPS5765937A JP S5765937 A JPS5765937 A JP S5765937A JP 55143497 A JP55143497 A JP 55143497A JP 14349780 A JP14349780 A JP 14349780A JP S5765937 A JPS5765937 A JP S5765937A
Authority
JP
Japan
Prior art keywords
words
block
given
crc
duplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55143497A
Other languages
Japanese (ja)
Inventor
Tsuneo Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55143497A priority Critical patent/JPS5765937A/en
Publication of JPS5765937A publication Critical patent/JPS5765937A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To reduce a required memory quantity and to make the duplex interleave of high capability for correction possible, by providing a duplex interleave means for every block length unit of information and a means which gives a CRC to plural block length units. CONSTITUTION:Information words are divided, and several words are defined as one block, and parities P and Q are given to the block, and a CRC (cyclic redundancy check code) is given to a large block length unit consisting of plural block length unit. For example, oblique and lateral parities P and Q are given to every bolck length consisting of 4 words of 16 words W<(1)>-W<(16)>, and the CRC is given to every large block consisting of words W<(1)>-W<(16)>. By split P and Q for every small block, the separation distance for every word of the P sequence required for preventing the occurrence of detection error is shortened, and a code constitution of a high capability for correction is possible with a small memory quantity.
JP55143497A 1980-10-13 1980-10-13 Split duplex interleave method Pending JPS5765937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55143497A JPS5765937A (en) 1980-10-13 1980-10-13 Split duplex interleave method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55143497A JPS5765937A (en) 1980-10-13 1980-10-13 Split duplex interleave method

Publications (1)

Publication Number Publication Date
JPS5765937A true JPS5765937A (en) 1982-04-21

Family

ID=15340082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55143497A Pending JPS5765937A (en) 1980-10-13 1980-10-13 Split duplex interleave method

Country Status (1)

Country Link
JP (1) JPS5765937A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172853A (en) * 1983-03-19 1984-09-29 Sony Corp Error correcting device
JPS6029073A (en) * 1983-06-17 1985-02-14 Hitachi Ltd Digital signal configuration method
JPS6133022A (en) * 1984-07-25 1986-02-15 Mitsubishi Electric Corp Code processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172853A (en) * 1983-03-19 1984-09-29 Sony Corp Error correcting device
JPS6029073A (en) * 1983-06-17 1985-02-14 Hitachi Ltd Digital signal configuration method
JPS6133022A (en) * 1984-07-25 1986-02-15 Mitsubishi Electric Corp Code processor

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