JPS59172853A - Error correcting device - Google Patents

Abstract

PURPOSE:To protect more strongly a data with higher priority by applying a unique error correcting code to (n+k)-set of symbols among (n+k+m+1)-set of symbols subjected to error correction coding. CONSTITUTION:In a subchannel of a compact disc where an information signal is recorded as a main channel, data for control of n-set of symbols are added with redundant code of k-set of symbols and encoded. The input data added with a data for display of m-set of symbols and one redundancy code and encoded and being subject to error correction coding and processing of (n+k+m+ 1)-set of symbols, is detected for the size of an error and an error location by a decoder 92, a P flag representing it is generated and applied to a decoder 93. The decoder 93 uses the P flag,corrects the error, generates a Q flag representing the size of error and applies it to a decoder 94. The decoder 94 uses the flags P, Q so as to check the error correction of the (n+k)-set of symbols and strengthen the protection of the control data.

Description

[Detailed description of the invention] "Industrial application field" This invention provides a recording medium for digital information signals.

01-Background technology and its problems related to error correction devices applied when transmitting via transmission paths such as optical fibers'' Optical digital audio disks (referred to as compact disks) are capable of converting digital audio signals into for main channel and control.

Sub-channels consisting of data for display etc. are recorded in a spiral signal trunk. The 0 subchannel, on which error correction encoding processing is performed on each of the main channel and subchannels, includes
, T, U, V, and W are defined. Of these channels, the P channel and Q channel are used to select a program when playing back a compact disc, and the remaining 6 channels of RNW are used to insert 9 display data or audio data. For example, the composer of the music recorded on the main channel.

Data for explaining the performer and the like is recorded on six R-W channels.

This subchannel data includes control data such as indicating the type of data actually recorded and instructions for processing the subchannel data. This control data is necessary to correctly process the display or audio data of the subchannel, and its importance is higher than that of the display or audio data. Therefore, during playback, this control data It is necessary to prevent errors from being included as much as possible.

For example, if an error occurs in even one bit of the control data, data for two displays will be mistakenly processed as audio data, resulting in a situation where an abnormality l:t occurs from the speakers.

In addition to the subchannel data G of this compact disc, the types of data to be transmitted may not be the same. For example, in a videotex system that uses existing telephone lines and optical transmission lines and uses a home television receiver as a display device.

In transmitting graphic information, control commands are sometimes used as special commands in addition to commands representing basic elements.

``Object of the invention'' This invention is applicable to cases where different types of data are included in data transmitted through the same transmission path.

For more important data, error detection or error correction processing is performed in common with data other than stiffness, and error correction decoding processing is performed if unique error detection or error correction processing is performed. This paper proposes an error correction device.

"Summary of the Invention" The present invention is applicable to transmission of data of n symbols (or bits, hereinafter the same) and m symbols of different types as a unit.

a first error correction code encoding process that generates a redundant code of n symbols for n symbols;

a second error detection code or error correction code encoding process that generates a redundant code of one symbol for every (n ten m) symbols G;

(n100m)
+1) symbol-based data error correction device G.

(nfk10m+1) symbols are supplied.

at least a first decoder of the second error detection code or error correction code for performing error detection and thereby generating a flag signal indicating the number (including zero) of error symbols and the location of the error;

The first decoder is supplied with (n ten k) symbols passed through the first decoder, and performs error detection using a flag signal.
and a second decoder for an error correction code.

Embodiment An embodiment of the present invention is an application of the present invention to an error correction device for subchannel data of a compact disc.

The data structure of a signal recorded on a compact disc will be explained with reference to FIGS. 1 and 2. FIG. 1 shows a data stream recorded on a compact disc. One frame of recording data is 588 bits long, and a frame synchronization pulse FS of a specific bit pattern is added to the beginning of each frame. After the frame synchronization pulse Jul S, a 3-bit DC component suppression pitch (RB) is provided, and then a G
Each of these 14-bit data bits DB numbered 0 to 32 and 3-bit DC component suppression bits RB are provided alternately. The 0th bit in the data bit DB is called a sub-coding signal or user's bit, and is used to control playback of the disc, display related information, etc. 1 to 12. The 17th to 28th data bits DB are allocated to main channel audio data.

The remaining 13th to 16th and 29th to 32nd data bits DB are allocated to parity data of the error correction code of the main channel. Each data bit DB has 8 bits when recording.
8-bit data is converted to 14-bit data by -14 conversion.

The 98 frames of the digital signal described above are called one block, and various processes are performed in block units.
B is 8 bits, and blocks (98 frames) are arranged in parallel in order. The sub-coding signals P-W of frames O and 1 are as follows.

A sync pattern, which is a predetermined bit pattern, is formed. Also, regarding the Q channel.

A CRC code for error detection is inserted in the last 16 frames out of 98 frames.A flag indicating the OPP channel, pause, and music. 2
8 Z period pulse is interrupted. Therefore, this P
OQQ allows you to select and play specified music by detecting and counting channels.
Channels, the same type of control can be performed in a more complex manner.1 For example, information on the Q channel can be imported into a microcomputer installed in a disc playback device, and even if music is in the middle of being played, it can immediately shift to playing other music, such as the G channel. Random music selections such as Other R channels to W channels.

Lyricists and composers of the songs recorded on the disc.

It is used to display explanations, poems, etc., and to provide audio explanations.

Furthermore, the sync pattern, P channel, and Q channel of this one block are expressed as l'c'j<, and 96 frames of data are taken as a packet. As shown in FIG. 3A, this (6×96) bit packet is further divided into four packs of 24 symbols each. The first symbol of each puncture is a command, the next 19 symbols are data, and the remaining four symbols are the parity of each pack's error correction code. This command is a 6-bit command consisting of a 3-bit mode and a 3-bit item, as shown in FIG. 3B.

The information represented by the three bits of the mode is determined as follows.

(000): Zero mode (001,) Graphic mode (010): Still one-stroke mode (011,): Sound mode The 3 bits in the item represent more detailed information on each of the above-mentioned operation modes. . Zero mode is a case where no information is recorded for the R-W channel of the sub-coding signal.

That is, in this zero mode, as shown in FIG. 4, all bits in the pack, including the 6 bits of mode and item, are truncated.

In addition, in the graphic mode where the 3 bits of the mode are (OO1), as shown in FIG.

Data for each pack is arranged. When using this graphic mode to create graphics using a font such as 1 character and 9 sentences, the 3 bits of the item are (001,) and in the case of a full graphic that controls the data of the entire display area of 1 display device, the eye left button is 3 bits are interrupted at (010). The second symbol of each pack in this graphic mode is taken as an instruction. This instruction gives necessary control commands in an operation mode defined by a command consisting of a mode and an item.

The error correction encoding process is performed on the two symbols of this graphic mode command and instruction, and the parity of the resulting two symbols is added. Also, the 16 symbols in the back are saved as a data area. and.

Error correction encoding processing is performed on a total of 20 symbols G in the background, and parity of the resulting 4 symbols is added.O Also in still picture mode or sound mode.

In the first case where predetermined commands and instructions are used, error correction encoding processing is performed in the same manner as described above.

To explain in more detail about the font graphics in graphic mode, the area used in one display screen is:
The screen area is called the screen area, and the area thereafter is called the border area.One display device is the line display shown in FIG. 5J, and the line display shown in FIG.
The screen area of the 0 line nice play using something like 21 with a CRT display as shown in 2 of 0 and 1
The position of a font is specified by a row address (ROW) and 40 column addresses (COT, UMN) from 0 to 39, and each font is defined by pack data. One font consists of (6×12) pixels. For alphabetical display,
(6x12) pixels is enough, but 1 Japanese (especially Kanji)
In the case of the display, one character is displayed using '(24×24) pixels.

Also, the screen area of a CRT display.

It is said to be the size of eight line displays lined up.

Therefore, the position is specified by a row address of 0 to 15 and a column address of 0 to 39.

The foreground color or the background color of the font displayed in the screen area of the above-mentioned line display or CRT display is the 3-bit O color corresponding to each component of R (red), G (green), and B (blue). Therefore, it is specified. FIG. 6 is a color table showing colors expressed in 3 bits.

Font Graph Inc. Instructions (RS T
(6 bits of U V W) is defined as the first order.

1=000001 Nib reset screen 2=OO
0010: Preset border 4 = OOO100 Ni-light font (without flash) 5 = OO0101 Ni-light font (with flash) 8 = OO1, OOO Ni-line display Scroll the specified line with 2 Left 16 = 010000: Specified on the CRT display Scroll left 17 = 010001: Scroll up a given column on CRT display 18 = 0100] 0: Scroll left 19 201001118 on CRT display Scroll right 20 = 01.01 on CRT display. OO: Scroll up on the cRT display using the instructions above to scroll up the preset screen or preset border (instruction 1 or 2).
), 19 from the 4th symbol in one pack
In the data area consisting of the 9th symbol, as shown in No. 778, the 3 bits (R8T) in the 4th symbol specify the color (c OL OR) and Biwa 7. All other values are set to O. The preset screen (instruction 1) is for line displays and CRTs.
Preset the screen area of display 1' to the specified color. Brisset Border (Instruction 2)
) presets the border area of the line display and CRT display to the specified color.

The data area in the pack for the light font (instruction 4) has the format shown in FIG. 7B. 3 bit (COLO) is.

Specifies the background color in the font, '(COLI).

Specify the foreground color. RL and COLUMN-L.

This is the address of the font on the line display. R
OW-C and COLUMN-C are the addresses of the font on the CR'l'' display.
When the 0 pixel is 0, the one indicated by y is the top pixel on the left side of the font, and the one indicated by 2 is the bottom pixel on the right side of the font. When this is 1, it is set as the foreground color. In addition, when using light font (with flash) (instruction 5), the font is switched alternately between the foreground color and the background color.

Also, instruction 8 and instruction 1
6 shifts the specified line one address to the left. Instruction 17 is.

Shifts the specified edge column one address to the right.

Instruction 18 shifts all fonts in the C'RT diffuse to the left by 11 addresses. Instruction 19 is.

CT (Shift all fonts on the CRT display to the right by one address. Instructions 20 shift all fonts on the CRT display up by one address. Show one diagram corresponding to these instructions. Zumo.

The data area of the pack has a predetermined format.

The error correction code (
Let me explain in detail. A (24°20) Reed-Solomon code is used as an error correction code for a pack of (6×24) humans. This Reed-Solomon code is C,
A polynomial on F(2) (where GF is a Galois field) is (P(
χ)=χ1X+1). As the parity check matrix H9 of this Reed-Solomon code, the one shown in FIG. 8 is used.

The primitive element a on 0F(2) is a=[0000,10] belongs to.

Further, one pack of 'FQ raw data is represented by a reproduced data matrix (2) as shown in FIG. 8G. The suffix for each of the 24 symbols indicates the symbol number of the sub-coding signal, and n in this suffix is
It means the pack number.

524n is a command, 524n+1 is an instruction, Q24□+2 and Q24□+3 are parity symbols for this command and instruction + P24n+20+ p24n+2
1 + P24n+22+P24n+23 is the parity symbol of the pack as described above. What is the parity of these four symbols?

It satisfies (H,·v,,=O).

A (4,2) Reed-Solomon code is used as an error correction code for commands and instructions. This Reed-Solomon code has a polynomial of (P (X) =X+X+1)(7) on GF(2). The harrity check matrix Hq and the reproduced data matrix q are shown in FIG. ()'F ('2)
The primitive element a above is a' = (000010') 0 parity symbol Q24□4-2 and Q
24n+3 satisfies (Hq·■q−0). One example of this is (n = 2) (k
= 2) (m=16) (1=4).

A Reed-Solomon code containing four P parity symbols is capable of correcting one and two symbol errors and detecting three or more symbol errors. Also, 2
A Riet-Solomon code including Q symbols is capable of correcting one symbol error and detecting two or more symbol errors.

FIG. 10 shows the basic configuration for forming data recorded on a compact disc G. In FIG. 10, 1 and 2 indicate input terminals to which two-channel audio signals such as stereo are supplied from a source such as a tape recorder. The audio signals of each channel are supplied to sample and hold circuits 5 and 6 via low-pass filters 3 and 4, and one sample is converted into 16 bits by A/D converters 7 and 8. This 2-channel audio PCM signal is converted into a 1-channel signal by multiplexer 9G.

The signal is supplied to an error correction encoder 10.゛The error correction encoder 10 cross-interleaves the audio PCM (i) to perform error-correctable encoding using a Reed-Solomon code. It rearranges the order of data so that

The output of this error correction encoder 10 is supplied to a multiplexer 1-1.

Further, an encoder 12 for the P channel and Q channel of the subcoding signal and an encoder 13 for the R channel to W channel are provided, and the outputs of the subcoding signals are combined by a multiplexer 14, The output of is supplied to the digital modulation circuit 15 20. (8 → 14)
Subject to conversion modulation. In this case, the synchronization signal generation circuit 16
The frame syncs from the P and Q channels are mixed and output to the output terminal 17. The encoder 12 for the P channel and the Q channel is configured to add a 16-bit CRC code to the Q channel.

The encoder 13 for the B channel to W channel performs error correction encoding using a Reed-Solomon code and interleaving.

In addition, sample hold circuits 5, 6, A/'II
:J converter 7, 8. Multiplexer 9, 11.1
Reference numeral 019 to which clock pulses and timing signals generated by the timing generation circuit 18 are supplied to each circuit such as 4 is an oscillator for generating a master clock.

FIG. 11 shows the configuration of a reproducing system for processing a compact disc (1'), in which a signal optically reproduced from a compact disc is supplied to an input terminal 20.

This reproduced signal is passed through the waveform shaping circuit 21 to the digital demodulation circuit 22. Clock regeneration circuit 23 and synchronization detection circuit 2
The supply runs out at 4. Clock regeneration circuit 2 configured with Pl and L
3, a pit clock synchronized with the reproduced data is extracted. The synchronization detection circuit 24 is configured to detect frame sync and generate a timing signal synchronized with the reproduced data, and supplies a predetermined timing signal to each circuit in the reproduction system.

Among the outputs of the digital demodulation circuit 22, main channel data undergoes error detection, error correction, and interpolation processing in an error correction circuit 25. Further, the sub-coding signal is subjected to error detection and error correction processing in the decoder 33.

The output of the error correction circuit 25 is supplied to a demultiplexer 26 and divided into two child channels.

Each channel is passed through a D/'A filter 27.28 and a low-pass filter 29.30, and output terminal 31.3.
2, the reproduced audio signals of each channel appear.

Further, P channel and Q channel data of the sub-coding signal obtained from the decoder 33 is supplied to a system control 34 by a microcomputer and used for operations such as 9-head selection and random music selection. The time code included in the Q channel is supplied to the display section 35 and displayed.

In addition, the display data included in the R channel to W channel is converted to analog by the D/'A converter 36.
n, is taken out to the output terminal 38 via the low-pass filter 37. This display signal is supplied to a CRT display. Furthermore, audio data such as commentary on songs included in R channel to W channel is D7'
, a converter 39 and a low-pass filter 40, the signal is taken out to an output terminal 41, and is supplied to a speaker via a low frequency amplifier (not shown).

Encoder 13 for R channel to W channel G
is equipped with an error correction encoder shown in FIG.

The error correction enhancer is shown by the dashed line.

Q Paris 11 of the (4,2) Reed-Solomon code mentioned above
a generator 51, the aforementioned (24,20) Reed-Solomon code P parity generator 52, and an interleave circuit 53.
It is composed of. This error correction encoder has S 24 n +324]1-1-
A total of 18 symbols from 1*524)1→4 to 524n+x9 are input.

Two symbols S2'4n+524rl+t are fed to the Qpari 11 generator 51+Qz+n+z, Q2
4n+3/g1 note symbols are generated. The 20 symbols including this Q parity are sent to the P parity generator 5.
Enter 24.

Four parity symbols are generated. The 24 symbols outputted from this P-no-rarity generator 52 are supplied to an interleaving circuit 53.

The interleave circuit 53 is composed of a RAM and its address controller, and generates output data in which a predetermined amount of delay is added to each symbol of input data by controlling write addresses and read addresses. In FIG. 12, the means for providing a predetermined amount of delay to each symbol is shown as a plurality of delay elements for ease of understanding. These delay elements include delay elements 61°, 71 .
81 and a delay element 62 for providing a delay amount of 2 backs,
Delay elements 63, 73 .72, 73 .
83, delay elements 64, 74.84 with a delay amount of 4 packs, delay elements 65, 75.85 with a delay amount of 5 packs, delay elements 66, 76, 86 with a delay amount of 6 packs, and delay elements 66, 76, 86 with a delay amount of 7 packs. Delay elements 67, 77, and 87 are used. Also.

For symbols without inserted delay elements.

The amount of delay is 0. In this way, three sets of eight delay amounts from 0 to 7 packs are provided.

This interleaving circuit 53 performs interleaving as shown in FIG. 8 consecutive input data series
Packs of n and output data sequences of the same length are shown in parallel in FIG. Focusing on the first puncture (indicated by the shaded area) of the input data series, the 24 symbols in this pack are distributed at positions 8 or 9 symbols apart in the output data series. If the output data series is divided equally at intervals of 8 symbols,
Three symbols of the pack of interest are placed as the first symbols of each set of eight symbols from the first to the third. As the second symbol in each set of 8 symbols from 4th to 6th.

Three symbols from the above pack are placed.

Thereafter, in the same way, the three symbols of the pack are arranged at positions shifted by every third Qth symbol in the set of eight symbols. Therefore, the three sets Q of the last eight symbols in the output data series shown in FIG.
As the second symbol, the three symbols of the second hack are dealt. Among the 24 symbols consisting of 3 of this set of 8 symbols, the symbols of the pack are arranged at a distance of 8 symbols each. Furthermore, at the boundary between the three sets of eight symbols, there is a distance of nine symbols because there is a seat of the ■ symbol.

Also, in a set of 8 symbols, symbols from multiple packs with timings later than the above pack are interleaved in positions that occur before the position of the symbol of the above pack. Ru. Furthermore, in the set of 8 symbols, at the position after the position of the symbol of the pack, symbols of a plurality of packs whose timing is before the puncture are arranged in an interleaved manner similar to the puncture. There is.

When error conditions in the reproduced subcoding signal of a compact disc are measured, burst errors of 4 symbols or more rarely occur. therefore.

(24, 20) By recording the 24 symbols included in the same E column of the Reed-Solomon code in a distributed manner as described above, two or more symbols become error symbols, and error correction is performed. This can be effectively prevented from becoming impossible.

In addition, as shown in FIG. 12, the interleave circuit 5
3 is the distance between commands, instructions, and Q-parity symbols included in the same pack,
The structure is such that interleaving is performed to make the symbol larger than other symbols. Therefore, as shown in FIG. 12, the input symbol supply lines to each delay element are not all parallel, but the interleave circuit 53 includes six diagonal supply lines.

To clarify the characteristics of this interleaving.

Assuming that all input symbol supply lines are parallel, 1
) What is the correspondence between the 24 symbols of Gutsuku and the data positions in the output series after interleaving?

The result is as shown in FIG. In FIG. 14 and FIG. 15, which will be explained next, the time width of one click of input data is expanded to eight times the original time width.

As shown in FIG. 14, the first eight symbols of the input symbols 824n+824n+1+024n+2
+ Q24n+3...524fi+7 is o+1 pack and 2 nogtsuku respectively.

3pack...0 that gives a delay of 7backs
Therefore, these eight symbols have symbol numbers (-24) in the output data series.

(-24X2), (-24X3)... (-24
×7). Also for the next eight symbols 524n+8...824n+15 after the input symbol,
Respectively.

0.1 puncture...A delay amount of 7 punctures is given.

Furthermore, the next 8 symbols S24□+16...S
24□10. 3 (also given a similar amount of delay. As a result of such interleaving, the distance of the first four symbols of the pack from each other is 9 equal to 24 symbols.

In one embodiment of the invention, symbol 824°+1 is applied to delay element 82&, symbol 524n is applied to delay element 61, symbol Q24□+2 is applied to delay element 65G, and symbol S2. l], l+
5 is supplied to the delay element 62, and symbol Q24n+3 is supplied to the delay element 87.
Interleave 117 supplies +23 to delay element 63
1 Route 53 is used. Therefore, the positions of the pairs of symbols mentioned above are swapped, and the correspondence between the input data sequence and the interleaved data sequence is the first.
The result is shown in Figure 5. As is clear from FIG. 15, the distances between the first four symbols of the bank are linear.

524n and S24 n+1 distance 265 symbols 5
Distance between 24Y1+1 and Q24n+2: 58 symbols Distance between Q24n+2 and Q24n+3: 65 symbols In this way, the distance between the four symbols can be expanded by more than twice G compared to 25 symbols.

It is possible to further improve the error correction ability for burst errors occurring in reproduced data.

FIG. 16 shows (1) an error correction decoder for R channels to W channels provided in the decoder 33 for raw silk sub-coding signals;

a dinterleave circuit 91 supplied with 24 symbols of one step of the reproduced sub-coding signal;
P1 to which the output of this dinterleave circuit 91 is supplied
The first four syns and pols of the output of the decoder 92 and the P1 decoder 92 are supplied (4.2). The Reed-Solomon code Q decoder 93 and the Q decoder 93 perform error correction. The above four symbols and P1 decoder 92
A P2 decoder 94 of a Reed-Solomon code is supplied with a pack of 20 symbols from (24.20).

P, the decoder 92, regarding 24 symbols of one back,
Detects the size of the error and calculates the error location in each case of 1-symbol error and 2-symbol error, and creates a flag (called P flag) that indicates stiffness information.
is supplied to the Q decoder 93G. Q decoder 93 performs error correction using this P flag. The Q decoder 93 performs error correction and calculates the number of error symbols (
0)), and this Q flag is supplied to the P2 decoder 94, and the P2
The number of error symbols (including 0) generated in the decoder 94 and the flag indicating the error location and the Q flag are used for error correction in the P2 decoder 94.

The input data to the dinterleave circuit 91 is the first
This is output data of the interleave circuit 53 in FIG. 2. The amount of delay given by this interleaving circuit 53 is canceled, and interleaving is performed such that each symbol has an equal delay of 7 backs. Actually, this dinterleaving is performed by controlling the write address and read address of RA and M. In Figure 16.

Dinterleave circuit 91 is shown as a configuration in which a delay element having a predetermined amount of delay is arranged on the transmission line of each symbol. Seven packs of delay elements are inserted into each transmission line of the symbol whose delay amount is 0 in the interleave circuit 53. In addition, the transmission lines of symbols whose delay amounts in the interleaving circuit 53 are 1 pack, 2 packs, 3 packs, 4 packs, 5 packs, and 6 packs are 6 packs, 5 packs, 4 packs, 3 packs, and 2 packs, respectively. , 1 pack of delay elements are inserted, and no delay element is inserted into the transmission line of the symbol for which the delay amount in the interleave circuit 53 is 7 packs.

1) 1 decoder 92 described above. The error correction operations performed by the Q decoder 93 and the P2 decoder 94 will be explained in more detail.

The flow chart shown in the 17th [3AG] shows the P1 decoder 9
The flowchart shown in FIG. 17B shows the decoding process carried out in the Q decoder 93, and the flowchart shown in FIG. Basically, the Q decoder 93 can correct one symbol error out of four symbols, and the +P2 decoder 94 can correct one and two symbol errors out of 24 symbols. It is. In the P1 decoder 92, first, the syndrome 5rO1
"rl 1Sr2'+ generation of s-work 3 (step 101
) is done. This calculation converts the symbol location to l
Then, it is expressed by a linear equation. Note that the calculations are all performed using (mad, 2).

A sro:ΣS] 1=0 These four syndromes Srl to Sr3 are used to calculate the error magnitude and error location. In order to easily and quickly perform this operation, constants A, B', and C, such as a 9th degree equation, are calculated (step 102).
).

A=SroSr2+S1"I B=Sr] gr2+SroSr
3C=SrISr3+Sr2 Next, the above syndrome and constants are used to determine the size of the error (step 103). By this determination and the calculation of the error location, which will be described later, a flag P indicating the magnitude and location of the error is formed. (Sro #0, S, 3'i: O, A'E
O', B'i'O, CN3) is established to determine whether there is a two-symbol error (step 104).

If there is no 2-symbol error, it is determined whether there is an error (step 105).

(91-o-”0.3r3=0. A,=B=C=0
), it is determined that there is no error.

If there is no error, it is determined whether there is a one-symbol error (step 106).

(Sro':O, Sra"to, A==B=(:'=
:Q), it is a one-symbol error.

If it is not a single symbol error, it is an error of three or more symbols.

In the case of a two-number error, an error location calculation (step 107) is performed. Error location 1+J can be found as follows. In the case of a one-symbol error, the calculation of the error location (step 108) is completed.

Error location 1 is determined by n. In this way +Pl decoder 9
The P flag obtained in step 2 is transmitted to the next stage Q decoder 93G (step 109).

■ Error locations of symbol errors and two-symbol errors are stored in memory (steps 110 and 112).
), a flag indicating no error is generated (step 111).

In the Q decoder 93, as shown in FIG. 17BG.

First, the syndrome 517o is manifested in the generation of Sr+ (step 121). Next, using these syndromes, the size of the error is determined (step 122). It is determined whether it is a 0-1 symbol error (step 12'3
) is performed, and if there is no one symbol error, it is determined whether there is no error (i.e., 5rO-0, 5r1=0) (
Step 124) is performed. In the case of a one symbol error, an error location calculation (step 125) is made. Error location 1 is found by . It is determined whether the error location 1 obtained in this way is included in the range (0≦1≦3) (step 126).

If error location 1 is included in this range,
The P flag is not checked (step 128).
It is checked whether the flag matches the error location (step 129).

When this matches, error correction (step 130)
will be done. Error correction is performed by the calculation (J+Sro2S□) when considering the reproduced symbol. if,
If the obtained error location 1 does not fall within the range mentioned above, or if the P flag and the error location do not match, this 24-symbol pack is considered an illegal pack and all symbols are Gastera nru (step 127). In other words, all symbols in the pack when a command or instruction is an error are invalidated.

In addition, a Q flag indicating a case where one symbol error has been corrected without an error is transmitted to the P decoder 94 (step 131), and a Q flag indicating a case where there is an error of two or more symbols is transmitted to the P2 decoder 94. 94 (step 132).

In the P2 decoder 94, as shown in FIG. 17C.

First, Jintro Tmus sro I sr, , s, 21
Sr3 is calculated in the same manner as in step 101 described above (step 141). These four syndromes S. ~sr
3 is used to calculate the error magnitude and error location. In order to perform this calculation easily and at high speed, constants A and B are
, C are calculated (step 142).

Next, the magnitude of the error is determined (step 143) using the syndrome and constants described above. (Sro
\O, Sr3,)Q, ANO,MO,c':O)
It is determined whether there is a two-symbol error (step 144) by checking whether the following holds true. If it is not an impossible 02-symbol error, it is determined whether there is no error (step 145).

(s, -0=:Q, 5p3=O, A=B=C=O
) is true, it is determined that there is no error.

If there is no error, it is determined whether there is a one symbol error (step 146).

(srO"to, Sr3'IEO, A=B=C=O)
If it holds true, it is a ■symbol error. If it is not a single symbol error, it is an error of three or more symbols, so processing is performed as a pad pack (incorrect pack) (step 147). All symbols in pad packs are discarded, just like in illegal packs.

In the case of 2 symbol errors, the error location calculation (step 148) is performed with 0 error locations 1. J is obtained in the same manner as in step 77'107 above.〇This error location 1. Check whether j is correct or not using Q flag 2 (step 149)
. The Q flag is examined to indicate either no error or an error of more than one symbol (step 150).
.

When the Q flag indicates no error.

Location check (step 151) will be performed.

If (4≦1<J≦23) holds true.

Since the error location is correct, the two-symbol error is corrected (step 153). If the above-mentioned relationship does not hold, this is inconsistent with the error detection result of the Q decoder 93, so the pack is processed as an illegal pack (step 154).

Therefore, one symbol at any error location from 0 to 3 will be corrected by the Q decoder 93, and two symbols from error locations included from 4 to 23 will be corrected by the P2 decoder 94. , it is possible to correct errors in three symbols in one pack.

If the Q flag indicates an error of two or more symbols, the location check (step 152) is interrupted. This rotation check is (0≦1〈J≦
3) is established, and if this relationship is established, the two-symbol error is corrected (step 153).
will be done. If this relationship does not hold, the pack is processed as an illegal pack.

2 symbol error correction (step 153).

This is a process of determining the error pattern "e y + e J'f" and adding this to the reproduced symbol. That is, S1 + e y = 5i Sj + ej = Sj If the result of error detection in the P2 decoder 94 is no error, A check is made (step 155) to see if the Q flag indicates no errors. If the Q flag is error free.

This pack is judged to contain no error symbols. For this case, when the Q flag indicates the existence of an error of 2 or more symbols.

This is because it is inconsistent with the decoding result of the P2 decoder 94.

The pack is treated as an illegal pack.

If the result of error detection in P2 decoder 94 is one symbol error, error location 1 is calculated (step 156). This is just a calculation. Next, the Q flag is checked. If the Q flag is error-free, a location check (step 158) is performed.

If (4≦1≦23) holds, there will be no inconsistency with the result of Q decoding, so error correction of (s1+5ro=Si) (step 159) will be delayed. If the above relationship does not hold, the pack is processed as an illegal pack.

If the result of the P2 decoder 94 is one symbol error and the Q flag indicates an error of two or more symbols.

Since this cannot occur in the first place, the pack is treated as an illegal bank.

If three or more symbol errors are detected as a result of the further P2 decoding, the pack is processed as a pad pack (step 147). As above,
7% '5 without error correction decoder processing.

"Other Embodiments" In the error correction decoder, 24 symbols in one bag are insufficiently supplied, and in the decoder 92, correction of symbol errors or 2 symbol errors is performed only when the number of error locations sought is from 4 to 23. You may also do this.

In addition, in a configuration in which the P1 decoder 92 only detects the error magnitude and error location as in the above-described embodiment, or in a configuration in which the P1 decoder 92 corrects error symbols at error locations (4 to 23), the P2 decoder 92 94 may be omitted.

"Application Example" Unlike the above embodiment, other codes such as adjacent codes may be used as the first and second error correction codes. Furthermore, the second code may be a hood (CRC code, simple parity) that only has an error detection function. Furthermore, a bit-by-bit error correction code such as a BCH code may be used.

"Effect of the invention" According to this invention, error correction encoding is performed (
n+k 10m+1) symbols.

Since unique error correction encoding is performed for (n 10k) symbols, + (n 10k + m+
1) Detect the error magnitude and error location for the symbols, and use this detection result to calculate '(n+
k) symbols can be checked for error correction. Therefore, it is possible to prevent the error correction operation of (n10k) symbols from being erroneous. It is possible to make the protection of high data more powerful.

[Brief explanation of drawings]

FIGS. 1 and 2 are route maps used to explain the data structure of a compact disc according to an embodiment of the present invention, and FIGS. 3 and 4 are route maps used to explain the sub-coding signal of a compact disc. , FIG. 5, FIG. 6, and FIG. 7 are route maps used to explain the font graphics mode using sub-coding signals, and FIGS. 8 and 9 are parity check matrices and error correction codes of an embodiment of the present invention. FIG. 10 is a block diagram showing the configuration of a recording thread according to an embodiment of the present invention. FIG. 11 is a block diagram showing the configuration of a reproduction system according to an embodiment of the present invention.
Fig. 2 is a block diagram showing the configuration of an error correction encoder in an embodiment of the present invention, Figs. 13, 14, and 15 are explanations of interleaving processing of the error correction encoder. FIG. 1 is a block diagram showing the configuration of an error correction decoder in an embodiment of the present invention. FIG. 17 is a flowchart for explaining the error correction loader. 10... Main channel error correction encoder, 12... Encoder for P channel and Q channel, 13... R channel ~ W
Encoder for channels, 20... Input terminal to which compact disc playback signals are supplied, 25...
...Main channel error correction circuit, 33...
...Decoder for sub-coding signals. 51... Q parity generator, 52... P parity generator, 53... Interleave circuit, 9
1゛°°finter-1 knob circuit, 92...P
□Decoder, 93...Q decoder, 94...
P2 decoder. Agent Tadashi Sugiura TomoR5TUVW Figure 4 (Cero 7th) (Ri'Rough 4...knob mode) Figure 5 COLUMNol 23456-----363
7383956i COLUMNol 23456---36'373
839 Negative Figure 6 Figure 8

Claims (1)

[Claims] fl) n symbols (fl) having different types of information (
or bits (the same applies hereinafter) and m symbols when transmitting data as a unit. a first error correction code embedding process that generates all redundant codes of n symbols for the n symbols; Second error detection that generates a redundant code of one symbol for (n++m) symbols: + −)”
or an error correction code encoding process. (n-1-k
In an error correction device for data in units of + m+1) symbols. By supplying the above (n0 to 10m±1) symbols and performing at least error detection. a first decoder of the second error detection code or error correction code generating a flag signal indicating the number (including zero) of error symbols and the error location; a second degerator for the first error correction code, which is supplied with the (n+k) symbols passed through the first decoder and performs error correction using the flag signal; An error correction device comprising: (2) When transmitting data of n symbols and m symbols containing different types of information as a unit. a first error correction code encoding process for generating a redundant code of n symbols for the n m symbols; a second error correction hood encoding process for generating a one-symbol redundancy code for (n + k 10m) symbols; (n + k +
In an error correction device for data in units of m + E−) symbols. The (n 10k 10m + 1) symbols are supplied -gn, and the second and a first decoder for the error correction code. When the (n+k) symbols passed through the first decoder are supplied, a second flag signal indicating the number of error symbols (including 0) is generated, and the first and second
a second decoder for the first error correction code that performs error correction using the flag signal of
a third decoder for the second error correction code, which is supplied with m+1) symbols and performs error correction using the second flag signal; An error correction device comprising: (3) In the error correction device according to claim 1 or 2, the first decoder performs error detection on (10 m+1 to n+) symbols, and (
An error correction device characterized in that it performs error correction on m+1) symbols. (4) In the error correction device according to claim 1 or 2, the above (n+k + m + 1.)
The m symbols are data recorded as subchannels of a disc on which an information signal is recorded as a main channel, and the m symbols are: σ) data or audio data for display in the data of the subchannel, and the n symbols are control data of the subchannel.