JPS59167810A - Error correcting device - Google Patents

Abstract

PURPOSE:To attain the improvement of the error correcting capability and the prevention of the error correction in error by designing the device that the processing for error detection and error correction is applied to an important data together with other data in common and the processing of error correction and decoding is applied during the processing of the unique error detection error correction. CONSTITUTION:One stereo signal applied to an input 1 is synthesized with the other stereo signal at a multiplexer 9 via an LPF3, a sample-and-hold circuit 5, and an A/D converter 7. Further, the synthesized PCM signal obtained is encoded with an error correcting encoder 10 capable of error correction and applied to a multiplexer 11. An encoder 12 relating to channels P, Q of a subcoding signal and an encoder 13 relating to channels R-W are provided and these outputs are applied to a multiplexer 11. The output of the multiplexer 11 is applied to a digital modulation circuit 15 and modulated with 8-14 conversions. In this case, a frame synchronizing signal from a synchronizing signal is mixed, and the output is extracted at an output terminal 17. Thus, the error detecting capability is improved.

Description

[Detailed description of the invention] "Industrial application field" This invention provides a recording medium for digital information signals.

0 ``Background technology and its problems'' related to error correction devices applied when transmitting via transmission paths such as optical fibers Optical digital audio discs (referred to as compact discs) are composed of digital audio signals. For main channel and control.

Sub-channels consisting of data for display etc. are recorded on a spiral signal track. Error correction encoding processing is performed on each of the main channel and subchannel. The subchannels include P, Q, R, S,
Eight channels called T, U, V, and W are defined. Of these channels, the P channel and the Q channel are used for selecting a program when playing back a compact disc, and data for one display or audio data is inserted into the remaining six R-W channels. For example, the composer of the music recorded on the main channel.

Data for explaining the performer and the like is recorded on six R-W channels.

This subchannel data includes control data such as indicating the type of data actually recorded and instructions for processing the subchannel data. This control data is necessary to correctly process the subchannel display or audio data, and its importance is higher than that of the subchannel display or audio data. It is necessary to prevent this from being included as much as possible. For example, if an error occurs in even one bit of the control data, the data for displaying 9 will be erroneously processed as audio data, resulting in an abnormal sound being generated from the speaker.

The type of data to be transmitted is not limited to the data of the subchannels of this compact disc, and may not be the same. For example, in a videotex system that uses existing telephone lines and optical transmission lines and uses a home television receiver as a display device.

To transmit graphic information, console commands are sometimes used as special commands in addition to commands representing basic elements.

``Object of the invention'' This invention is applicable to cases where different types of data are included in data transmitted through the same transmission path.

For more important data, error detection or error correction processing is performed in common with other data, and error correction decoding processing is performed when unique error detection or error correction processing is performed. 0 ``Summary of the Invention'' This invention proposes an error correction device that performs error correction when data of n symbols (or bits, the same shall apply hereinafter) of different types and m symbols is transmitted as a unit.

a first error detection code or error correction code encoding process that generates a redundant code of n symbols for n symbols;

a second error correction code encoding process that generates a one-symbol redundancy code for (, n + m) symbols;

(nf k
In an error correction device for data in units of 10 m +1 symbols.

a first decoder provided with (n + k) symbols and at least performing error detection to generate a first flag signal indicative of an error condition;

The (n + k) symbols corrected by the first decoder and the received (m, +1) symbols are provided, and by performing error detection, a second flag signal indicating an error condition is generated. and a second decoder that performs error correction using the first flag signal and the second flag signal.

Embodiment An embodiment of the present invention is an application of the present invention to an error correction device for subchannel data of a compact disc.

The data structure of the signal recorded on the compact disc will be explained with reference to Figures 1 and 2. Figure 1 shows the data stream recorded on the compact disc. One frame is made up of bits, and a frame synchronization pulse F8 with a specific bit pattern is added to the beginning of each frame.After the 07-rem synchronization pulse XF8, a 3-bit DC component suppression pitch (RB) is provided. Furthermore, after that, data bits DB numbered 0 to 32, each having 14 bits, and a DC component suppression bit RB of 3 bits are provided alternately. These are called subcoding signals or user bits,
It is used to control disc playback, display related information, etc. 1 to 12. The 17th to 28th data bits DB are allocated to main channel audio data.

The remaining 13th to 16th and 29th to 32nd data bits DB are allocated to parity data of the error correction code of the main channel. Each data bit DB has 8 bits when recording.
8-bit data is converted to 14-bit data by -14 conversion.

The above-mentioned 98 frames of the digital signal are called one block, and various types of processing are performed in units of this one block.

Figure 2 shows each data bit p except for the DC component suppression bit.
-B is 8 bits, and the sub-coding signal PNW of frames 00 and 1 indicates a state in which one block (98 frames) is arranged in parallel.

A sync pattern, which is a predetermined bit pattern, is formed. Also, regarding the Q channel.

A CRC code for error detection is inserted into 16 frames on the terminal side among the 98 frames.

The P channel is a flag indicating pause and music, and has a low level for music, a high level for pause, and a 2 Hz pulse in the lead-out section. Therefore, by detecting and counting the P channels, it becomes possible to select and reproduce designated music. The Q channel can perform the same type of control in a more complex manner.9For example, the Q channel information can be imported into a microcomputer installed in a disc playback device, and the playback of other music can be immediately started even in the middle of music playback. Random music selections such as Other than this, the R channel or channel.

Lyricists and composers of the songs recorded on the disc.

It is used to display explanations, poems, etc., and to provide audio explanations.

Also, data of 967 frames of this 1 block excluding the sync pattern, P channel, and Q channel is regarded as a packet. As shown in Figure 3A, this (6
The X96) bit packet is further divided into four packs of 24 symbols each. The first symbol of each pack is a command, the next 19 symbols are data, and the remaining four symbols are the parity of the error correction code of each pack. This command is a 6-bit command consisting of a 3-bit mode and a 3-bit item, as shown in FIG. 3B.

The information represented by the three bits of the mode is determined as follows.

(000): Zero mode (001)! Graphic mode (010): Still image mode (011)! The three bits of the sound mode item represent more detailed information on each of the above-mentioned operation modes. Zero mode is a case where no information is recorded for the RNW channel of the subcoding signal.

That is, in this zero mode, all bits in the pack are set to 0, including the 6 bits for mode and item, as shown in FIG.

In addition, in the graphic mode where the 3 bits of the mode are (001), as shown in FIG.

Data for each pack is arranged. When performing a 7-ont graphic such as 2 characters and 9 sentences in this graphic mode, the 3 bits of the item are set to (001) and the data of the entire display area of the display device is controlled in the case of a full graphic. The 3 bits are (010). The second symbol of each pack in this graphics mode breaks the instruction. This instruction provides necessary control commands in the operating mode defined by the fant consisting of modes and items.

The two symbols of this graphic mode command and instruction are subjected to error correction encoding processing, and the parity of the resulting two symbols is added. Furthermore, 16 symbols in the pack are used as a data area. and.

A total of 20 symbols in the pack are subjected to error correction encoding processing, and parity b of the resulting four symbols is added.

Even in still image mode or sound mode.

When predetermined commands and instructions are used, the error correction encoding process is carried out in the same way as described above. The area where the screen is displayed is called the screen area, and the other area is called the border area. In addition, as the 9 display device, the line display shown in 511A and the line display shown in 5B
Use one of the CRT displays shown in the figure below.

The screen area of the line display is 2, 0 and 1.
The font position is specified by 40 row addresses (ROW) and 40 column addresses (COLUMN) from 0 to 39, and each font is defined by pack data. It consists of 6×12) pixels. In case of alphabetical display, (6
Although 12) pixels is sufficient, in the case of displaying one Japanese character (particularly kanji), one character is displayed using (24×24) pixels.

Also, the screen area of a CRT display.

It is said to be large and has eight line displays lined up.

Therefore, the position is specified by a row address of 0 to 15 and a column address of 0 to 39.

The 7-ont foreground color or the background color displayed on the screen area of the above-mentioned line display or CRT display is determined by three bits corresponding to each of the R (red), G (green), and B (blue) components. It is specified.

FIG. 6 is a T color table showing colors expressed in 3 bits.

Font graphics instructions (R8TU
VW (6 bits) is defined as 9th order.

1 = 000001 = Preset screen 2 = 000
010: Preset Voter 4=000100 Nilight font (without flash) 5=000101 Nilight font (with flash) s=ooiooo Suffix 4-lef the specified line on the Niline display.

16=010000: Move a predetermined row on a CRT display, fill the space left 17=010001: Move a predetermined column on a CRT display, move a filler up 18=010011 On a CRT display, move a filler left 19=010011: Move a predetermined column on a CRT display.
Light 20 = 010100: Scroll amplifier on CRTf display With the above instructions, in the case of a preset screen or preset border (instruction 1 or 2), the data area consisting of the 4th symbol to the 199th symbol in one pack is: As shown in FIG. 7A, three bits (RAT) in the fourth symbol are used as data (coLOR) specifying a color, and all bits other than n are zero. Preset screen (instruction 1) presets the screen area of the line display and CRT display to the specified color.0 Preset border (instruction 2) presets the border area of the line display and CRT display to the specified color. .

In the case of write 7 ont (instruction 4), the data area in the pack is formatted as shown in FIG. 7B. 3 bits (COLO)i;i.

Specify the background color in 7 onts, and (C'0L1) is.

Specify the foreground color. RL and COLUMN-L.

This is a 7-ont address on the line display. R
OW-C and COLUMN-C are 7-ont addresses on the CRT display. The (6x12) bits of the pack data area are the font pixel data,
The one indicated by y is the top pixel on the left side of the font (7 on), and the one indicated by 2 is the bottom pixel on the right side of the font. When the pixel is 0, it is used as the background color, and when it is 1, the foreground color is interrupted. Furthermore, in the case of light font (with flash) (instruction 5), the foreground color and background color are alternately switched.

Also, instruction 8 and instruction 1
6 is the θ instruction 17 which shifts the specified row by one address to the left.

0 Moves the specified column to the right by one address.
Instruction 18 shifts all 7 onts on the CRT display one address to the left.
Instruction 19 is.

Shift all fonts on the CRT display one address to the right. Instruction 20 is
Shift all 7 onts on the CRT display up one address. Corresponding to these instructions is one figure not shown.

The data area of the pack is in a predetermined format.

The error correction code regarding the above-mentioned subcoding signal will be explained. A (24°20) Reed-Solomon code is used as an error correction code for the (6×24) bit pack. This Reed-Solomon code is GF
(2') (where GF is a Galois field), and the polynomial is (P (X) = X +1). The parity check matrix Hp of this Reed-Solomon code is the eighth
The one shown in the figure is used. Primordial light a on GF(2')
is for a=(000010).

In addition, one pack of reproduced data is expressed as a reproduced data matrix ゎT, as shown in Fig. 8. The suffix attached to each of the 24 symbols indicates the symbol number P of the sub-coding signal, and n in this suffix means the pack number. 0824111 is a command and +824n+1 is an instruction. *Q
24n+2 and 24rl+3 are parity symbols for this command and instruction.
P24m+201 P24n+21 IP24Z1+
22 P24n + 23 C is the parity symbol of the pack as mentioned above. What is the parity of these four symbols?

(Hp-Vp=Q).

A (4,2) Reed-Solomon code is used as an error correction code for commands and instructions. This Reed-Solomon code has a polynomial (P (X) = X'x+1) on GF(2). The parity check matrix Hq and the reproduced data matrix ■9 are shown in FIG. The primitive light a on GF (2') is a=(000010). Parity symbols Q24m+2 and Q2
4n+3 satisfies (Hq-Vq=O). One example of this is (n = 2) (k
= 2) (m=16) (1=4).

A Reed-Solomon code containing four P parity symbols is capable of correcting one and two symbol errors and detecting three or more symbol errors. Also, 2
A Reed-Solomon code containing three Q symbols is capable of correcting one symbol error and detecting two or more symbol errors.

FIG. 10 shows the basic configuration for forming data to be recorded on a compact disc. In Figure 10,
1 and 2 indicate input terminals to which two-channel audio signals such as stereo are supplied from a source such as a tape recorder. The audio signal of each channel is filtered through low-pass filters 3 and 4 [through sample and hold circuits 5 and 6].
Further, one sample is converted into 16 bits by A/D converters 7 and 8. This two-channel audio PCM signal is converted into a one-channel signal by a multiplexer 9.

The signal is supplied to an error correction encoder 10.

In the error correction encoder 10, the audio PCM signal is subjected to cross-interleave processing to perform error-correctable encoding using a Reed-Solomon code. The p-interleap process rearranges the order of data so that each symbol is included in two different error correction code sequences.

The output of this error correction encoder 10 is supplied to a multiplexer 11.

Further, an encoder 12 for the P channel and the Q channel of the subcoding signal and an encoder 13 for the R channel to W channel are provided, and their outputs are combined by a multiplexer 14 and supplied to the multiplexer 11. The output of the multiplexer 11 is supplied to a digital modulation circuit 15 and undergoes (8→14) conversion modulation. In this case, the frame sync from the synchronization signal generation circuit 16 is mixed and taken out to the output terminal 1T. Encoder 12 for the P channel and Q channel encodes a 16-bit CRC for the Q channel.
It is configured to add a code.

The encoder 13 for R channel to W channel performs error correction encoding using Reed-Solomon code and interleaving. Sample hold circuit 5 * 61 A/D converter T, 8. Clock pulses and timing signals generated by the timing generation circuit 18 are supplied to each circuit such as the multiplexer 9, 11, 14, etc. 19 is an oscillator for generating a master clock.

FIG. 11 shows the configuration of a reproduction system for processing a reproduction signal of a compact disc, and a signal optically reproduced from the compact disc is supplied to an input terminal 20.

This reproduced signal is passed through the waveform shaping circuit 21 to the digital demodulation circuit 22. Clock regeneration circuit 23 and synchronization detection circuit 2
4. Clock regeneration circuit 23 with PLL configuration
A bit clock synchronized with the reproduced data is extracted. Further, the synchronization detection circuit 24 is configured to detect frame sync and generate a timing signal synchronized with reproduction data, and supplies a predetermined timing signal to each circuit of the reproduction yarn.

Among the outputs of the digital demodulation circuit 22, main channel data undergoes error detection, error correction, and interpolation processing in an error correction circuit 25. Further, the sub-coding signal is subjected to error detection and error correction processing in the decoder 33.

The output of the error correction circuit 25 is supplied to a demultiplexer 26 and divided into two channels.

For each channel, the D/A connector (-27.28 and 4-bass filter 29.30 are passed through, and the output terminal 31.3
In addition, the data of the P channel and Q channel of the sub-coding signal obtained from the decoder 33 is supplied to the system control 34 by a microcomputer, and the playback audio signal of each channel appears at 2.0. The time code included in the OQ channel used to perform the operation is supplied to the display section 35 and displayed.

In addition, the display data included in the R channel to W channel is converted into analog by the D/A converter 36,
The signal is taken out to an output terminal 38 via a low-pass filter 37. This display signal is.

C'RT display. Furthermore, audio data such as song commentary included in the R channel to W channel is taken out to an output terminal 41 via a D/A converter 39 and a p-pass filter 40, and is sent to a low frequency amplifier (not shown). is supplied to the speaker via the

The encoder 13 for the R channel to W channel includes a T error correction encoder shown in FIG.

The error correction encoder is shown by the dashed line.

This error correction system is composed of the above-mentioned (4,2) Reed-Solomon code Q parity generator 51, the above-mentioned (24,20) Reed-Solomon code P parity generator 52, and an interleave circuit 53. The encoder has
n@th pack's 82jn +524n+1+ 524
A total of 18 symbols from zt+4 to 524n+19 are input.

Two symbols 524n+Et24fi+t are fed to the Q parity generator 51+Qz4n+2+024
The 20 symbols including the Q parity are input to the P parity generator 52, which generates n+s parity symbols.

Four parity symbols are generated. 0 interleaving circuit 53 to which 24 symbols outputted from this P nozarity generator 52 are supplied to an interleaving circuit 53.
consists of a RAM and its address controller,
By controlling the write address and read address, output data with a predetermined amount of delay added to each symbol of input data is generated. In FIG. 12, the means for providing a predetermined amount of delay to each symbol is shown as a plurality of delay elements for ease of understanding. These delay elements include delay elements 61, 71.81 for providing a delay amount of 1 pack (24 symbols), delay elements 62, 72.82 for providing a delay amount of 2 packs, and delay elements 62, 72, 82 for providing a delay amount of 3 packs. Delay elements 63, 73, 83, delay elements 64, 74, 84 with a delay amount of 4 packs, delay elements 65, 75, 85 with a delay amount of 5 packs, and delay elements 6 with a delay amount of 6 packs.
Delay element 67.7 with delay amount of 6.76.86 and 7 packs
7.87 is used. Also.

For symbols without inserted delay elements.

The amount of delay is 0. In this way, three sets of eight delay amounts from 0 to 7 packs are provided.

This interleaving circuit 53 performs interleaving as shown in FIG. 8 consecutive input data series
packs and output data sequences of the same length are shown in parallel in FIG. Focusing on the first pack (indicated by the shaded area) of the input data sequence, the 24 symbols in this pack are distributed at positions 8 or 9 symbols apart in the output data sequence. If we divide the one-ta series equally at intervals of 8 symbols, we get
The three symbols of the pack that are being focused on as the symbols of the first application in each set of eight symbols from the first to the third check are selected six times. 2nd of each set of 8 symbols from 4th to 6th
As the second symbol.

Three symbols from the above pack are placed.

Thereafter, in the same way, the three symbols of the pack are arranged at positions shifted by one symbol for every three symbols in the set of eight symbols. Therefore, in the three sets of the last eight symbols in the output data series shown in FIG. 13, the three hack symbols are arranged as the eighth symbol of each set. Among the 24 symbols consisting of 3 of this set of 8 symbols, the symbols of the pack are arranged in pressure parts of 8 symbols each. In addition, at the boundary of three sets of 8 symbols, there is a shift of 1 symbol, so a distance of 9 symbols exists.◎ Also, in the set of 8 symbols, there is a gap that occurs before the position of the symbol in the pack above. In the same position as the above pack, symbols of a plurality of packs having timings later than the above pack are interleaved and arranged. Further, in the set of 8 symbols, at positions after the position of the above-mentioned nosic symbol, there are a plurality of nosick symbols '4?' whose timing is before the above-mentioned nosick. When we measure the error state in the reproduced sub-coding signal of the 0 compact disc, which is arranged in an interleaved manner in the same way as the above-mentioned back, we find that almost no burst errors of 4 or more symbols occur.

(24, 20) By recording the 24 symbols included in the same series of Reed-Solomon codes in a distributed manner as described above, two or more symbols become error symbols, making error correction impossible. can be effectively prevented.

Further, as shown in the 12th FA, the interleaving circuit 5
3 is the distance between commands and instructions included in the same bag and their Q parity symbols,
The structure is such that interleaving is performed such that T is larger than that of other symbols. For this reason, as shown in FIG. 12, the input symbol supply lines to each delay element are not all parallel, but the interleaving circuit 53 includes six diagonal supply lines.

To clarify the characteristics of this interleaving.

Assuming that all input symbol supply lines are parallel, 1
What is the correspondence between the 24 symbols of the pack and the data positions in the output series after interleaving?

In this FIG. 14 and in FIG. 15, which will be described next, the time width of one pack of input data is expanded to eight times the original time width.

As shown in FIG. 14, the first eight symbols of the input symbols 824n + 524n+1, Q24n+2
+ Q24n+4...824fi+7 are 0.1 pack and 2 pack, respectively.

33 packs... A delay amount of 7 packs is given.

Therefore, these eight symbols have symbol numbers (-24) in the output data series.

(-24X2), (-24X3)... (-24
×7). The next eight symbols 5ztn+s...524n+15 after the input symbol also have
Respectively.

A delay amount of 0.1 pack...7 pack is given.

Furthermore, the next eight symbols S24. n+16...
A similar amount of delay is given to 524n+23. As a result of such interleaving, the first four symbols of the back are separated from each other by 5 equal to 24 symbols. In one embodiment of the invention, symbol 524n+1 is fed to delay element 82 and symbol 524n+18 is delayed. The symbol Q24n++ is supplied to the delay element 61, the symbol Q24n++ is supplied to the delay element 65, and the symbol Q24n++ is supplied to the delay element 62, and the symbol Q2an++ is supplied to the delay element 87.
An interleave circuit 53 is used which supplies the symbol P24n+2B to the delay element 63 as well as the symbol P24n+2B.

Therefore, the positions of the bare symbols mentioned above are exchanged, and the correspondence relationship between the input data sequence and the interleaved data sequence becomes T shown in FIG. 15. As is clear from FIG. 15, the distances between the first four symbols of the pack are linear.

Distance between 824n and 824n+1 = 65 symbols Distance between 524n+1 and (h4n+2: 58 symbols Distance between 0.24n+2 and Q24n+3: 65 symbols In this way, the distance between the four symbols is 25
It can be enlarged more than twice as much as the symbol.

It is possible to further increase the error correction ability for burst errors occurring in reproduced data.

FIG. 16 shows an error correction decoder related to the R channel to W channel provided in the decoder 33 of the sub-coding signal of the reproduction system. The error correction decoder is shown by the broken line.

A dinterleave circuit 91 is supplied with 24 symbols of one pack of the reproduced sub-coding signal, and the first four symbols of the output of this dinterleave circuit 91 are supplied (4.2 ) Reed-Solomon code Q decoder 92.

One pack of symbols consisting of the above four symbols error-corrected by this Q decoder 92 and 20 symbols from the dinterleave circuit 91 is supplied (24,
20) P decoder 93 of Reed-Solomon code.

Number of error symbols from Q decoder 92 @ (including O)
The first 7 lags (referred to as Q flags) indicating is used for error correction in the P decoder 93.

The input data to the dinterleave circuit 91 is the first
This is output data of the interleave circuit 53 in FIG. 2. The amount of delay given by this interleaving circuit 53 is canceled, and interleaving is performed such that each symbol has an equal delay of 7 backs. Actually, this dinterleaving is performed by controlling the write address and read address of the RAM. In Figure 16.

The dinterleave circuit 91 is shown as having a configuration in which T delay elements having a predetermined amount of delay are arranged on the transmission line of each symbol. Seven packs of delay elements are inserted into each transmission line of the symbol whose delay amount is 0 in the interleave circuit 53. In addition, the transmission lines of symbols whose delay amounts are 1 back, 2 pack, 3 pack, 4 pack, 5 pack, and 6 pack in the interleave circuit 53 include 6 pack, 5 pack, 4 pack, 3 pack, 2 pack, and 6 pack, respectively. One pack of delay elements is inserted, and the delay element is not inserted into the transmission line of the symbol whose delay amount in the interleave circuit 53 is 7 packs.

70 in FIG. 17A and FIG. 17B regarding the error correction operation performed by the Q decoder 92 and P decoder 93 described above.
- Explanation will be given with reference to the chart and the table of FIG.

17A shows the decoding process performed by the Q decoder 92, and FIG. 17B shows the decoding process performed by the P decoder 93. Basically, the Q decoder 92 can correct one symbol error out of four symbols, and the P decoder 93 can correct HJ correction for one and two symbol errors out of 24 symbols. is possible. In the Q decoder 92,
First, generation of syndrome sro+SrH (step 1
01) is performed. This calculation is expressed by setting the symbol number to 1. In addition, all calculations are (mod, 2)
It is done in Next, the size of the error is determined using these syndromes (step 102).

It is determined whether there is a one-symbol error (step 103), and if it is not a one-symbol error, it is determined whether there is no error, that is, S, o=Q, sr, =Q)7> (step 104). In case of one symbol error, subtraction of error location (step 1
05) is done. The error location i is determined by 31 oir·matayu=i Sr6. It is determined whether the error location i obtained in this way is included in the range (0≦1≦3) (step 1106).

If error location 1 is included in this range,
Error correction (step 1o7) is made. For error correction, assume that the reproduced symbol is 81.

This is done by the calculation (81+Sr,=Si). if.

If the obtained error location 1 is not included in the above-mentioned range, the check of these 24 symbols is deemed to be illegal (it should not be an error T) and all symbols are discarded (step 10B). ,,In other words, if the command or instruction is an error, the number of symbols in the pack will be 0, all invalid ones will be interrupted.In addition, the Q flag indicating the case where one symbol error cannot be corrected without an error) is set by the P decoder. A Q flag indicating a case where there is an error of two or more symbols is transmitted to the P decoder 93 (step 110).

In the P decoder 93, as shown in FIG. 17B.

First, syndrome S r6 r sr, l s r
2'''' r3 is calculated as shown in the following equation (step 121).

3 sr0=　Σ　Sl 1=0 Using these four syndromes Sro to Sr3.

Operations are performed to determine the magnitude of the error and the location of the error. In order to perform this calculation easily and quickly, constants A, B, C, and D, such as linear expressions, are calculated (step 122).

A=SroSr2+5r1 B=SrIS, 2+5roSr3 C=SrlSr, +S, 2 Next, using the syndrome and constants described above, a determination of the magnitude of the error (step 123) is made. A second 7 lag is formed indicating the magnitude and location of the error. (Sr.

40, Sr3”qO, Ago, B?0. C'xi
It is determined whether there is a two-symbol error (step 124) by checking whether 'tR' holds true.

If it is not a two-symbol error, it is determined whether there is an error (step 125).

(Sr.=0,5r3=0.A=B-C=0) holds T
If so, it is determined that there is no error.

If there is no error, it is determined whether there is a one symbol error (step 126).

(sr, (o, sr, :!qQ, A=B=C=0
) holds, it is a one-symbol error. If it is not a single symbol error, it is an error of 3 or more symbols, so a pad pack (incorrect pack)
The processing as follows (step 127) is performed. The band pack symbol is the same as for the illegal pack.
Everything will be thrown away.

In the case of a two symbol error, an error location calculation (step 128) is made. Error location 1. j is obtained in a linear manner.

This error location 1. A check is made whether j is correct using the Q flag (step 129).
The OQ flag is examined to indicate either no error or an error of more than one symbol (step 130).
.

When the Q flag indicates no error.

A location check (step 131) is made.

If (4≦1<j≦23) holds true.

Since the error location is correct, the two-symbol error is corrected (step 133). If the above relationship does not hold, the pack is processed as an illegal back because it is inconsistent with the error detection result of the Q decoder 92 (step 134).

This corresponds to cases 3 and 7 in the table of FIG.

In this case 7, one symbol at any error location from 0 to 3 is corrected by the Q decoder 92, and two symbols at error locations from 4 to 23 are corrected by the P decoder 93. Therefore, errors in three symbols in one pack can be corrected.

A location check (step 132) is performed if the Q flag indicates an error of two or more symbols. This location check is (0≦1〈j≦3
) is established, and if this relationship is established, the two-symbol error is corrected (step 133). This n corresponds to case 11 in FIG. 18. Moreover, if this relationship is not established, it is processed as an illegal back.

2 symbol error correction (step 133).

This is a process of finding error patterns el and ej and adding them to the reproduced symbols. That is, Si+ei-81 rows+ej=Sj If the result of error detection in the P decoder 93 is that there is no error, a check is made to see if the Q7 lag indicates no errors (step 135). If the Q flag is error-free.

This pack is determined to contain no error symbols. This corresponds to Case 1 and Case 5 in the table of Figure 18. On the other hand, when the Q flag indicates the presence of an error of two or more symbols, this is inconsistent with the decoding result of the p decoder 93, so the pack is processed as an illegal pack. This corresponds to case 9 in the table of FIG.

If the result of error detection by the Pi encoder 93 is one symbol error, the error location 1 is multiplied by 1 (step 136), which is a calculation of 0 or so. Next, the Q flag is checked. If the Q flag is error-free, the location check (step 138) is skipped.

If (4≦1≦23) holds true, there is no contradiction with the result of Q decoding, and therefore error correction of +(8i+5ro=81) is performed (step 139). This is the first
This corresponds to Case 2 and Case 6 in Figure 8. If the above relationship does not hold, the pack is processed as an illegal pack.

If the result of the P decoder is a 1 symbol error and the Q flag indicates an error of 2 or more symbols, it is 2 original.

Since it cannot occur, the pack is treated as illegal. This is case 10 in Figure 18.
Applies to.

Furthermore, if errors of three or more symbols are not detected as a result of P decoding, the pack is processed as a pad pack (step 127).

Case 4 in Figure 18. This applies to Case 81 and Case 12.

"Application Example" Unlike the above embodiment, other codes such as adjacent codes may be used as the first and second error correction codes. Furthermore, the first code may be a code (C'f (C code, simple parity)) that only has an error detection function. Also good.

"Effect of the invention" According to this invention, error correction encoding (n
+10m+1) among the symbols.

For (n+k) symbols, if original error detection or error correction encoding is performed, first (
Generates a T flag indicating the number of error symbols for n 10k ) symbols.

Since this flag is used for error correction of the (n 10k 10m + 1) symbols in the next stage, it is possible to improve the error correction ability and prevent erroneous error correction. In addition, when error correction is performed on (n+k) symbols, it is possible to detect that the error correction is incorrect, and the information on the operation mode and control content in the sub-coding signal of the compact disc can be detected.
It is possible to improve the ability to detect errors in data with high importance, such as data such as data.

[Brief explanation of drawings]

1 and 2 are route maps used to explain the data structure of a compact disc according to an embodiment of the present invention, and FIGS. 3 and 4 are schematic P5j diagrams used to explain sub-coding signals of the compact disc. 5, 6 and 7 are route maps used to explain the font graphics mode using sub-coding signals, and FIGS. A T diagram showing the matrix, FIG. 10 is a block diagram showing the configuration of a recording system according to an embodiment of the present invention, FIG. 11 is a block diagram showing the configuration of a reproducing system according to an embodiment of the present invention, and FIG. 13, 14, and 15 are route diagrams used to explain the interleaving process of the error correction encoder, and FIG. A block diagram showing the configuration of an error correction decoder in one embodiment. FIGS. 17 and 18 are 70-chambers and tables used to explain the error correction decoder. 10. Main channel error correction encoder, 12 ... Encoder for P channel and Q channel, 13 ... Encoder for R channel to W channel, 20 ... Input terminal to which compact disc playback signal is supplied, 25.
・Mountain・Main channel error “J, positive circuit, 33・
...Decoder for sub-coding signals. 51...Q parity generator, 52...
P-nog quality occurrence N, 53...Interleave circuit, 91...Dinterleave circuit, 9
2...P decoder, 93...Q decoder. Agent Tadashi Sugiura Tomo R5TUVW (Gelafi Pukumode)

Claims (1)

[Claims] (1) n symbols (T) containing different types of information (
lt bits (the same applies hereafter) and m symbols when transmitting data as a unit. a first error detection code or error correction code encoding process for generating a redundancy code of n symbols for said n symbols; a second error correction code encoding process for generating a one symbol redundancy code for (n + k + m) symbols; In an error correction apparatus for data in units of (n+k 10 m + 1) symbols subjected to error correction encoding processing consisting of: The above-mentioned (n 10k) symbols are supplied, and at least the above-mentioned first process 2-detection code or error-correction code generates a first flag signal indicating an error state by performing error detection. 1 decoder. This first decoder supplies the corrected (n+k) symbols and the received (m+1') symbols and performs error detection. generating a second flag signal indicating an error condition; a second decoder for the second error correction code that performs error correction using the first flag signal and the second flag signal; An error correction device comprising: (2. In the error correction device according to claim 1, the first flag signal is p ('n + k
) symbols, the second flag signal is a signal indicating the number of error symbols (including 0), and the second flag signal is:
Regarding (n + k + m + 1) symbols. This signal indicates the number of error symbols (including 0) before error correction by the second decoder, and the first and second flag signals are compared, and the second flag signal is determined according to the result.
An error correction device characterized in that error correction processing of a decoder is controlled. (3) In the error correction device according to claim 1, the first flag signal is a signal indicating the number of error symbols (including 0) regarding (n+k) symbols; The flag signal No. 2 is a signal indicating the error location among the (nf + 1) symbols before error correction by the second decoder, and the first and second flag signals are collated, An error correction device characterized in that error correction processing of the second decoder is controlled according to the result. (4) In the error correction device according to claim 1, the (n 10k 1m +1) symbols are data recorded as a subchannel of a disc on which an information signal is recorded as a main channel. The error is characterized in that the m symbols are display data or audio data in the data of the subchannel, and the n symbols are control data of the subchannel. correction device.