JPH08147888A - Method and device for recording digital signal - Google Patents

Abstract

PURPOSE: To prevent occurrence of errors in digital signals by arranging a second- and a third error detecting and correcting code in the blocks at the ends of the recording areas respectively and arranging the digital signals in the blocks inside the above recording area and recording them. CONSTITUTION: One hundred and thirty nine blocks which record data record 188 byte video signal data 41 and 7 byte control information 42 related to the video signals 41 such as the kinds of signals, recording dates and editing information. Thus, by arranging the second error detecting and correcting codes and the third error detecting and correcting codes at the ends of the region respectively and the data in the central portion, the probability of generating erroneous data can be reduced to the drop-out which is liable to occur at the two ends of a tape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording method and apparatus for recording digital signals, and more particularly to a method and apparatus for recording digital compressed video signals.

[0002]

2. Description of the Related Art A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape by using a rotary head is disclosed in Japanese Patent Laid-Open No. 174496/1993.

[0003]

In such a digital signal recording apparatus, an error detection / correction code is doubly added in track units in order to correct a data error during reproduction. However, burst errors due to large dropouts that tend to occur at the tape end are not considered.

It is an object of the present invention to provide a digital signal recording method and apparatus in which a digital signal does not become an error even if a dropout occurs at the end of a tape.

[0005]

The above object is to divide a digital signal into a predetermined number of bytes, and add a sync signal, a control signal and a plurality of types of error detection and correction codes to the digital signal divided into the predetermined number of bytes. In a digital signal recording method and apparatus in which a digital signal recording area is formed by a predetermined number of blocks and recorded on a magnetic recording medium, the error detection and correction code has one series of error detection and correction codes. Constituting a first error detection / correction code composed of signals contained in a block, and second and third error detection / correction codes composed of signals of which one sequence of error detection / correction code is composed of a plurality of blocks And the second and third error detection and correction codes are arranged in blocks at both ends of the recording area, and the digital signal is placed inside the recording area. It can be achieved by recording disposed in blocks.

[0006]

Since the second and third error detection and correction codes are arranged in the blocks at the ends of the recording area and the digital signals are arranged and recorded in the blocks inside the recording area, the tape ends, that is, the recording. Even if the dropout occurs at the edge of the area, the probability that the digital signal becomes erroneous can be reduced.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a recording pattern of one track 82 on the tape 81 shown in FIG. Reference numeral 3 is an additional information recording area such as an audio signal, 7 is a data recording area for recording a digital compressed video signal, 12 is a subcode recording area for recording subcodes such as time information and program information, and 2, 6 and 11 are respectively Recording area preambles, 4, 8 and 13 are postambles 5 and 9 of the respective recording areas.
Is the gap between the respective recording areas, and 1 and 14 are the margins at the track ends. In this way, by providing the postamble, the preamble, and the gap in each recording area, it is possible to perform postrecording in each area independently. Of course, digital signals other than the digital compressed video signal and audio signal may be recorded in the recording areas 3 and 7.

FIG. 2 shows a block configuration of each area. Figure 2
(A) shows the additional information recording area 3 and the data recording area 7,
Is a block configuration of. 20 is a synchronization signal, 21 is ID information, 22 is a video signal or additional information data, and 23 is a first
Is a parity (C1 parity) for error detection and correction. The sync signal 20 is 2 bytes, the ID information 21 is 4 bytes, the data 22 is 195 bytes, the parity 23 is 9 bytes, and one block is 210 bytes. FIG. 2B is a block configuration of the subcode recording area 12. In the block of the subcode recording area, the sync signal 20 and the ID information 21 are the same as those in FIG. 2A, the data 22 is composed of 24 bytes and the parity 23 is composed of 5 bytes, and one block is shown in FIG. ) Is composed of 35 bytes which is 1/6 of the block. In this way, the number of bytes in one block is set to be an integer ratio, and the sync signal 11 and the ID information 12 are configured to be the same in all areas, so that a block for recording and a sync signal for recording are generated. , ID information detection and the like can be processed by the same circuit.

FIG. 3 shows the structure of the ID information 21. 31
Is an area code, 32 is a track address, 33 is a block address within one track, 34 is ID data, and 35 is a parity for detecting an error in the area code 31, the track address 32, the block address 33 and the ID data 34. . The area code 31 is for identifying each area. For example, in the data recording area 7, "0"
0 "," 10 "in the additional information recording area 3, and" 11 "in the sub-code recording area 12. Also, in the data recording area 7 and the like, plural kinds of codes, for example," 00 "and"".
01 ”may be assigned to identify different data such as variable speed reproduction data. The track address 32 is
An address for identifying the track, for example,
The address is changed in units of 1 track or 2 tracks. In this case, 64 or 128 tracks can be identified by a 6-bit address. The block address 33 is an address for identifying a block in each recording area. For example, 0 in the data recording area 7
˜157, 0 to 13 in the additional information recording area 3, and 0 to 17 in the subcode recording area 12.

The track address 32 is repeated, for example, in units of 12 or a multiple thereof in order to identify a third error detection / correction code which will be described later.

The C1 parity 23 is, for example, the data 22.
And the area code 31, track address 32, and block address in the ID information 21. As a result, it is possible to improve the detection capability of block addresses and the like during reproduction.

FIG. 4 shows a data structure of one track in the data recording area 7. The sync signal 20 and the ID information 21 are omitted. Data recording area 7 is 15
It is composed of 8 blocks, and the first 14 blocks are provided with the third error detection and correction code (C3 parity) 44 and the next 1
Data is recorded in 39 blocks and the second error detection and correction code (C2 parity) 43 is recorded in the last 5 blocks. The 139 block for recording data includes 188 bytes of video signal data 41 and 7 bytes of control information 4 related to the video signal 41 such as signal type, recording date and time, and editing information.
Record 2. In this way, by arranging the second error detection correction code and the third error detection correction code at both ends of the area and by arranging the data at the center, it is possible to prevent the data from being dropped out at both ends of the tape. It is possible to reduce the probability that is incorrect. Of course, the position of the second error detection and correction code and the position of the third error detection and correction code may be reversed.

The C2 parity 43 is 13 in track units.
5 bytes of C2 parity is added to 9 bytes of data and 14 bytes of C3 parity. Further, the C3 parity 44 divides the data of 139 blocks into two even-numbered blocks and odd-numbered blocks in units of 12 tracks, for example.
Add 7 bytes of C3 parity to each. As the error detection and correction code, for example, Reed Solomon code may be used.

FIG. 5 shows C in the data recording area 7 of FIG.
This is a portion excluding one parity 23. 45 is a data recording area of one track, and D (i, j, k)
Is data 41 or control signal 42, R (i, j, k) is C3 parity 44, and Q (i, j, k) is C2 parity 4
It is 3. Further, i is a track address (0 to 11),
j is a block address (0 to 157), and k is a data position (0 to 194) in one block. The track address is added in units of 12 tracks. At this time, the polynomial expression C2 (x) of the code sequence of the second error detection / correction code is as follows.

[0016]

[Equation 1]

However, 0≤i0≤11, 0≤k0≤194
Is.

The polynomial expression C3 (x) of the code sequence of the third error detection / correction code is as follows.

[0019]

[Equation 2]

However, i '= (i0 + n) mod12,
j '= j0 + 2n, k' = (k0 + n) mod 195,0
≤ i0 ≤ 11, 0 ≤ j0 ≤ 1, and 0 ≤ k0 ≤ 194.
That is, when j0 = 0, 7 bytes of C3 parity is added to 70 bytes of data having an even block address. When j0 = 1, 7 bytes of C3 parity is added to 69 bytes of data having an odd block address. At this time, the equation 2 becomes n = 0 to 75. Therefore, it is necessary to make the processing different when j0 = 0 and when 1, but when j0 = 1, n = 76 (j = 153)
If the processing is performed assuming that there is virtual data such as "0" at the time of, both can be performed by the same processing.

The polynomial expression C3 (x) of the code sequence of the third error detection / correction code may be expressed by the following equation.

[0022]

(Equation 3)

However, i '= i "= (i0 + n) mod
12, j '= j0 + 2n + 13, j "= j0 + 2n-1
40), k '= k "= (k0 + n) mod195, or i' = (i0 + n + 6) mod12, i" = (i0
+ N-70) mod12, j '= j0 + 2n + 13,
j ″ = j0 + 2n−140, k ′ = (k0 + n + 6) mo
d195, k "= (k0 + n-70) mod195,0
≤ i0 ≤ 11, 0 ≤ j0 ≤ 1, and 0 ≤ k0 ≤ 194.
That is, when j0 = 1, 7 bytes of C3 parity is added to 70 bytes of data having an even block address. When j0 = 0, 7 bytes of C3 parity is added to 69 bytes of data having an odd block address. At this time, the equation 2 becomes n = 1 to 76. Therefore, it is necessary to make the processing different between when j0 = 0 and when 1, but when j0 = 0 and n = 0 (j = 13), it is assumed that there is virtual data, for example, "0". Both can be performed in the same process. In this case, the order of the data and the parity is reversed, but since the parity is arranged in the lower order on the polynomial, the generation becomes easy.

As described above, by changing the code length (the number of data) between the code sequence of the odd block address and the code sequence of the even block address, it is possible to form a two-sequence code sequence even when the number of data blocks is odd. it can. Even if the code lengths are different in each series, the same processing can be performed as described above as long as the number of parities is the same.
Similarly, it is also possible to divide into three or more series.

Of course, the code length 153 and the parity number 14
One series of codes may be used. In this case, the polynomial expression C3 (x) of the code sequence is

[0026]

[Equation 4]

However, i '= (i0 + n) mod12,
j ′ = n, k ′ = (k0 + n) mod195, 0 ≦ i0 ≦
11, 0 ≦ k0 ≦ 194, or

[0028]

(Equation 5)

However, i '= i "= (i0 + n) mod
12, j '= n + 14, j' = n-139, k '=
k ″ = (k0 + n) mod195 or i ′ = (i0 + n
+14) mod12, i ″ = (i0 + n-139) mo
d12, j '= n + 14, j' = n-139, k '=
(K0 + n + 14) mod 195, k ″ = (k0 + n−
139) mod 195, 0 ≦ i0 ≦ 11, 0 ≦ k0 ≦ 19
It becomes 4.

When the third error detection / correction code is added in units of m tracks, if the number of parities is 1 / m or more of the code length, erasure correction is performed to correct even one track erroneously. be able to. In the present embodiment, the error detection and correction code having a code length of 77 or 76 and a parity number of 7 is set to 1
It is added in units of 2 tracks. That is, one series of codes is composed of 7 bytes or 6 bytes in one track, and an error of up to 7 bytes can be corrected by erasure correction, so that even if one track is all erroneous, it can be corrected.

Here, if the track address is repeated on a track of an integral multiple of m, for example, 60 tracks, and the track address and the code sequence are associated with each other, the track address is detected to detect the code sequence. Identification can be done.

FIG. 6 shows the data structure of one track in the additional information recording area 3. The sync signal 20 and the ID information 21 are omitted. The additional information recording area 3 is composed of 14 blocks, and the information 51 related to a video signal such as an audio signal is recorded in 9 blocks. The second error detection and correction code (C2 parity) 52 is recorded in the following 5 blocks. As with the data recording area 7, the parity 52 adds 5 bytes of parity to 9 bytes of data. In this way, the same number of data recording areas 7 and C2 parities can be used for the same processing. Although the third error detection and correction code is not added to the additional information recording area 3, this is because, for example, in the case of an audio signal, even data and odd data are dispersed in different tracks. This is because even if all the tracks become erroneous, it is possible to perform efficient correction by the average value interpolation. Of course, the third error detection and correction code may be added to this area as well.

In the additional information recording area 3 as well, the parity 52 is arranged closer to the end of the track (upper part in FIG. 6), and the parity is generated by the same method as the equation 4 or the equation 5. , It is possible to reduce the probability that data will be erroneous for dropouts that tend to occur at both ends of the tape.

FIG. 7 shows another example of the structure of one track of data in the data recording area 7. The synchronization signal 20
The ID information 21 is omitted. Data recording area 7
Is composed of, for example, 161 blocks, and the first 2
Control information 42 in blocks and 156th blocks, third error detection and correction code (C3 parity) 44 in 14th blocks from 3rd to 16th blocks, data in 139 blocks in 17th to 155th blocks, last 5 Second error detection and correction code (C2 parity) in the block
Record 43. The C2 parity 43 adds 5 bytes of C2 parity to 139 bytes of data, 3 bytes of control signal, and 14 bytes of C3 parity in track units. The C3 parity 44 adds 14 blocks of C3 parity to 139 blocks of data in units of 12 tracks, for example. The addition of C3 parity is
It may be similar to the case of FIG. In this way, when the data and the control signal are arranged in different blocks, the code length can be shortened and the correction capability can be improved by adding the third error detection and correction code only to the data. . Since the control signal 42 normally records the same information in multiplex, there is no problem even if the third error detection and correction code is not added.

FIG. 9 shows the structure of the data 22 in the subcode recording area 12. In FIG. 9, 8-byte packs 91, 92, and 93 are recorded as data. Parity 2
3 is 5 bytes. This parity can also be used for processing by making the C2 parity of the data recording area 7 and the additional information recording area 3 have the same number of parity.

FIG. 10 shows an embodiment of a digital signal recording apparatus for recording by the recording method of the present invention. 10
0 is a rotary head, 101 is a capstan, and 102 is FIG.
A recording signal processing circuit that generates a recording signal, a recording signal detection circuit 103 that detects the transmission rate, type, etc. of the recording signal, and a control 104 that controls the recording mode or the like according to the result detected by the recording signal detection circuit 103. A control circuit such as a microprocessor, 105 is the rotary head 10
A timing generation circuit that generates a timing signal that serves as a reference for rotation of 0, 106 is a servo circuit that controls the feed speed of the rotary head and the tape, and 107 is an interface circuit.

The recording data input from the input terminal 108 is input to the recording signal processing circuit 101 and the recording signal detection circuit 102 via the interface circuit 107.
The recording signal detection circuit 102 detects the transmission rate, type, etc. from the rate of the information or signal added to the recording data and outputs it to the control circuit 104. The control circuit 104 determines the recording mode based on the detection result, and sets the operation modes of the recording signal processing circuit 102 and the servo circuit 106. In the synchronous mode, although omitted in the figure, the timing generation circuit 105 outputs a synchronous clock and inputs data at that timing. In the recording signal processing circuit 102, the additional information is separated, the error detection / correction code, and I are added according to the recording mode judged by the control circuit 104.
D information, subcodes, etc. are generated, the recording signal of FIG. 1 is generated, and the rotary head 100 records the tape 81.

FIG. 11 shows an example of the configuration of the recording signal processing circuit 102. 200, 210, 220 are memory circuits, 20
1, 211, 221 are data buses, 222 is a C3 encoding circuit, 203, 213 are C2 encoding circuits, 204, 21
4 is a C1 encoding circuit, 205 and 215 are synchronization signals, and ID
A recording signal generation circuit for generating a recording signal by adding information and the like, 206 and 216 are output terminals for recording signals to the A head and B head, respectively, and 223 is an input terminal for recording data.

The recording data input from the input terminal 223 is stored in the storage circuit 220 via the bus 221.
The C3 encoding circuit 222 adds C3 parity to the recording data stored in the storage circuit 220 in units of 12 tracks. At this time, the storage circuit 220 stores the C3 parity so that it is arranged at the head as shown in FIG. 4 or 7. After that, the data recorded by the A head is stored in the storage circuit 200 via the bus 201, and the data recorded by the B head is stored in the storage circuit 210 via the bus 211. The data recorded in the A head stored in the storage circuit 200 is added with C2 parity in track units in the C2 encoding circuit 203 and then added with C1 parity in block units in the C1 encoding circuit 204. Is input to the recording signal generation circuit 205, a synchronization signal, ID information, and the like are added to generate a recording signal, which is output from the output terminal 206. The data recorded on the B head is also subjected to the same processing and output from the output terminal 216. In the present embodiment, the coding processing of C2 and C1 is performed independently for even-numbered tracks and odd-numbered tracks, but of course, two-track processing may be performed by the same circuit. Further, with respect to the C1 coding circuit, the C2 coding circuit, and the C1 coding circuit, the same circuit may generate all or two types of parity.

It is not necessary to generate C3 parity for the data recorded in the additional information recording area 3. For the subcode, the C2 code generation circuit may generate the parity.

FIG. 12 shows an embodiment of a digital signal reproducing apparatus for reproducing a signal recorded by the recording method of the present invention. Reference numeral 110 is a reproduction signal processing circuit for reproducing data and ID information from the reproduction signal, 111 is an output clock generation circuit for generating an output clock of reproduction data, and 112 is an interface circuit.

At the time of reproduction, the reproduction operation is first performed in an arbitrary reproduction mode, and the reproduction signal processing circuit 110 detects the ID information. Then, the control circuit 104 determines in which mode the recording was performed, and the operation modes of the reproduction signal processing circuit 110 and the servo circuit 106 are reset and reproduction is performed. The reproduction signal processing circuit 110 detects the synchronization signal, error detection and correction, etc. from the reproduction signal reproduced by the rotary head 100, reproduces the data, the additional information, and the subcode, and outputs them to the interface circuit 112. If the tape is recorded in the time-axis compression mode, the tape feed speed is set to 1 / the compression rate at the time of recording, and the reproduced signal is processed by the reproduction signal processing circuit 110 to set the track address 32 and the block address 33. As a reference, the data is rearranged in the same order as when it was recorded and then output. The output clock generation circuit 111 reproduces a clock synchronized with the data transmission rate at the time of recording by a PLL or the like with reference to the amount of data recorded on the track, and outputs it to the interface circuit 112. In the interface circuit 112, the output clock generation circuit 111
The reproduced data is output from the output terminal 113 with the clock generated in step 1 as a reference. The data may be output separately from the data and the additional information, or may be multiplexed and output.

Similarly to the recording signal processing circuit 102, the reproducing signal processing circuit 110 may independently perform C1 correction and C2 correction on the reproduced signals of the A track and the B track, and then perform C3 correction in units of 12 tracks.

[0044]

According to the present invention, by adding the third error detection and correction code added in the unit of a plurality of tracks in addition to the first and second error detection and correction codes added in the unit of track, Even if all the tracks are in error, the error can be corrected. Further, by arranging the second error detection correction code and the third error detection correction code at both ends of the recording area and by arranging the data at the center, the data can be stored against the dropouts that are likely to occur at both ends of the tape. The probability of error can be reduced.

[Brief description of drawings]

FIG. 1 is a recording pattern diagram of one track according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of each area.

FIG. 3 is a configuration diagram of ID information 21.

FIG. 4 is a configuration diagram of data of one track in a data recording area 7.

5 is a C1 parity 2 in the data recording area 7 of FIG. 4;
It is a figure showing the part except 3.

FIG. 6 is a configuration diagram of data of one track in an additional information recording area 3.

7 is another configuration diagram of data of one track in the data recording area 7. FIG.

FIG. 8 is a diagram showing a recording pattern on a tape.

FIG. 9 is a configuration diagram of data 22 in the subcode recording area 12.

FIG. 10 is a configuration diagram of a digital signal recording apparatus for performing recording by the recording method of the present invention.

11 is a configuration diagram of a recording signal processing circuit 102. FIG.

FIG. 12 is a block diagram of a digital signal reproducing apparatus for reproducing a signal recorded by the recording method of the present invention.

[Explanation of symbols]

3 ... additional information recording area, 7 ... data recording area, 12 ... subcode recording area, 20 ... synchronization signal, 21 ... ID information,
22 ... Data, 23 ... C1 parity, 41 ... Video signal data, 42 ... Control information, 43 ... C2 parity, 44 ... C
3 parity, 51 ... Additional information data, 52 ... C2 parity, 100 ... Rotating head, 101 ... Capstan, 10
2 ... Recording signal processing circuit, 103 ... Recording signal detecting circuit, 1
04 ... Control circuit, 105 ... Timing generation circuit, 106
… Servo circuit, 107… Interface circuit, 200
... storage circuit, 203 ... C2 encoding circuit, 204 ... C1 encoding circuit, 205 ... recording signal generating circuit, 210 ... storage circuit, 213 ... C2 encoding circuit, 214 ... C1 encoding circuit, 215 ... recording signal generating circuit , 220 ... Memory circuit, 2
22 ... C3 encoding circuit.

Claims (10)

[Claims] 1. A digital signal is divided into a predetermined number of bytes, and a sync signal, a control signal and a plurality of types of error detection and correction codes are added to each of the digital signals divided into the predetermined number of bytes to form a block format, In the digital signal recording method of forming a digital signal recording area by several blocks and recording it on a magnetic recording medium, in the error detection and correction code, one series of error detection and correction codes is 1
A first error detection / correction code composed of signals contained in a block, and second and third error detection / correction codes composed of signals in which one sequence of error detection / correction code is composed of a plurality of blocks. , The second and third error detection and correction codes are respectively arranged in blocks at both ends of the recording area, and the digital signal is stored in the second area of the recording area.
And a digital signal recording method characterized by arranging and recording in a block inside a block in which a third error detection and correction code is arranged. 2. The third error detection and correction code is arranged in a block on the head side of the recording area, and the second error detection and correction code is arranged and recorded in a block on the last side of the recording area. The digital signal recording method according to claim 1, wherein 3. The digital signal recording method according to claim 1, wherein the third error detection and correction code is composed of a plurality of types of sequences having different code lengths. 4. A plurality of types of sequences having different code sequences are
4. The digital signal recording method according to claim 3, wherein the numbers of parities are the same. 5. A fourth error detection / correction code having the same block format as the block and the same format as the first error detection / correction code, and the same parity number as the second error detection / correction code. 2. The digital signal recording method according to claim 1, further comprising a second digital signal recording area to which a fifth error detection and correction code is added. 6. A digital signal is divided into a predetermined number of bytes, and a sync signal, a control signal and a plurality of types of error detection and correction codes are added to each of the digital signals divided into the predetermined number of bytes to form a block format, In a digital signal recording device for forming a digital signal recording area by several blocks and recording it on a magnetic recording medium, a first encoding for adding a third error detection and correction code to the digital signal in units of a plurality of blocks. A circuit and the digital signal encoded by the first encoding circuit to the third signal.
Second encoding circuit for adding a second error detection and correction code in a block unit different from the block to which the error detection and correction code is added, and a block for the digital signal encoded by the second encoding circuit. A third encoding circuit for adding the first error detection and correction code in units is provided, and the second and third error detection and correction codes are respectively arranged in blocks at both ends of the recording area, and the digital signal is output. A digital signal recording apparatus, characterized in that it is arranged and recorded in a block inside a block in which the second and third error detection and correction codes of the recording area are arranged. 7. The third error detection and correction code is arranged in a block on the head side of the recording area, and the second error detection and correction code is arranged and recorded in a block on the last side of the recording area. 7. The digital signal recording method according to claim 6, wherein. 8. The digital signal recording device according to claim 6, wherein the first encoding circuit adds the same number of parities to a plurality of types of digital signals having different data numbers. 9. A digital signal is divided into a predetermined number of bytes, and a sync signal, a control signal and a plurality of types of error detection and correction codes are added to each of the digital signals divided into the predetermined number of bytes to form a block format, In a digital signal recording method of forming a digital signal recording area by several blocks and recording it on a magnetic recording medium, at least one error detection correction code among the plurality of types of error detection correction codes is an error detection correction code. 1 is composed of signals included in a plurality of blocks, and the error detection and correction code is generated so as to be located in the higher order on the code polynomial, and the error detection and correction code is arranged in the first block. , A digital signal recording method characterized by arranging and recording a digital signal in a subsequent block. 10. A digital signal is divided into a predetermined number of bytes, and a sync signal, a control signal, and a plurality of types of error detection and correction codes are added to each of the digital signals divided into the predetermined number of bytes to form a block format, In a digital signal recording method of forming a digital signal recording area by several blocks and recording it on a magnetic recording medium, at least one error detection correction code among the plurality of types of error detection correction codes is an error detection correction code. Is generated by signals included in a plurality of blocks, and the error detection / correction code is generated so as to be located in the lower order on the code polynomial, and the error detection / correction code is digitally generated in the first block. A method for recording a digital signal, characterized in that the position of the signal is changed so as to be arranged in a subsequent block and the signal is recorded.