JP3257291B2 - Digital signal recording method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for recording digital signals, and more particularly to a method and apparatus for recording digital compressed video signals.

[0002]

2. Description of the Related Art A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape by using a rotary head is described in Japanese Patent Application Laid-Open No. 5-174496.

[0003]

In such a digital signal recorder, in order to correct a data error at the time of reproduction, an error correction code is added double in track units. However, no consideration is given to a case where all tracks are erroneous due to clogging of the head or the like.

An object of the present invention is to provide a digital signal recording method and apparatus capable of coping with a case where all tracks are erroneous.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to divide a digital signal into a predetermined number of bytes, add a synchronization signal, a control signal, and an error detection and correction code to the digital signal divided into a predetermined number of bytes. In a digital signal recording method and apparatus in which a digital signal recording area is formed by a predetermined number of blocks and recorded on a magnetic recording medium, one series of the error detection and correction code is included in one block. A first error detection and correction code composed of included signals, a second error detection and correction code composed of signals in which one series of error correction codes are included in a plurality of blocks in one track, and an error detection and correction code 1 sequence Ri is the name more <br/> third ECC code composed of signals included in the plurality of blocks across a plurality of tracks, and the, Serial third error detection correction code, the code length
This can be achieved by being constituted by a plurality of different types of series .

[0006]

The first error detection and correction code is added in units of blocks, so that errors in the block can be corrected. The second error detection and correction code is added in units of tracks, so that one track can be corrected. Can be corrected over a plurality of blocks within the third error detection and correction code,
Since it is added in units of a plurality of tracks, it is possible to correct errors that extend over a plurality of tracks.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a recording pattern of one track.
Reference numeral 3 denotes an additional information recording area for recording an audio signal, etc., 7 denotes a data recording area for recording a digital compressed video signal, 12 denotes a subcode recording area for recording subcodes such as time information and program information, and 2, 6 and 11 denote, respectively. , 4, 8 and 13 are postambles of the respective recording areas, 5 and 9 are gaps between the respective recording areas, and 1 and 14 are track edge margins. By providing a postamble, a preamble, and a gap in each recording area in this way, it is possible to perform dubbing on each area independently. Of course, digital signals other than digital compressed video signals and audio signals may be recorded in the recording areas 3 and 7.

FIG. 2 shows a block configuration of each area. FIG.
(A) shows the additional information recording area 3 and the data recording area 7,
Is a block configuration. Reference numeral 20 denotes a synchronization signal, 21 denotes ID information, 22 denotes a video signal or additional information data, and 23 denotes a first signal.
(C1 parity) for error detection and correction. The synchronization signal 20 is composed of 2 bytes, the ID information 21 is composed of 4 bytes, the data 22 is composed of 195 bytes, the parity 23 is composed of 9 bytes, and one block is composed of 210 bytes. FIG. 2B shows a block configuration of the subcode recording area 12. In the block of the subcode recording area, the synchronization signal 20 and the ID information 21 are the same as those in FIG. 2A, the data 22 is composed of 24 bytes, and the parity 23 is composed of 5 bytes. ) Is composed of 35 bytes of 1/6 of the block. In this way, the number of bytes in one block is also made to be an integer ratio, and the configuration of the synchronization signal 11 and the ID information 12 is the same in all areas, so that the generation of the block at the time of recording and the synchronization signal at the time of recording are performed. , ID information detection and the like can be processed by the same circuit.

FIG. 3 shows the structure of the ID information 21. 31
Is an area code, 32 is a track address, 33 is a block address in one track, 34 is ID data, and 35 is a parity for detecting errors in the area code 31, track address 32, block address 33 and ID data 34. . The area code 31 is for identifying each area. For example, in the data recording area 7, "0"
0, "10" in the additional information recording area 3, and "11" in the subcode recording area 12. In the data recording area 7 and the like, a plurality of types of codes, for example, "00" and "" are used.
01 "may be assigned to identify different data such as variable speed reproduction data.
An address for identifying a track, for example,
The address is changed in units of one track or two tracks. In this case, 64 tracks or 128 tracks can be identified by a 6-bit address. The block address 33 is an address for identifying a block in each recording area. For example, in the data recording area 7, 0
157, 0-13 in the additional information recording area 3, and 0-17 in the subcode recording area 12.

The track address 32 is repeated in, for example, a track unit of 12 or a multiple thereof in order to identify a third error correction code described later.

The C1 parity 23 is, for example, the data 22
And an area code 31, a track address 32, and a block address in the ID information 21. As a result, the ability to detect a block address and the like during reproduction can be improved.

FIG. 4 shows the structure of data of one track in the data recording area 7. Note that the synchronization signal 20 and the ID information 21 are omitted. Data recording area 7 is 15
The first 139 blocks contain data, and the next 14 blocks contain a third error correction code (C
3) 44 and a second error correction code (C2 parity) 43 in the last five blocks. The first 139 blocks are 188 bytes of video signal data 41.
And control information 42 related to the video signal 41 such as a 7-byte signal type, recording date and time, and editing information.

The C2 parity 43 is 13 per track.
A 5-byte C2 parity is added to the 9-byte data and the 14-byte C3 parity. The C3 parity 44 divides 139 blocks of data into even blocks and odd blocks in units of 12 tracks, for example.
A 7-byte C3 parity is added to each. For example, a Reed-Solomon code may be used as the error correction code.

FIG. 5 shows C in the data recording area 7 of FIG.
This shows a portion excluding one parity 23. 45 is a data recording area of one track, and D (i, j, k)
Is data 41 or control signal 42, R (i, j, k) is C3 parity 44, Q (i, j, k) is C2 parity 4
3. I is a track address (0 to 11);
j is a block address (0 to 157), and k is a data position (0 to 194) in one block. It is assumed that the track address is added in units of 12 tracks. At this time, the polynomial expression C ₂ (x) of the code sequence of the second error correction code is as follows.

[0016]

(Equation 1)

However, 0 ≦ i ₀ ≦ 11, 0 ≦ k ₀ ≦ 194
It is.

The polynomial expression C ₃ (x) of the code sequence of the third error correction code is expressed by the following expression.

[0019]

(Equation 2)

Where i ′ = (i ₀ + n) mod 12,
j ′ = j ₀ + 2n−1, k ′ = ｛(k ₀ + n) mod 19
5｝, 0 ≦ i ₀ ≦ 11, 0 ≦ j ₀ ≦ 1, 0 ≦ k ₀ ≦ 194
It is. That is, when j ₀ = 1, 7-byte C3 parity is added to 70-byte data having an even block address. When j ₀ = 0, a C3 parity of 7 bytes is added to 69 bytes of data having an odd block address. At this time, Equation 2 is n = 1 to 7
It becomes 6. Therefore, it is necessary to make the processing different between j ₀ = 0 and 1. When j ₀ = 0, n = 0 (j = −
In the case of 1), if processing is performed on the assumption that there is virtual data, for example, “0”, both can be performed by the same processing.

As described above, by changing the code length (number of data) between the code sequence of the odd block address and the code sequence of the even block address, two code sequences can be formed even when the number of data blocks is odd. it can. The same processing can be performed as described above, even if the code length is different in each sequence, as long as the number of parity is the same.
Similarly, it is possible to divide into three or more series.
Of course, one sequence code having a code length of 153 and a parity number of 14 may be used, but by dividing, the number of parity of one code sequence can be reduced, and the error correction process is facilitated.

When the third error correction code is added in units of m tracks, if the number of parities is equal to or more than 1 / m of the code length, erasure correction is performed to correct even if all tracks are erroneous. Can be. In this embodiment, the code length 77
Or 76, an error correction code having a parity number of 7 is added in units of 12 tracks. That is, a one-series code is composed of 7 bytes or 6 bytes in one track, and an error of up to 7 bytes can be corrected by erasure correction. Therefore, even if all tracks are erroneous, it can be corrected.

Here, the track address is repeated on a track of an integral multiple of m, for example, 60 tracks, and if this track address is made to correspond to a code sequence, the track address is detected and the code sequence of the code sequence is detected. Identification can be performed.

FIG. 6 shows the structure of one track of data in the additional information recording area 3. Note that the synchronization signal 20 and the ID information 21 are omitted. The additional information recording area 3 is composed of 14 blocks, and information 51 relating to a video signal such as an audio signal is recorded in 9 blocks. In the subsequent five blocks, a second error correction code (C2 parity)
Record 52. As with the data recording area 7, the parity 52 adds a 5-byte parity to 9-byte data. In this way, by making the number of the data recording area 7 and the number of the C2 parity the same, the processing can be shared. Note that the third error correction code is not added to the additional information recording area 3. For example, in the case of an audio signal, this is achieved by dispersing even data and odd data on different tracks. This is because even if all the tracks become erroneous, efficient correction by average value interpolation can be performed. Of course, a third error correction code may be added to this area.

FIG. 7 shows the ID data 3 in the data recording area 7.
4. The ID data 34 constitutes one piece of information with, for example, 5 bytes of 5 blocks. By multiplex-recording this information a plurality of times, the detection capability at the time of reproduction is improved. The data of 5 blocks is ID-1
7 are composed of seven types of data.

ID-1 defines the recording format of the data recording area 7. That is, by changing the value of ID-1, it is possible to cope with a plurality of types of formats.

ID-2 specifies the recording mode, that is, the maximum recording capacity. In the present embodiment, when two-channel recording is performed at a rotation speed of 1800 rpm using four rotating heads, data of about 25 Mbps can be recorded. FIG. 8 shows a recording pattern on the tape at this time. Reference numeral 81 denotes a tape, and reference numeral 82 denotes one track shown in FIG. 1A, 1B, 2A, and 2B represent four recording heads.
A track (one frame) is recorded. Here, FIG.
If recording is performed once every two times as shown in (b),
The recording capacity is about 12.5 Mbps. FIG.
If recording is performed once every four times as shown in (c),
The recording capacity is about 6.25 Mbps. In this case, if the tape feed speed is set to 1/2 or 1/4, the track patterns on the tape become almost the same. Similarly, the maximum recording capacity can be reduced to 1 / n of 25 Mbps. When recording, identify the transmission rate of the recorded data,
Set the optimal recording mode and record. Then, the mode in which the recording was performed is recorded in ID-2. For example,
It is set to "1" at 25 Mbps, "2" at 12.5 Mbps, and "3" at 6.25 Mbps.

ID-3 specifies a time axis compression mode, that is, a time axis compression ratio at the time of recording. This corresponds to a method in which a digital signal is compressed in a time axis and transmitted in a short time, and is recorded and then expanded in a time axis to be reproduced. For example, the value is "1" when there is no time axis compression, "2" when the time axis compression ratio is twice, and "3" when the time axis compression ratio is four times.

ID-4 defines the number of channels of data to be recorded simultaneously. For example, in recording mode 1,
12.5 Mbps data can be recorded on two channels.

ID-5 specifies whether the rate of data to be recorded is synchronized with the number of rotations of the rotary head. For example, it is “1” when synchronized, and “0” when not synchronized. When synchronized, the amount of data to be recorded on each track can be made constant, and when not synchronized, it is necessary to change between tracks.

ID-6 specifies the amount of data to be recorded on one track. For example, when recording 12 Mbps data, the recording mode 2 may be selected and 25,000 bytes may be recorded on one track. When the data rate is not synchronized with the rotation speed of the rotary head, the data amount may be controlled in frame units.

The ID-7 is information relating to the type of data and other recording data.

As described above, by controlling the recording mode and the amount of data to be recorded on one track in accordance with the transmission rate of the data to be recorded, efficient recording can be performed by a simple recording and reproducing process. At the time of reproduction, it is sufficient to first detect the ID data 34, identify the recording mode or the like, set the reproduction processing circuit to that mode, and perform reproduction.

The ID data 34 of the additional information recording area 3 may have the same configuration as that of FIG. In the additional information recording area 3, additional information of about 1.6 Mbps can be recorded in the recording mode 1, and for example, a PCM audio signal having a quantization frequency of 48 kHz, a quantization bit number of 16 bits, and two channels can be recorded. .

ID data 34 of subcode recording area 12
Records a start flag indicating the beginning of the program, a flag for skip reproduction, and the like. In the subcode recording area 12, unlike the data recording area 7 and the additional information recording area 3, the same data is recorded in all blocks in one frame. As a result, the detection capability at the time of high-speed search or the like can be improved.

FIG. 10 shows the structure of the data 22 in the subcode recording area 12. In FIG. 10, 8-byte packs 91, 92 and 93 are recorded as data. The parity 23 has 5 bytes. This parity can also be used for processing by making the number of parity equal to the C2 parity of the data recording area 7 and the additional information recording area 3.

FIG. 11 shows the structure of the packs 91 to 93. Byte 0 is an item indicating the content of information to be recorded in the pack. By switching items, a plurality of types of information can be recorded. Byte 7 is a parity for detecting an error in the pack data.

FIG. 12 shows an embodiment of a digital signal recording apparatus for performing recording by the recording method of the present invention. 10
0 is a rotating head, 101 is a capstan, 102 is FIG.
A recording signal processing circuit 103 for generating a recording signal of the recording signal 103, a recording signal detecting circuit 103 for detecting a transmission rate and a type of the recording signal, and a control 104 for controlling a recording mode and the like according to a result detected by the recording signal detecting circuit 103. Control circuit, such as a microprocessor, 105
A timing generation circuit for generating a timing signal serving as a reference for rotation of 0 or the like, a servo circuit 106 for controlling the rotation speed of the rotary head and the tape, and an interface circuit 107.

The recording data input from the input terminal 108 is input to the recording signal processing circuit 101 and the recording signal detection circuit 102 via the interface circuit 107.
The recording signal detection circuit 102 detects a transmission rate, a type, and the like from the information or signal rate added to the recording data, and outputs the detection result to the control circuit 104. The control circuit 104 determines the recording mode based on the detection result, and sets the operation mode of the recording signal processing circuit 102 and the servo circuit 106. In the case of the synchronous mode, although not shown in the figure, a synchronous clock is output from the timing generation circuit 105 and data is input at that timing. The recording signal processing circuit 102 separates additional information, generates an error correction code, ID information, a subcode, etc., according to the recording mode determined by the control circuit 104, generates the recording signal of FIG. Recording is performed on the tape 81 by the head 100.

FIG. 13 shows an example of the configuration of the recording signal processing circuit 102. 200, 210, 220 are storage circuits, 20
1, 211 and 221 are data buses, 222 is a C3 encoding circuit, 203 and 213 are C2 encoding circuits, and 204 and 21.
4 is a C1 encoding circuit, 205 and 215 are synchronization signals, ID
A recording signal generation circuit 206 for generating a recording signal by adding information and the like, 206 and 216 are output terminals for recording signals to the A-head and B-head, respectively, and 223 is an input terminal for recording data.

The recording data input from the input terminal 223 is stored in the storage circuit 220 via the bus 221.
The recording data stored in the storage circuit 220 is added with a C3 parity in the C3 encoding circuit 222 in units of 12 tracks, and thereafter, the data recorded by the A head is stored in the storage circuit 200 via the bus 201. Data recorded by the B head is stored in the storage circuit 210 via the bus 211. The data recorded in the A head stored in the storage circuit 200 is added to the C2 parity in the track unit in the C2 encoding circuit 203,
In one encoding circuit 204, the C1 parity is added in block units and input to the recording signal generation circuit 205, where a synchronization signal, ID information and the like are added to generate a recording signal, which is output from the output terminal 206. The data recorded in the B head is output from the output terminal 216 after performing the same processing. In the present embodiment, the encoding processes of C2 and C1 are independently performed on the even-numbered track and the odd-numbered track. However, it is needless to say that two-track processing may be performed by the same circuit. Also, the same circuit may generate all or two types of parity for the C1 encoding circuit, the C2 encoding circuit, and the C1 encoding circuit.

It is not necessary to generate a C3 parity for data recorded in the additional information recording area 3. For the sub-code, parity generation may be performed by a C2 code generation circuit.

FIG. 14 shows an embodiment of a digital signal reproducing apparatus for reproducing a signal recorded by the recording method of the present invention. Reference numeral 110 denotes a reproduction signal processing circuit that reproduces data, ID information, and the like from the reproduction signal, 111 denotes an output clock generation circuit that generates an output clock of the reproduction data, and 112 denotes an interface circuit.

At the time of reproduction, first, a reproduction operation is performed in an arbitrary reproduction mode, and the reproduction signal processing circuit 110 detects ID information. Then, the control circuit 104 determines which mode has been recorded, and the operation mode of the reproduction signal processing circuit 110 and the servo circuit 106 is reset to perform reproduction. The reproduction signal processing circuit 110 performs detection of a synchronization signal, error detection and correction, and the like from the reproduction signal reproduced by the rotary head 100, reproduces data, additional information, and subcode, and outputs the reproduced data to the interface circuit 112. In the case of recording in the time axis compression mode, the tape feed speed is set to 1 / the compression ratio at the time of recording, and the reproduced signal is processed by the reproduction signal processing circuit 110 so that the track address 32 and the block address 33 are converted. The data is rearranged in the same order as at the time of recording and output. The output clock generation circuit 111 reproduces a clock synchronized with the data transmission rate at the time of recording by a PLL or the like based on the amount of data recorded on the track, and outputs the clock to the interface circuit 112. In the interface circuit 112, the output clock generation circuit 111
The reproduced data is output from the output terminal 113 on the basis of the clock generated in step (1). As for the data output, the data and the additional information may be output independently or may be multiplexed and output.

In the reproduction signal processing circuit 110, similarly to the recording signal processing circuit 102, C1 correction and C2 correction are independently performed on the reproduction signals of the tracks A and B, and then the C3 correction is performed in units of 12 tracks.

[0046]

According to the present invention, in addition to the first and second error detection and correction codes added in track units, the third error detection and correction code added in multiple track units is added. Even when all the tracks become erroneous, the error can be corrected.

[Brief description of the drawings]

FIG. 1 is a recording pattern diagram of one track according to an embodiment of the present invention.

FIG. 2 is a block diagram of each area.

FIG. 3 is a configuration diagram of ID information 21.

FIG. 4 is a configuration diagram of data of one track in a data recording area 7;

FIG. 5 shows a C1 parity 2 in the data recording area 7 of FIG.
It is a figure showing the part except 3.

FIG. 6 is a configuration diagram of data of one track in an additional information recording area 3.

FIG. 7 is a configuration diagram of ID data 34 in a data recording area 7;

FIG. 8 is a diagram showing a recording pattern on a tape.

FIG. 9 is a timing chart during recording.

FIG. 10 is a configuration diagram of data 22 in a subcode recording area 12;

FIG. 11 is a configuration diagram of packs 91 to 93.

FIG. 12 is a configuration diagram of a digital signal recording device that performs recording by the recording method of the present invention.

FIG. 13 is a configuration diagram of a recording signal processing circuit 102.

FIG. 14 is a block diagram of a digital signal reproducing apparatus for reproducing a signal recorded by the recording method of the present invention.

[Explanation of symbols]

3 additional information recording area, 7 data recording area, 12 subcode recording area, 20 synchronization signal, 21 ID information,
22 data, 23 C1 parity, 31 area code, 32 track address, 33 block address, 34 ID data, 41 video signal data, 42
Control information, 43 ... C2 parity, 44 ... C3 parity,
51 ... additional information data, 52 ... C2 parity, 100 ...
Rotating head, 101: capstan, 102: recording signal processing circuit, 103: recording signal detection circuit, 104: control circuit, 105: timing generation circuit, 106: servo circuit, 107: interface circuit, 200: storage circuit, 203 ... C2 encoding circuit, 204: C1 encoding circuit, 205: recording signal generation circuit, 210: storage circuit, 2
13 ... C2 encoding circuit, 214 ... C1 encoding circuit, 21
5: recording signal generation circuit, 220: storage circuit, 222: C
3 coding circuit.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Keiji Noguchi Inventor Keiji Noguchi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd. Inside Hitachi, Ltd. Image Media Research Laboratories (56) References JP-A-6-150577 (JP, A) Kaisho 59-215013 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/18, 20/10

Claims (5)

(57) [Claims] A digital signal is divided into a predetermined number of bytes, and a synchronous signal, a control signal and an error detection / correction code are added to the digital signal divided into the predetermined number of bytes to form a block. In the digital signal recording method of forming a digital signal recording area by the block and recording the magnetic signal on a magnetic recording medium, the error detection and correction code is constituted by a signal including one series of the error detection and correction code in one block. a first error detection and correction code, and the second error detection and correction code constituted by a signal included in a plurality of blocks of one series are in one track of error detection and correction code, a series multiple tracks of the error detection and correction code Ri Na more and the third ECC code composed of signals included in the plurality of blocks that span,
The third error detection and correction code has a different code length.
A digital signal recording method comprising a plurality of types of streams . 2. The method according to claim 1, wherein the third error correction code comprises n pieces of the data.
Code length composed of digital signal and k parity
A first series of (n + k) and (n-1) said digits
Code length (n
+ K-1) composed of two types of second series.
Digital signal recording method according to claim 1, wherein the that. 3. A fourth error correction code having the same block format as the block and having the same format as the first error correction code, and a fifth error correction code having the same parity number as the second error correction code. 2. The digital signal recording method according to claim 1, wherein a second digital signal recording area to which an error correction code is added is provided. 4. A digital signal is divided into a predetermined number of bytes, and a synchronizing signal, a control signal and an error detection and correction code are added to the digital signal divided into the predetermined number of bytes to form a block. A digital signal recording apparatus for forming a digital signal recording area by said blocks and recording the digital signal on a magnetic recording medium, comprising: a third error detection / correction system comprising a plurality of types of sequences having different code lengths in units of a plurality of tracks in the digital signal. A first encoding circuit for adding a code, a second encoding circuit for adding a second error detection and correction code to the digital signal encoded by the first encoding circuit in track units, A third encoding circuit for adding a first error detection and correction code to the digital signal encoded by the second encoding circuit in block units; Digital signal recording apparatus characterized by. 5. The first encoding circuit according to claim 1, further comprising: a first parity addition unit for adding k parity units to the n digital signals spanning a plurality of tracks; and (n-1) digital signal units. 5. The digital signal recording apparatus according to claim 4, wherein a second parity addition for adding k parities is performed.