JPH08235782A - Data forming method, data reproducing method, data forming device, data reproducing device and recording method - Google Patents

Abstract

PURPOSE: To improve the reliability of data by performing interleave processing by piling up required sector packets and moving a control signal in an error correction code to the place just after a synchronizing signal after imparting the error correction code and the synchronizing signal to the control signal. CONSTITUTION: An even-odd frame Even-Odd-SynoFrame is formed by piling up sixteen rows of sector packets formed with six pieces of divided data into which data having a prescribed length are divided and the data are subjected to interleave processing. An error correction code is generated for every sector packet such as an odd frame and a control I&E included in the error correction code is moved so as to succeed the place just after a synchronizing signal Sync in the heading part of a head packet partitioned by a DC code DCC. This is similar to an even frame, by this code structure, deinterleaving is easily and surely performed, reproduction processing is simplified and the reliability of data is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data forming method for recording video data and the like on an optical disk, a data reproducing method, a data forming apparatus, a data reproducing apparatus and a storage medium related thereto.

[0002]

2. Description of the Related Art Generally, in data transmission, a sync signal is added to each fixed data length for transmission or recording. This is to prevent error propagation due to bit shift. That is, in information data in which a fixed number of bits is 1 symbol, if a signal error occurs during transmission and an extra bit is inserted or missing even in 1 bit during transmission, a continuous bit string is divided into symbols in the reproduction process. In this case, the increase / decrease of 1-bit error causes all the subsequent symbol data to be erroneous. Therefore, a sync signal is added in a fixed symbol unit and the sync signal is used to prevent error propagation due to bit shift. The same applies when recording information data on a recording medium such as an optical disk.

In data transmission or data recording with such a sync signal added, the reliability of the data can be improved by arranging the data immediately after the sync signal, and the reliability of the data can be increased by moving away from the sync signal. Means to go down.

However, since the information data is subjected to long interleaving processing (for example, interleaving processing using a plurality of sector packets) and an error correction code is added, it has high reliability regardless of the arrangement. Can be made.

For this reason, conventionally, an ID signal and a control signal, which require a reproduced signal, are arranged next to the synchronization signal in units of sectors, and then information data and an error correction code are arranged.

However, when the information data is arranged in this way, there is a problem that the control process becomes complicated in the memory control in the deinterleave process or the like. Further, in a system in which one sequence is divided into a plurality of frames when transmitting an encoded sequence and a synchronization signal is added to each frame, when the information data is divided and a control signal is inserted between them, the reproduction process is performed. It has the drawback of complexity.

[0007]

SUMMARY OF THE INVENTION The present invention has been made under such circumstances, and a data forming method capable of enhancing the reliability of data and facilitating memory control in reproduction processing. , A data reproducing method, a data forming device, a data reproducing device, and a storage medium.

Further, the present invention is a system in which one sequence is divided into a plurality of frames and a synchronization signal is added to each of them.
An object of the present invention is to provide a data forming method, a data reproducing method, a data forming device, a data reproducing device, and a storage medium that can easily perform a reproducing process.

[0009]

In order to solve such a problem, a data forming method of the present invention according to claim 1 divides data into data packets of a fixed length, and a sector packet composed of a plurality of divided data packets. And adding predetermined control data to each data packet in a distributed manner, and generating a first error correction code for each data packet including control data and adding the first error correction code to each data packet. No. 1 code sequence, a step of interleaving a plurality of sector packets in which the first code sequence is overlapped in a division order, and a second error correction code of each sequence after interleave processing is generated. Forming a second code sequence formed by adding the second code sequence to the second code sequence and adding a synchronization signal to the second code sequence. The control data included and a step of moving immediately after the synchronization signal.

According to a second aspect of the data forming method of the present invention, a step of dividing the data into data packets of a fixed length and forming a sector packet consisting of a plurality of divided data packets, and a predetermined control data for each data Adding to the packets in a distributed manner; generating a first error correction code of each data packet including control data to form a first code sequence added to each data packet; The sector packet in which the code sequence is overlapped in the division order is divided into a plurality of blocks, and the step of performing the inter-block interleaving process in each block and the sector packet in which the intra-block interleaving process is performed are overlapped in a plurality of stages to block the blocks. The step of performing interleave processing, and the second error correction code of each sequence after block interleave processing To generate a second code sequence by adding the sync signal to the beginning of the second code sequence and to add control data included in the second code sequence to the sync signal. And a step of moving immediately after.

According to a third aspect of the data forming method of the present invention, in the data forming method of the second aspect, the original data divided into data packets and the control data are arranged in different blocks. Characterize.

The data forming method of the present invention according to claim 4 is the data forming method according to claim 1, 2 or 3, wherein the control data includes first control data including address information of the sector packet, and a code. Second including the serialized sequence number
And control data of

According to a fifth aspect of the data forming method of the present invention, in the data forming method according to the fourth aspect, the second code sequence includes a head frame arranged at the head of the sector packet and a subsequent frame of the head frame. The first control data is moved immediately after the synchronization signal of the first frame, and the second control data is added to the subsequent frame. It is characterized by moving immediately after the frame synchronization signal.

According to a sixth aspect of the data forming method of the present invention, in the data forming method of the fifth aspect, the first control data is dispersed in units of one symbol immediately after the synchronization signal of each head frame forming the sector packet. The second control data is arranged in one symbol immediately after the synchronization signal of each subsequent frame forming the sector packet.

According to a seventh aspect of the data reproducing method of the present invention, the control data arranged immediately after the synchronization signal added to the second code sequence is moved to a predetermined position of the second code sequence. , A step of performing error detection and correction processing using each second code sequence using a second error correction code added to each second code sequence, and a sector from a plurality of data packets subjected to the error detection and correction processing. A step of constructing a packet and performing deinterleave processing by superposing these sector packets in a plurality of stages; and performing error detection and correction processing using the first error correction code added to each series after deinterleave processing And steps.

The data reproducing method of the present invention according to claim 8 comprises the step of moving the control data arranged immediately after the synchronization signal added to the second code sequence to a predetermined position of the second code sequence. , A step of performing error detection and correction processing using each second code sequence using a second error correction code added to each second code sequence, and a sector from a plurality of data packets subjected to the error detection and correction processing. A step of constructing a packet and performing a deinterleave process in block units by stacking these sector packets in multiple stages; a step of performing an in-block deinterleave process in each block; and a sequence of each sequence after the two deinterleave processes. And a step of performing error detection and correction processing using the first error correction code added to.

According to a ninth aspect of the data forming apparatus of the present invention, the data is divided into data packets of a fixed length, a sector packet composed of a plurality of divided data packets is formed, and predetermined control data is stored in each data packet. Control data addition means for adding in a distributed manner, and a first error correction code is generated for each data packet to which the control data is added by this control data addition means, and each first error correction code is added to each data packet. And a first code sequence forming means for forming a first code sequence, interleave processing means for performing interleave processing by superposing a plurality of sector packets in which the first code sequence is superposed in a division order, and after interleaving processing. Second code sequence forming means for generating a second error correction code of each sequence and adding it to each sequence to form a second code sequence. With adding a sync signal to the second code sequence, and a control data moving means for moving immediately after the synchronization signal control data included in the second code sequence. The data forming apparatus of the present invention according to claim 10 is
Data is divided into data packets of a fixed length, and a sector packet composed of a plurality of divided data packets is formed,
Control data adding means for adding predetermined control data to each data packet in a distributed manner, and a first error correction code for each data packet to which the control data is added by this control data adding means are generated to generate each first First code sequence forming means for forming a first code sequence by adding an error correction code to each data packet, and a sector packet in which the first code sequence is superposed in the division order are divided into a plurality of blocks, and In-block interleaving processing means for performing intra-block interleaving processing within a block, and block interleave processing means for performing block interleaving processing in block units by stacking sector packets that have been subjected to intra-block interleaving processing in multiple stages, and after block interleaving processing The second error correction code of each series is generated and added to each series. Second code sequence forming means for forming two code sequences, a sync signal is added to the head of the second code sequence, and the control data included in the second code sequence is moved immediately after the sync signal. Control data moving means.

The data forming apparatus of the present invention according to claim 11 is the data forming apparatus according to claim 10, wherein the original data divided into data packets and the control data are arranged in different blocks. Characterize.

According to a twelfth aspect of the present invention, there is provided the data forming device according to the ninth or tenth or eleventh aspect, wherein the control data includes first control data including address information of the sector packet and a code. And second control data including a chemical sequence number.

According to a thirteenth aspect of the present invention, there is provided the data forming apparatus according to the twelfth aspect, wherein the second code sequence includes a head frame arranged at the head of the sector packet and a subsequent frame of the head frame. The control data moving means adds a synchronization signal to the head of the first frame and the subsequent frame, and moves the first control data immediately after the synchronization signal of the first frame. Then, the second control data is moved immediately after the synchronization signal of the subsequent frame.

According to a fourteenth aspect of the present invention, in the data forming apparatus according to the thirteenth aspect, the control data moving means uses the first control data immediately after the synchronization signal of each head frame forming a sector packet. The second control data is distributed by 1 symbol immediately after the synchronization signal of each succeeding frame forming the sector packet.

According to a fifteenth aspect of the present invention, in the data reproducing apparatus, the control data arranged immediately after the sync signal added to the second code sequence is moved to a predetermined position of the second code sequence. Moving means and second error detection and correction processing means for performing error detection and correction processing using the second error correction code added to each second code sequence for each second code sequence to which the control data has been moved. A sector packet is composed of a plurality of data packets that have been subjected to error detection and correction processing, and deinterleave processing means for performing deinterleave processing by stacking these sector packets in multiple stages, and each series after deinterleave processing And a first error detection and correction processing means for performing error detection and correction processing using the first error correction code added to the.

According to a sixteenth aspect of the present invention, in the data reproducing apparatus of the present invention, the control data arranged immediately after the sync signal added to the second code sequence is moved to a predetermined position of the second code sequence. Moving means and second error detection and correction processing means for performing error detection and correction processing using the second error correction code added to each second code sequence for each second code sequence to which the control data has been moved. And a block deinterleave processing unit that constructs a sector packet from a plurality of data packets that have been subjected to error detection and correction processing, and that performs deinterleave processing in block units by stacking these sector packets in multiple stages, and within each block In-block deinterleave processing means for performing deinterleave processing, and first error correction code in which each series after two deinterleave processings is added to each series It comprises a first error detection and correction processing means for performing error detection and correction processing using the.

According to a seventeenth aspect of the present invention, there is provided a storage medium according to the present invention, in which a sector packet formed by superposing a plurality of data packets obtained by dividing data into a predetermined length, and a synchronization signal arranged at a predetermined position of each data packet. Predetermined control data dispersedly arranged immediately after each synchronization signal.

In the storage medium of the present invention as set forth in claim 18, a data packet obtained by dividing data into a fixed length is divided into a head frame and a subsequent frame arranged subsequent to the head frame, and these frames are divided. A plurality of overlapping sector packets, a first synchronization signal arranged at a predetermined position of each head frame, a second synchronization signal arranged at a predetermined position of each subsequent frame, and each first synchronization signal And first control data including the address information of the sector packet, and second control data including immediately after each second synchronization signal and including the coding sequence number. .

[0026]

According to the present invention, since the predetermined control data is dispersedly added to each data packet and the control data is moved immediately after the synchronization signal, the reliability of the data can be improved. The memory control can be facilitated in the reproduction process.

Further, in the present invention, the second code sequence is divided into a head frame arranged at the head of the sector packet and a succeeding frame arranged subsequent to the head frame, and the first frame and the succeeding frame are divided. Since a sync signal is added to the head, the first control data is moved immediately after the sync signal of the head frame, and the second control data is moved immediately after the sync signal of the subsequent frame.
In a system in which one sequence is divided into a plurality of frames and a sync signal is added to each of them, the reproduction process can be easily performed.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a data structure of a sector packet according to an embodiment of the present invention. The sector packet shown in the figure is 128B (bytes) x 16 rows of main data, 1B.
× 4 rows (0th to 3rd rows) of 4B sector address code
Data (ID), 1B × 6 rows (4th to 9th rows) of 6B sector address spare data (RSV), 1B × 2 rows (first
2B error correction parity of lines 0 to 11- (IE
C) 4B EDC, 8B ROW NO, 8B AU
20B other control data of X, total 2080B
The information data is composed of. That is, ID, RSV,
Each data of 16B in total of IEC and EDC is 144B × 1
In the encoded sequence of 6 rows, 1B is at the 129th column of each sequence.
It is distributed and arranged one by one. Further, a total of 16B of data of ROW NO and AUX is distributed and arranged by 1B in the 130th column.

Here, "predetermined control data" in the claims means ID, RSV, IEC, EDC, ROW N.
O, AUX, and "first control data" means ID,
RSV, IEC, EDC, "second control data"
Means ROW NO, AUX.

Further, ID is an address code of a sector packet, RSV is its spare code, IEC is these error correction codes, EDC is an error detection code corresponding to, for example, CRC, ROW NO is the line number of each line, and AU.
X refers to other control codes as defined later by the user.

The error correction parity (IEC) is generated in advance by forming an address error correction code sequence for a total of 10B of the sector address code (ID) and the sector address spare data (RSV). It is a thing.

In FIG. 1, Po and Pi are respectively a first error correction parity signal (outer code) described later,
The second error correction parity-signal (inner code).

Next, as shown in FIG. 2, a first error correction parity-signal (outer code) Po is generated and added in the above first error correction coded sequence. In FIG. 2, the data series are shown by arrows only for two series.

Here, a sector packet of 144B × 16 rows excluding the second error correction parity-signal (inner code) Pi is divided into 9 blocks with 16B × 16 rows as one block.

Next, as shown in FIG. 3, interleave processing is performed within each block. The arrow in FIG. 3 indicates a state in which the data sequence indicated by the arrow in FIG. 2 has been moved.

Next, as shown in FIG. 4, block interleave processing is performed. Block interleave processing is
Each sector packet divided into 9 blocks is passed through a column of block units, for example, as shown in FIG. 5, through 9 types of delay circuits having different delay amounts, and the sector configuration is dispersed in block units. As a result, the 9 blocks forming the sector packet of the first correction coded sequence are arranged diagonally.

Next, the sector packet (recording sector #n) formed in the uppermost stage is used as a second correction coded sequence of 16 rows to form a data sequence similar to the data sequence shown in FIG. On the other hand, the second error correction parity-signal (inner code) Pi is generated and added.

FIG. 6 shows the packet arrangement structure of this recording sector. As shown in the figure, the information data is in the same position as the data arrangement in the original packet sector after the intra-block interleaving and the block interleaving processing are performed. In FIG. 6, the numbers in parentheses are
It indicates how much the sector address code (ID), sector address spare data (RSV), error correction parity (IEC), etc. are displaced from the allocated block (one block is one unit). ing.

Then, the sector packet thus generated is transmitted or recorded with a sync signal and the like added as follows.

That is, as shown in FIG. 7, each row of a sector packet consisting of 16 rows is set to the head frame (Even).
Sync Frame and subsequent frame (Odd Sy)
ncFrame) and two frames.
As shown in FIG. 8, the first frame is
0.5B DC code (DCC), 1.5B sync signal (Sync), 1B first control data (I & E) and 11B information data, and 4 sets of 0.5B DC code (DCC) and 16B information data. As shown in FIG. 9, the succeeding frame has a direct current code (DCC) of 0.5B, a synchronization signal (Sync) of 1.5B, and a second control data of 1B (Row) from the beginning.
NO + AUX) and 11B information data, and 4 sets of 0.
It is composed of a 5B DC code (DCC) and 16B information data.

In short, in this embodiment, predetermined control data is dispersedly added to each data packet, and the control data is moved immediately after the synchronization signal. This improves the reliability of data and facilitates memory control in the reproduction process. Further, the second code sequence is divided into a head frame arranged at the head of the sector packet and a succeeding frame arranged subsequent to the head frame, and a synchronization signal is added to the head frame and the head of the succeeding frame. , The first control data is moved immediately after the sync signal of the first frame, and the second control data is moved immediately after the sync signal of the subsequent frame. Thus, in a system in which one stream is divided into a plurality of frames and a sync signal is added to each of them, the reproduction process is easily performed.

Next, the data forming apparatus according to the present invention will be described.

FIG. 10 is a diagram showing the structure of this data forming apparatus.

As shown in the figure, the information data multiplexing unit 1
Is a compressed video signal, an audio signal, a sub-video signal such as a caption, and a control signal used for synchronizing the video signal and the audio signal.
Organize so that stream transmission is possible.

The sector packet processing unit 2 has a selector S1.
The output of the information data multiplexing unit 1 selected by or the information file management data is input. The information file management data is control information management data relating to the compression style of the video signal, the stream number of the audio signal, the compression ratio, and the like as a whole. The sector packet processing unit 2 first transfers information file management data to one sector packet capacity (in this example,
Sector alignment to 2048 bytes) and generate a base array for serialization for subsequent error correction coding. Here, as shown in FIG. 11, a base array of sector packets of 128 bytes (or symbols) × 16 rows is formed. After generating the sector packet (base) of the management data, the sector packet processing unit 2 then connects the selector S1 to the information data multiplexing unit 1 side to generate the information data stream in which the sub video signal and the audio signal are multiplexed. Upon reception, a sector packet (base) array of 2048 bytes (128B × 16 rows) similar to the above is formed. When the sector packet processing unit 2 arranges 1 sector packet, the sector packet processing unit 2 outputs 128
A signal is sent to the delay unit 3 and the information data error detection code generation unit 4 in byte units.

The information data error detection code generation unit 4 generates an error detection code (IEC) in units of one sector.

On the other hand, when the information data error detection code generator 4 generates one IEC, the ID generation counter 5
The count signal is incremented by 1, an address signal (ID) of a sector packet corresponding to the IEC is generated, and a control signal related to the sector (SLI = content identification signal in sector packet unit)
Is sent to the ID error detection and correction code generation unit 6.

The ID error detection / correction code generation section 6 uses ID +
An error correction code IEC of SLI (selector control signal) is generated. Here, when the order of ID and SLI is selected by the selector S2 and the above IEC is generated, the selector S3 is selected.
As a result, it is sent to the outer code (Po) generation unit 7 that generates the outer code (Po) that is the first error correction code in 1-byte units, and the intra-block interleave circuit 8.

On the other hand, the information data is sent to the ID by the delay unit 3.
The transmission timing is adjusted to the transmission timing of + SLI + IEC + EDC, and the same is sent to the outer code (Po) generator 7 and the intra-block interleave processor 8.

Information data (128B) and signal 1 such as ID
The row number generation hexadecimal counter 9 performs an up-counting operation at the timing when B is sent to the outer code (Po) generation unit 7. First 128 of sector packet (base)
When B is transmitted, the line number generation hexadecimal counter 9 is set to "0".

The row number generation hexadecimal counter 9 transmits the value at that time together with the count operation as the check sequence number to the outer code (Po) generation section 7 and the intra-block interleave circuit 8 together with the information data and the ID signal. To do.

The outer code (Po) generator 7 receives the transmitted information data 128B, 1B such as an ID signal, and 1B from the line number generation hexadecimal counter 9 and the inner code (Pi) generator 1.
A 14-byte first error correction code is generated by 8B of the Pi signal generated by 0. In one sector packet,
16 sequences are generated. The array of sector packets at this time is shown in FIG.

The intra-block interleaving processing unit 8 uses P
128B × 16 rows of information data excluding the i signal, 1B × 16 rows of IDs, 1B × 16 rows of row numbers and outer code Po
The 14B × 16 rows of sector packet data of 144B × 16 rows are divided into 9 blocks of 16B × 16 rows, and interleave processing is performed in each block. FIG.
Shows the arrangement of typical raw data.

The intra-block interleaved data is subjected to block interleaving processing by a delay circuit 11 having a delay amount of 9 types.

The intra-block interleave and the block-interleaved data generate an internal code (Pi) which is a second error correction code, and an internal code (Pi) generation circuit 10
And the inner code (Pi) is generated.

152B × the sum of the data generated by the inner code generation circuit 10 and the output data of the delay circuit 11
The 16-row sector packet is input to the conversion / addition unit 12. Here, the output of the 129th column (first control data) of the delay circuit 11 is input to the first column of the conversion adding section 12, and the output of the 130th column (second control data) of the delay circuit 11 is converted. It is wired so as to be input to the 69th column of the addition unit 12. With such wiring, movement of control data according to the present invention is realized.

After that, the conversion adding unit 12 converts the parallel data of 152B into byte serial data, adds a synchronization signal (see FIGS. 7 to 9), and sends the data to the modulation circuit 13.

The modulation circuit 13 modulates this data into a signal suitable for transmission or recording processing, and transmits it bit-serially or records it on a medium such as an optical disk.

Next, the data reproducing apparatus according to the present invention will be described.

FIG. 14 is a diagram showing the structure of the data reproducing apparatus.

First, the reproducing apparatus shown in FIG. 14 receives a modulated signal transmitted or recorded on a recording medium. Upon receiving such a modulated signal, the reproducing apparatus sends it to the demodulation circuit 13 and detects the synchronization pattern with the synchronization signal detection circuit 14.

In the detection of the synchronization pattern, a code error occurs due to a defect or the like in the information data and a false synchronization signal is detected. Therefore, as a countermeasure against this, the synchronization window generator 15 causes the synchronization signal whose signal section is longer than the synchronization pattern. A detection window signal is generated, and the reproduction synchronization signal generator 16 inputs the synchronization detection signal and the synchronization signal detection window signal via the AND circuit 17 to generate a reproduction synchronization signal. Then, demodulation is performed based on this reproduction synchronization signal to prevent error synchronization.

The demodulation circuit 13 outputs an error correction code sequence based on the reproduction synchronizing signal generated as described above. The output of the demodulation circuit 13 is input to the inner code error detection / correction processing unit 18 via the serial / parallel conversion circuit 30.

Here, the output of the first column (first control data) of the serial / parallel conversion circuit 30 is the inner code error detection / correction processing unit 1.
8 is input to the 129th column, and the serial-parallel conversion circuit 30 has 69
The output of the second column (second control data) is the detection correction processing unit 18.
Are wired so as to be input to the 130 th column.
With such wiring, movement of control data according to the present invention is realized. That is, according to the present invention, the reliability of data can be improved only by performing such wiring processing.

The inner code error detection / correction processing unit 18 performs error detection / correction processing on the error correction code sequence output from the demodulation circuit 13 based on the second error correction code (inner code (Pi)).

The data subjected to the error detection / correction processing by the inner code (Pi) is sequentially sent to the sequence order compensation circuit 19. The inner code error detection / correction processing unit 18 outputs an inner code error flag when the error correction code sequence is uncorrectable data. After the error detection and correction process using the inner code,
The line number data is sent to the line number check circuit 20.
The row number check circuit 20 checks the row number data when the error symbol correction processing in the inner code error detection / correction processing is small, and the error code can be corrected in the inner code error detection / correction processing. Even if the number is large, when the ascending (or descending) relationship is confirmed in the two sequences before and after the sequence in the error detection / correction process, the line number data is checked, and in the inner code error detection / correction process, the above 2 Except for one case, presettable 16
The data of the binary counter 21 is checked. The row number check circuit 20 uses the above data to check whether the data is correctly sent in the sequence order, and if it is incorrect, sends a control signal to the sequence order compensation circuit 19 to correct the incorrect sequence.

The sequence order compensating circuit 19 uses n types of identification code addition order rules, performs unit division from the identification code determined to be correct and the order of the rules, and when the number of lines, which is the number of sequences in the unit, is small. It also has a function of adding a dummy series, removing a double series when the number of series is large, and setting the number of rows in the unit to n.

The presettable hexadecimal counter 21
Then, when the correct line number data is detected, that data is preset.

The output data from the sequence order compensation circuit 19 is
It is sent together with the error flag to the delay circuit 22 which performs the block deinterleave processing. The error flag is a flag that is set for a data packet that cannot be corrected by the inner code.

Next, the information data excluding the inner code (Pi) and the outer code (Po) are subjected to intra-block de-interleaving processing by the intra-block de-interleaving processing section 23,
The outer code (Po) error detection and correction processing unit 24 performs error detection and correction processing using the outer code. The outer code (P
In the error detection / correction processing by o), the uncorrectable error flag by the inner code is used as the error location instruction signal,
By allocating the parity signal to the error pattern generation, it is also used for erasure correction with improved correction capability.

The information data for which the error correction processing by the outer code is completed is output to the decoder circuit (not shown) via the sector packet processing unit 25. The decoder circuit outputs the information data to a decoder circuit that decodes the video signal and the audio signal.

Information data is received in recording sector units, data sector packets are formed by deinterleaving processing, and decoded into original data sector packets. A system for reproducing data recorded in a recording medium or the like. Then, while the reproduction data rate of the compressed video data or the like changes, the reading operation from the recording medium is performed by the completion operation. In this case, the disc etc. is constantly rotating,
It is necessary to use a buffer memory or the like to return the data reading point to the front when a certain amount is stored, and to read from the continuous portion of the last data read before when there is free space in the memory again. In this reproducing apparatus, such continuity of data is managed by the ID signal which is the address signal of the sector packet.

First, the ID signal portion is extracted from the output data of the sequence order compensating circuit 19, sent to the ID signal error correcting circuit 26 together with the uncorrectable error flag, and error correction processing is performed by the IEC parity signal. By this processing, the ID signal is only recorded in the recording sector, and (Pi) and (IE
Since the product code is composed of C), high correction capability can be provided.

The ID signal detected here is OUT-ID.
It is output via the detection circuit 29 and used for reading control from the recording medium.

When the ID signal is not detected by this correction processing, the ID control unit 28 determines the ID counter 2 as in the case of the row number.
Substitute using the output of 7. Unlike the line number, the ID counter 27 is a counter capable of counting the number of IDs of the recording medium or more, and when the ID correction circuit 26 detects a correct ID signal, the data is preset. In the above-described embodiment, the data interleaving process is described by taking the block interleaving process as an example. However, the present invention provides a similar system in a complete interleaving process or other data structure that does not depart from the gist of the present invention. Can be configured.

Further, as a medium on which data is recorded by the data structure according to the present invention, there are all kinds of storage media such as an optical disk, a magnetic disk, various memories and the like.

[0077]

As described above, according to the present invention,
The reliability of data can be improved, and memory control can be facilitated in the reproduction process. Further, in a system in which one sequence is divided into a plurality of frames and a sync signal is added to each of them, the reproduction process can be easily performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a data structure of a sector packet in an embodiment of the present invention.

FIG. 2 is a diagram for explaining generation of an outer code according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining inter-block interleaving according to an embodiment of the present invention.

FIG. 4 is a diagram for explaining block interleaving according to an embodiment of the present invention.

FIG. 5 is a diagram for explaining block interleaving according to an embodiment of the present invention.

FIG. 6 is a diagram showing a packet arrangement structure of a recording sector in an embodiment of the present invention.

FIG. 7 is a diagram showing a frame structure according to an embodiment of the present invention.

FIG. 8 is a diagram showing a frame structure according to an embodiment of the present invention.

FIG. 9 is a structural example of data in an embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a data forming apparatus according to the present invention.

11 is an example of a data structure after sector packet processing in the apparatus of FIG.

12 is a structural example of data to which a line identification code is added in the device of FIG.

13 is a diagram for explaining interleaving processing in the apparatus of FIG.

FIG. 14 is a block diagram showing the configuration of a data reproducing device according to the present invention.

[Explanation of symbols]

 1 ... Information data multiplexing unit 2 ... Sector packet processing unit 3 ... Delay device 4 ... Information data error detection code generation unit 5 ... ID generation counter 6 ... ID error detection correction code Generation unit 7 ... Outer code (Po) generation unit 8 ... In-block interleave processing unit 9 ... Line number generation hexadecimal counter 10 ... Inner code (Pi) generation unit 11 ... Delay circuit 12 Conversion conversion unit 13 Modulation circuit 14 Synchronization signal detection circuit 15 Synchronization window generation unit 16 Reproduction synchronization signal generation unit 17 AND circuit 18 Internal code error Detection / correction processing unit 19 ………… Sequential sequence compensation circuit 20 ………… Line number check circuit 21 ………… Presettable hexadecimal counter 22 ………… Delay circuit 23 ………… Internal block deinterleave processing unit 24 ………… Outside Sign (Po) Ri detection correction processing unit 25 ......... sector packet processor 30 ......... P converter

Claims (18)

[Claims] 1. A step of dividing data into data packets of a certain length, forming a sector packet composed of a plurality of divided data packets, and a step of adding predetermined control data to each data packet in a distributed manner. A step of generating a first error correction code of each data packet including data and forming a first code sequence formed by adding the data packet to each data packet; and a sector packet in which the first code sequence is overlapped in a division order, A step of performing interleaving processing by superimposing a plurality of stages, a step of generating a second error correction code of each series after the interleaving processing, and forming a second code series formed by adding to each series, a second code Adding a synchronization signal to the sequence and moving control data included in the second code sequence immediately after the synchronization signal. That data forming method. 2. A step of dividing data into data packets of a fixed length and forming a sector packet composed of a plurality of divided data packets, a step of adding predetermined control data to each data packet in a distributed manner, and a control A step of generating a first error correction code of each data packet including data and forming a first code sequence formed by adding the data packet to each data packet; and a plurality of sector packets in which the first code sequence is overlapped in a division order. Into blocks and perform intra-block interleaving in each block, and step of performing sector inter-block interleaving on each block by performing block interleaving on a block-by-block basis, and after block interleaving A second error correction code of each series is generated and added to each series. Forming a code sequence, with the addition of synchronization signals at the beginning of the second code sequence,
Moving the control data included in the second code sequence immediately after the synchronization signal. 3. The data forming method according to claim 2, wherein the original data divided into data packets and the control data are arranged in different blocks. 4. The data forming method according to claim 1, 2 or 3, wherein the control data includes first control data including address information of the sector packet and second control data including an encoding sequence number. A data forming method comprising: 5. The data forming method according to claim 4, wherein the second code sequence is divided into a head frame arranged at the head of the sector packet and a succeeding frame arranged after the head frame, Along with adding a synchronization signal to the beginning of the first frame and the subsequent frame, the first control data is moved immediately after the synchronization signal of the first frame, and the second control data is moved immediately after the synchronization signal of the subsequent frame. Characterizing data forming method. 6. The data forming method according to claim 5, wherein the first control data is arranged immediately after the synchronization signal of each head frame forming the sector packet in a unit of one symbol, and the second control data is arranged. A data forming method characterized by arranging one symbol immediately after the synchronization signal of each subsequent frame forming a sector packet. 7. A step of moving the control data arranged immediately after the synchronization signal added to the second code sequence to a predetermined position of the second code sequence, and each second code sequence for each second code sequence. Second added to the code sequence of
Error detection and correction processing using the error correction code of, and forming a sector packet from a plurality of data packets that have been subjected to error detection and correction processing, and performing a deinterleave processing by superposing these sector packets in multiple stages. A step of performing error detection and correction processing on each series after deinterleaving processing using a first error correction code added to each series, a data reproducing method comprising: 8. A step of moving the control data arranged immediately after the synchronization signal added to the second code sequence to a predetermined position of the second code sequence, and each second code sequence for each second code sequence. Second added to the code sequence of
Error detection and correction processing using the error correction code, and a sector packet is composed of a plurality of data packets that have been subjected to error detection and correction processing, and these sector packets are stacked in multiple stages and deinterleave processing is performed in block units. Steps to perform, steps to perform intra-block deinterleave processing in each block, and steps to perform error detection and correction processing using the first error correction code added to each series after the two deinterleave processings And a data reproducing method comprising: 9. Control data adding means for dividing data into data packets of a fixed length, forming sector packets composed of a plurality of divided data packets, and adding predetermined control data to each data packet in a distributed manner. A first error correction code is generated for each data packet to which the control data is added by the control data adding means, and a first code sequence is formed by adding each first error correction code to each data packet. First code sequence forming means, interleave processing means for performing interleave processing by superposing a plurality of sector packets in which the first code sequence is overlapped in a division order, and second error correction codes of each series after interleave processing. Second code sequence forming means for forming a second code sequence that is generated and added to each sequence, and a synchronization signal is added to the second code sequence. Together, the data forming apparatus characterized by comprising a control data moving means for moving the control data included in the second code sequence immediately following the synchronization signal. 10. Control data adding means for dividing data into data packets of a fixed length, forming sector packets composed of a plurality of divided data packets, and adding predetermined control data to each data packet in a distributed manner. A first error correction code is generated for each data packet to which the control data is added by the control data adding means, and a first code sequence is formed by adding each first error correction code to each data packet. First code sequence forming means, a sector packet in which the first code sequence is superposed in the division order is divided into a plurality of blocks, and inter-block interleaving processing means performs inter-block interleaving processing in each block, and intra-block interleaving processing A block that performs block interleave processing in block units by stacking multiple sector packets And a second code sequence forming means for generating a second error correction code of each sequence after the block interleaving process and forming a second code sequence formed by adding it to each sequence, A sync signal is added to the beginning of the code sequence of 2, and
And a control data moving unit that moves control data included in the second code sequence immediately after the synchronization signal. 11. The data forming apparatus according to claim 10, wherein the original data divided into data packets and the control data are arranged in different blocks. 12. The data forming apparatus according to claim 9, 10 or 11, wherein the control data includes first control data including address information of the sector packet and second control data including an encoding sequence number. A data forming device comprising: 13. The data forming apparatus according to claim 12, wherein the second code sequence is divided into a head frame arranged at the head of the sector packet and a succeeding frame arranged after the head frame. The control data moving means adds a synchronization signal to the heads of the first frame and the subsequent frame, moves the first control data immediately after the synchronization signal of the first frame, and moves the second control data to the next frame. A data forming device which moves immediately after a synchronization signal. 14. The data forming device according to claim 13, wherein the control data moving means disperses and arranges the first control data in units of one symbol immediately after the synchronization signal of each head frame forming the sector packet, A data forming apparatus, characterized in that second control data is dispersedly arranged in one symbol immediately after a synchronization signal of each subsequent frame forming a sector packet. 15. Control data moving means for moving the control data arranged immediately after the synchronization signal added to the second code sequence to a predetermined position of the second code sequence, and each control data moving means. Second error detection and correction processing means for performing error detection and correction processing by using the second error correction code added to each second code series, and a plurality of error detection and correction processing-executed Deinterleave processing means for constructing a sector packet from the data packets of (1) and performing deinterleaving processing by stacking these sector packets in a plurality of stages, and a first error correction code in which each series after deinterleaving processing is added to each series. A data reproducing apparatus comprising: a first error detection / correction processing unit which performs error detection / correction processing using the data reproduction apparatus. 16. A control data moving means for moving control data arranged immediately after a synchronization signal added to the second code sequence to a predetermined position of the second code sequence, and each of the control data moved means. Second error detection and correction processing means for performing error detection and correction processing by using the second error correction code added to each second code series, and a plurality of error detection and correction processing-executed Block deinterleave processing means for constructing a sector packet from the data packets of (1) and performing deinterleave processing in block units by stacking these sector packets in multiple stages, and in-block deinterleave processing means for performing in-block deinterleave processing And the first de-interleaved sequence is subjected to error detection and correction processing using the first error correction code added to each sequence. Data reproduction apparatus characterized by comprising an error detection and correction processing means. 17. A sector packet formed by stacking a plurality of data packets obtained by dividing data into a predetermined length, a synchronization signal arranged at a predetermined position of each data packet, and a distributed arrangement immediately after each synchronization signal. A storage medium comprising predetermined control data. 18. A data packet formed by dividing data into a fixed length is divided into a head frame and a subsequent frame arranged subsequent to the head frame, and a sector packet formed by stacking a plurality of these frames, and each head packet. A first synchronization signal arranged at a predetermined position of a frame, a second synchronization signal arranged at a predetermined position of each subsequent frame, and a distributed arrangement immediately after each first synchronization signal, and the sector packet Storage medium, which comprises: first control data including address information of the second control data; and second control data including a coding sequence number, which is distributed immediately after each second synchronization signal.