JPH08213918A - Data generating method, data generator, disk and data transmitter - Google Patents

Abstract

PURPOSE: To improve the error correction capability by generating a 1st error correction code of each series in a sector packet with a 2nd error correction code added to one-preceding sector packet so as to enhance the security of the 2nd error correction code. CONSTITUTION: In a first coding an external code 16 sequence of 152 symbols ×16 lines is generated by inserting, a 1st parity symbol of 14 symbols × 16 lines generated by an original data packet matrix 130 symbols × 16 lines and a 2nd parity symbol of 8 symbols × 16 lines having been generated just before by a 2nd coding means shown by 8 lines at the right end, to the 130-th to 143rd lines of the code 16 sequence. Since a 1st error correction code of each series in a sector with a 2nd error correction code added to one-preceding sector packet to the sector packet is generated, the 2nd error correction code is protected by the 1st error correction code and the error correction capability is more strengthened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data forming method for forming an error correction code suitable for digital data transmission and recording.

[0002]

2. Description of the Related Art As an error correction code used for transmission and recording of digital data, many methods and devices for product-coding an error-correcting code sequence such as Reed-Solomon code or for interleaving data before and after product-coding. Has been put to practical use.

Product coding of two series of error correction codes is performed by including each data symbol in two error correction codes so that even if one error correction code cannot be corrected, the other If the error correction code of can be corrected, it is possible to perform repeated correction based on the correction result. Further, by generating an erasure pointer in the other error correction code based on one uncorrectable error correction code, it is possible to perform erasure error correction with a large number of correction symbols. Therefore, conventionally, the product coding technique has been widely used. Further, data interleaving has the effect of lengthening the correctable burst error by dispersing the burst error, and is therefore used in most recording systems where burst errors are likely to occur.

However, in the conventional product coding technique of two series of error correction codes, the outer code (first error correction code) is protected by the inner code (second error correction code). Since the inner code (second error correction code) is not protected by any of them, the above-mentioned correction or the like may be performed when the second error correction code becomes uncorrectable. Can not.

Further, both of the product code structure and the data interleaving require a memory having a size corresponding to the product code structure length and the interleave length, and a control circuit for the product and the decoding device. Therefore, the product code having a long construction length and the code having a long interleave length, which have high error correction capability, have a drawback of complicating the apparatus. That is, the conventional product code constituent device with interleaving is, for example, as shown in FIG. 13, delay devices 53-1 and 53 for interleaving provided between error correction coding devices 51 and 52 of two systems. -2 ... Is set with different delay amounts in units of one symbol, so that the delay units 53-1 and 53-2, which have different delay amounts, are set to one code symbol length of the first error correction code system. It is necessary to use an equal number. Therefore, it is difficult to perform long interleaving between code sequences having a long code symbol length with improved error correction capability.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a system capable of enhancing the protection of the second error correction code and enhancing the error correction capability. Is intended.

It is another object of the present invention to provide a system capable of significantly reducing the complexity of hardware for processing a super large product code and interleave length.

[0008]

In order to solve such a problem, a data forming method of the present invention according to claim 1 divides data into data packets of a fixed length, and a sector packet composed of a plurality of divided data packets. And a second error correction code added to the sector packet immediately before the sector packet, the first error correction code of each series in the sector packet is generated, and each data packet is generated. To form a first code sequence, a sector packet in which the first code sequence is overlapped in a division order is overlapped by a plurality of stages to perform an interleave process, and a second sequence of each sequence after the interleave process is performed. Of the error correction code and adding it to each sequence to form a second code sequence.

According to a second aspect of the data forming method of the present invention, the step of dividing the data into data packets of a fixed length and forming a sector packet composed of a plurality of divided data packets, and one step before the sector packet. Second sector error correction code added to each sector packet to generate a first error correction code of each sequence in the sector packet and form a first code sequence added to each data packet. Step, and a step of performing intra-block interleaving processing on each sector packet in which the first code sequence is superposed in the division order; Step of performing interleave processing, and second error correction code of each sequence after block interleave processing Generated by and a step of forming a second code sequence which is obtained by adding to each series.

According to a third aspect of the data forming apparatus of the present invention, the data is divided into data packets of a fixed length, sector packet forming means for forming a sector packet composed of a plurality of divided data packets, and the sector packet forming means. A first code sequence generated by generating a first error correction code of each sequence in a sector packet formed by adding the second error correction code added to the preceding sector packet and adding the generated first error correction code to each data packet A first code sequence forming means, an interleave processing means for performing an interleave process by superposing a plurality of sector packets obtained by overlapping the first code sequence in the division order, and a second code of each sequence after the interleave process.
Second code sequence forming means for forming a second code sequence by generating the error correction code of and adding it to each sequence.

According to a fourth aspect of the present invention, there is provided a data forming device which divides data into data packets of a fixed length, and which constitutes a sector packet composed of a plurality of divided data packets, and sector packet forming means. A first code sequence generated by generating a first error correction code of each sequence in a sector packet formed by adding the second error correction code added to the preceding sector packet and adding the generated first error correction code to each data packet A first code sequence forming means for forming a block, a sector packet in which the first code sequence is superposed in the division order, an intra-block interleave processing means for performing an intra-block interleaving processing in each block, and an intra-block interleaving processing are performed. Block interleave processing that stacks multiple sector packets in multiple stages and performs block interleave processing in block units. Second forming and over blanking processing unit, the second code sequence which is obtained by adding to each sequence to generate a second error correcting code of each sequence after block interleaving
Code sequence forming means.

According to a fifth aspect of the present invention, data is divided into data packets of a fixed length, and a sector packet composed of a plurality of divided data packets and a sector packet immediately before the sector packet are added. Second
Error correction code is added for each series in a sector packet, and the first error correction code added to the sector packet and for each series after interleave processing are added to the sector packet. And a second error correction code.

According to a sixth aspect of the present invention, data is divided into data packets of a fixed length, and a sector packet composed of a plurality of divided data packets and a sector packet immediately before the sector packet are added. Second
Is generated for each series in a sector packet to which the error correction code of is added, and is generated for each series after the first error correction code added to the sector packet and intra-block interleave processing and block interleave processing, The second error correction code added to the sector packet.

According to a seventh aspect of the present invention, there is provided a data transmission device according to the present invention, wherein for any positive integer k, m, n, pi and a positive integer po smaller than k × m, (k × m-po) symbols. ×
An original data packet composed of n rows and a second of a pi symbol × n row structure generated and added by the second encoding means.
, And the first parity symbol of n rows is generated and added to obtain the code length (k ×
(m + pi) symbols, a set of first error correction code n series, and (k × m + pi) symbols × n rows of the first
Error-correcting code sequence forming the first correction code sequence and the encoded packet data forming the first correction code sequence and arranged in a matrix excluding a portion of pi symbols × n rows (k × m) A part of symbols × n rows is divided into k blocks each having a size of m symbols × n rows, and the divided k blocks are each one diagonal of a block matrix of k blocks × k rows. Block delay arranging means arranged as element blocks and a plurality of original data packets to be transmitted successively and sequentially are subjected to the first encoding and block delay arrangement while k blocks × 1 row, that is, block delay. From the (k × m) symbol × n-row matrix after arrangement, pi
A second parity symbol of symbol × n rows is generated and added to form a set consisting of a second error correction code n sequence having a code length of (k × m + pi) symbols, and (k × m
+ Pi) symbols × n rows of the second error correction code forming the second error correction code and the matrix symbol after the second error correction code sequence is formed by the second coding means in the row direction (k Xm + pi) n rows of each symbol are sequentially output and transmitted as final encoded packet data which is the second error correction code sequence.

The data transmission apparatus of the present invention according to claim 8 is the data transmission apparatus according to claim 7, wherein (k × m−p)
The symbol arrangement order of the original packet data composed of (o) symbols × n rows is (k × m-po) symbols × in the row direction.
It is characterized by having n rows. According to a ninth aspect of the present invention, there is provided the data transmission apparatus according to the seventh aspect, wherein the first error correction code n having a code length (k × m) symbol is used.
The first encoding means for forming the sequence is (k × m-po)
The original data packet matrix of symbols × n rows is included on the left end side (k × m) The row numbers of the matrix of symbols × n rows are 0 to n−
1, when the column number is changed from 0 to k × m−1, the row with the row number 0 is rotatably arranged in the row corresponding to the row number n, and is converted into a row circular matrix capable of handling the rows with the row numbers n and above. In line (k ×
(m-po) original data symbols are obtained by increasing the row number and the column number by 1 from the i-th row and 0-th column (i + k × m-).
Po-1) row (k × m-po-1) is converted and arranged, and the i-th first error correction code is incremented by one from the i-th row and 0-th column. Obtained by (i + k
(K × m-po-1) rows (k × m-po-1) up to (k)
× m-po) original data symbols and line numbers 0 to n
-1, the second parity symbol generated and added by the second encoding means rearranged from the row number k × m to k × m + po−1, and the second parity symbol of n rows is a row circular matrix. An (i + pi-1) row (k × m + p) obtained by increasing the row number and the column number by 1 from the i-th row (k × m)
i−1) columns are generated from pi second parity symbols up to i−1) columns, and po first parity symbols are generated, and (i +
Po from (k + m-po) rows (k * m-po) columns to (i + k * m-1) rows (k * m-1) columns obtained by increasing the row number and the column number by one. The first parity symbol is inserted and arranged to form a code.

A data transmission apparatus according to a tenth aspect of the present invention is the data transmission apparatus according to the ninth aspect, wherein when the first encoding means performs the first encoding after the block delay arrangement, It is characterized in that a result equivalent to that obtained by performing block delay arrangement after encoding is obtained.

The data transmission apparatus of the present invention according to claim 11 is the data transmission apparatus according to claim 7, wherein the code length (k ×
The second coding means for forming the second error correction code n sequence of (m + pi) symbols is (k × m) symbols after the block delay arrangement × pi second parity symbols for each row of n rows. A data transmission device, characterized in that.

According to a twelfth aspect of the present invention, there is provided the data transmission device according to the seventh aspect, wherein m is equal to n.

According to a thirteenth aspect of the present invention, in the data transmission apparatus according to the seventh aspect, the means for sequentially outputting and transmitting the second error correction code sequence as the final encoded packet data is the second error. The length of an integer fraction of (k × m + pi) symbols, which is the code length of one series of correction codes, is set to 1
It is characterized by constructing a synchronization frame as one unit.

A data transmission apparatus according to a fourteenth aspect of the present invention is the data transmission apparatus according to any one of the seventh to thirteenth aspects.
It is characterized by exchanging all row and column relationships.

[0021]

In the present invention, the first error correction code of each series in the sector packet is generated by adding the second error correction code added to the sector packet immediately before the sector packet. , The second error correction code has a structure protected by the first error correction code. Therefore, the error correction capability can be made stronger. Further, according to the present invention, the encoding or decoding processing, which has conventionally been increased in proportion to the constituent length of the product code and the interleave length, the size of the memory and the control circuit scale thereof is the same for each small block. By adopting an encoding method which requires only multiple times, it suffices if there are several types of circuit blocks that perform the same processing. That is, the interleave, which was conventionally performed in symbol units, is 1
A block interleave method is adopted in which one code sequence set is divided into multiple blocks and the blocks are interleaved.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be described below in detail with reference to the drawings.

First, the procedure of data formation according to the present invention will be described with reference to FIGS.

As shown in FIG. 1, the original data packet before encoding is (9 × 16-14) symbols × 16 from the left end.
It consists of lines. The data arrangement order in the original data packet matrix of 130 symbols × 16 rows is 130 symbols in the order from 0th column to 129th column in each row, which is arranged in the order from 0th row to 15th row. Further, the second parity symbol 8 symbols × 16 rows generated immediately before by the second encoding means described later is shown in the rightmost 8 columns in FIG. 1 for the first encoding.

In the first encoding, 14 symbols × 16 rows of the first parity symbol generated from 130 symbols × 16 rows of the original data packet matrix and the second parity symbol shown at the right end are arranged in 130 columns to 143 columns. Insert it in 1
An outer code 16 sequence of 52 symbols × 16 rows is formed.

The first code sequence is, for example, a 16-sequence Reed-Solomon (152, 138, 15) code,
The code words of each of the 16 sequences are formed as shown by the arrows in FIG.

Next, the original data packet excluding the second parity symbol and the first parity symbol 14 in FIG.
Row numbers 0 to 15 and column numbers 0 to 143 in a matrix of 4 symbols × 16 rows are set, and rows with row numbers 0 are rotatably arranged in rows corresponding to row numbers 16 to handle rows with row numbers 16 and above. I will.

Then, as shown in FIG. 2, i (0≤i≤
The symbol of the 15th row is obtained by increasing the row number and the column number by 1 from the i-th row and the 0-th column (i + 143) row 143.
Reposition up to the row.

Although FIG. 2 does not show the second parity symbol arranged at the right end to generate the first parity symbol, the arrow in FIG. 2 indicates the sequence of the rearranged first codeword. Shows. Therefore, the first parity symbol is generated by rearranging the symbols of the original data packet part of FIG. 1 as shown in FIG. 2 and then arranging the second parity symbol at the right end to form a sequence of code words having arrows. First to be
May be encoded.

In any case, the first code sequence is finally formed in such a manner that 16 codes are diagonally scanned in a matrix of 144 symbols × 16 rows as shown in FIG. Therefore, when the second code sequence is further crossed on the first code sequence for product encoding, the first code sequence is not included in the first code sequence.
All the 16 codes forming the code sequence of No. 1 periodically repeat the same diagonal scanning for every 16 symbol columns, which is the number corresponding to the number of rows of the matrix. Only one symbol in one code cannot be included in one code forming the second code sequence. Therefore, in order to further form the product code by intersecting the second code sequence on the first code sequence, the burst error correction capability is also increased.
Interleave the first code sequence. At this time, all 16 codes forming the first code sequence skillfully utilize the property of periodically repeating the same diagonal scanning for every 16 symbol columns, which is the number corresponding to the number of rows of the matrix. By performing block interleaving in which the unit is a block of 16 rows × 16 columns, a delay device, memory control,
The configuration of the device for forming the second code sequence is simplified.

That is, as shown in FIG.
16 symbols x 1 row, each size is 16 symbols x 1
Divide into 9 blocks of 6 rows, and divide the 9 divided blocks by a delay device to make a block including 0 columns in a block matrix of 9 blocks x 9 rows the first block at the upper left position. Place it as an element block.

Next, 9 blocks × 1 row, that is, after the block delay arrangement (9 A set of 16 second error-correcting codes each having a code length of (9 × 16 + 8) symbols by adding a second parity symbol of 8 symbols × 16 rows to a matrix of × 16) symbols × 16 rows. And nothing,
An inner code (second error correction code) sequence of 152 symbols × 16 rows is formed. The second code (inner code) sequence thus formed is 152 symbols × 16 in FIG.
It is indicated by a frame of rows, and is, for example, a 16-series Reed-Solomon (152, 144, 9) code. The calculation of this sequence is performed row by row, and 14 rows of 152 symbols are sequentially output and transmitted as final encoded packet data in the row direction.

FIG. 4 shows a basic configuration example of an apparatus for performing the first encoding (formation of outer code sequence) to the second encoding (formation of inner code sequence) described above.

In FIG. 4, original data packets of 130 symbols × 16 rows are sequentially input to the first encoder 41 one packet at a time, and at the same time, the second parity (added by the second encoder) ( The inner code parity) is also input after being delayed by 16 rows by the inner code feedback delay device 42.

In the first encoding device 41, 14 columns × 16 rows of outer code parity are also diagonally generated and inserted while diagonally rearranging the original symbol matrix according to the first encoding procedure. An outer code sequence of columns × 16 rows is formed. 144 columns × 16 consisting of the original symbol matrix of this outer code sequence and the parity part of the generated and inserted outer code
The row is divided into 16 blocks each having 16 columns × 16 rows, and each block is divided into nine blocks with block numbers 0 to 8, and the delay amount is set to (block number × 16 rows) for each block. Be led to. Since the delay amount of the block number 0 is 0 in practice, eight delay units 43-1 and 43-1 are shown in FIG.
Only 43-2 ... are shown. In this way, the nine blocks appearing at the same time in the output of the delay device after each block undergoes different delays, and one block is included from each of the nine outer code sequences. The constructed symbol matrix is completed after all 9 outer code sequences are block-interleaved.
Obviously it will be the same as row 6.

Then, the symbol matrix of 144 columns × 16 rows is input to the second encoding device 44, and the inner code parity 8 by the row direction operation according to the second encoding procedure is used.
Column × 16 rows are added to form an inner code sequence of 152 columns × 16 rows.

Also, the inner code parity of 8 columns × 16 rows is fed back to the first coding device 41 after being delayed by 16 rows by the inner code feedback delay unit 42 to generate the next outer code. To be done.

In this embodiment, one line of 152 symbols, which is the length of one inner code, is finally halved.
A sync frame having 76 symbols of a length of 1 as one unit is constructed and transmitted. The 76-symbol synchronization frame has a structure having a frame synchronization signal (SYNC) at its head as shown in FIG. 5, for example.

The relationship between rows may be reversed from that in the above embodiment.

Next, the above data forming apparatus will be described more specifically with reference to FIG.

As shown in the figure, the information data multiplexing unit 1
Is a compressed video signal, an audio signal, a sub-video signal such as a caption, and a control signal used for synchronizing the video signal and the audio signal.
Organize so that stream transmission is possible.

The sector packet processing unit 2 has a selector S1.
The output of the information data multiplexing unit 1 selected by or the information file management data is input. The information file management data is control information management data relating to the compression style of the video signal, the stream number of the audio signal, the compression ratio, and the like as a whole. The sector packet processing unit 2 first transfers information file management data to one sector packet capacity (in this example,
Sector alignment to 2048 bytes) and generate a base array for serialization for subsequent error correction coding. Here, as shown in FIG. 7, a base array of sector packets of 128 bytes (or symbols) × 16 rows is formed. After generating the sector packet (base) of the management data, the sector packet processing unit 2 then connects the selector S1 to the information data multiplexing unit 1 side to generate the information data stream in which the sub video signal and the audio signal are multiplexed. Upon reception, a sector packet (base) array of 2048 bytes (128B × 16 rows) similar to the above is formed. When the sector packet processing unit 2 arranges 1 sector packet, the sector packet processing unit 2 outputs 128
A signal is sent to the delay unit 3 and the information data error detection code generation unit 4 in byte units.

The information data error detection code generation unit 4 generates an error detection code (IEC) in units of one sector.

On the other hand, when the information data error detection code generator 4 generates one IEC, the ID generator counter 5
The count signal is incremented by 1, an address signal (ID) of a sector packet corresponding to the IEC is generated, and a control signal related to the sector (SLI = content identification signal in sector packet unit)
Is sent to the ID error detection and correction code generation unit 6.

The ID error detection / correction code generation unit 6 uses ID +
An error correction code IEC of SLI (selector control signal) is generated. Here, when the order of ID and SLI is selected by the selector S2 and the above IEC is generated, the selector S3 is selected.
As a result, it is sent to the outer code (Po) generation unit 7 that generates the outer code (Po) that is the first error correction code in 1-byte units, and the intra-block interleave circuit 8.

On the other hand, the information data is sent to the ID by the delay unit 3.
The transmission timing is adjusted to the transmission timing of + SLI + IEC + EDC, and the same is sent to the outer code (Po) generator 7 and the intra-block interleave processor 8.

Information data (128B) and signal 1 such as ID
The row number generation hexadecimal counter 9 performs an up-counting operation at the timing when B is sent to the outer code (Po) generation unit 7. First 128 of sector packet (base)
When B is transmitted, the line number generation hexadecimal counter 9 is set to "0".

The row number generation hexadecimal counter 9 transmits the value at that time together with the count operation as the check sequence number to the outer code (Po) generation section 7 and the intra-block interleave circuit 8 together with the information data and the ID signal. To do.

The outer code (Po) generator 7 receives the transmitted information data 128B, 1B such as an ID signal, and 1B from the line number generation hexadecimal counter 9 and the inner code (Pi) generator 1.
8B of the Pi signal generated by 0 and delayed by 16 rows by the inner code feedback delay device 42, the first of 14 bytes
Error correction code is generated. 1 in 1 sector packet
Six sequences are generated. The array of sector packets at this time is shown in FIG.

The intra-block interleaving processing unit 8 uses P
128B × 16 rows of information data excluding the i signal, 1B × 16 rows of IDs, 1B × 16 rows of row numbers and outer code Po
The 14B × 16 rows of sector packet data of 144B × 16 rows are divided into 9 blocks of 16B × 16 rows, and interleave processing is performed in each block. FIG. 9 shows a typical arrangement of original data.

The interleaved data in the block is subjected to block interleaving processing by a delay circuit 11 having a delay amount of 9 types.

The intra-block interleave and the block-interleaved data generate an internal code (Pi) which is a second error correction code.
And the inner code (Pi) is generated.

In the sector packet of 152B × 16 rows in which the data sent to the inner code generation circuit 10 and the inner code (Pi) are combined, the conversion addition unit 12 converts the parallel data of 152B into byte serial data, and A frame sync signal is added to a series (row = or one row is divided into a plurality of frames) as a frame and is sent to the modulation circuit 13.

The modulation circuit 13 modulates this data into a signal suitable for transmission or recording processing, and transmits it in bit serial or records it on a medium such as an optical disk.

Next, the data reproducing apparatus according to the present invention will be described.

FIG. 10 is a diagram showing the structure of this data reproducing apparatus, and FIGS. 11 and 12 are diagrams showing the timing of various signals in this apparatus.

First, the reproduction apparatus shown in FIG. 10 receives a modulated signal transmitted or recorded in a recording medium. When the reproducing apparatus receives such a modulated signal (a),
The sync signal is sent to the demodulation circuit 30 and the sync pattern is detected by the sync signal detection circuit 14.

In the detection of the synchronization pattern, a code error occurs in the information data due to a defect or the like, and a false synchronization signal is detected. Therefore, as a countermeasure against this, the synchronization window generator 15 causes the synchronization signal having a longer signal section than the synchronization pattern. The detection window signal (c) is generated, and the reproduction synchronization signal generation unit 16 inputs the synchronization detection signal (b) and the synchronization signal detection window signal (c) via the AND circuit 17 to generate the reproduction synchronization signal (d). To do. Then, demodulation is performed based on the reproduction synchronization signal (d) to prevent error synchronization.

By the way, the relationship among the modulation signal (a), the synchronization detection signal (b) and the synchronization signal detection window signal (c) is as shown in FIG. 11, and such a synchronization signal detection window signal is used. In the error synchronization processing method, the synchronization signal detection window signal cannot be synchronized forever if the synchronization signal detection window signal is separated from the synchronization signal by a certain distance or more. Therefore, in this embodiment, when synchronization cannot be performed for a certain period of time, the synchronization signal detection window signal is opened and only the first synchronization signal is unconditionally used as the synchronization signal. The (c ′) portion of the sync signal detection window signal (c) in FIG. 11 is a window signal created because it is opened.

The demodulation circuit 13 outputs an error correction code sequence based on the reproduction synchronizing signal (d) generated as described above.

The inner code error detection / correction processing unit 18 performs error detection / correction processing on the error correction code sequence output from the demodulation circuit 13 based on the second error correction code (inner code (Pi)).

The data (e) which has been subjected to the error detection and correction processing by the inner code (Pi) is sequentially sent to the sequence order compensation circuit 19. The inner code error detection and correction processing unit 18 outputs an inner code error flag (f) when the error correction code sequence is uncorrectable data. After the error detection and correction processing using the inner code, the row number data (g) is sent to the row number check circuit 20.

The line number check circuit 20 checks the line number data (g) when the error symbol correction process is small in the above inner code error detection and correction process, and the correction process is possible in the inner code error detection and correction process. However, even when the number of error symbols is large, the ascending (or descending) relationship in the error detection and correction process is 2 before and after the sequence.
When it is confirmed in the sequence, the line number data (g) is checked, and in the inner code error detection and correction process, the data (h) of the presettable hexadecimal counter 21 is checked except for the above two cases. The row number check circuit 20 uses the above data to check whether the data is correctly sent in the sequence order, and if it is incorrect, sends the control signal (k) to the sequence order compensation circuit 19 to correct the incorrect sequence.

The sequence order compensating circuit 19 uses n kinds of identification code addition order rules and performs unit division from the identification code determined to be correct and the rule order. When the number of lines in the unit is small, It also has a function of adding a dummy series, removing a double series when the number of series is large, and setting the number of rows in the unit to n.

The presettable hexadecimal counter 21
Then, when the correct line number data is detected, that data is preset.

By the signal (k), the sequence order compensation circuit 1
The output data (i) of 9 also has the correct number of sequences in the correct sequence order, and it is possible to maximize the ability of the error detection and correction processing by the outer code thereafter. In the example of FIG. 12, the 13th series of data in the output data (i) is replaced with the correct data again, and the number of series is also corrected to the correct relationship. As a result, the output data (i) from the sequence order compensation circuit 19 has the correct number of sequences in the correct sequence order, and is sent to the delay circuit 22 that performs block deinterleave processing together with the error flag (j). The error flag (j) is a flag set for a data packet that cannot be corrected by the inner code.

Next, the information data excluding the inner code (Pi) and the outer code (Po) are subjected to intra-block de-interleaving processing by the intra-block de-interleaving processing unit 23,
The outer code (Po) error detection and correction processing unit 24 performs error detection and correction processing using the outer code. The outer code (P
In the error detection and correction processing by o), the uncorrectable error flag (j) by the inner code is used as the error location instruction signal, and the parity signal is used for error pattern generation, which is also used for erasure correction with improved correction capability. To be done.

The information data for which the error correction processing by the outer code is completed is output to the decoder circuit (not shown) via the sector packet processing unit 25. The decoder circuit outputs the information data to a decoder circuit that decodes the video signal and the audio signal.

By the way, the information data is received by the recording sector unit, the data sector packet is formed by the deinterleaving process, and the original data sector packet is decoded. However, the system for reproducing the data recorded on the recording medium or the like. Then, while the reproduction data rate of the compressed video data or the like changes, the reading operation from the recording medium is performed by the completion operation. In this case, the disc etc. is constantly rotating,
It is necessary to use a buffer memory or the like to return the data reading point to the front when a certain amount is stored, and to read from the continuous portion of the last data read before when there is free space in the memory again. In this reproducing apparatus, such continuity of data is managed by the ID signal which is the address signal of the sector packet.

First, the ID signal portion is extracted from the output data of the sequence order compensating circuit 19, is sent to the ID signal error correcting circuit 26 together with the uncorrectable error flag, and the IEC parity signal is used for error correction processing. By this processing, the ID signal is only recorded in the recording sector, and (Pi) and (IE
Since the product code is composed of C), high correction capability can be provided.

The ID signal detected here is OUT-ID.
It is output via the detection circuit 29 and used for reading control from the recording medium.

When the ID signal is not detected by this correction processing, the ID control unit 28 determines the ID counter 2 as with the line number.
Substitute using the output of 7. Unlike the line number, the ID counter 27 is a counter capable of counting the number of IDs of the recording medium or more, and when the ID correction circuit 26 detects a correct ID signal, the data is preset. This relationship is shown in (i ′) (j ′) (m) (n) of FIG.
It shows in (o). As a matter of course, after the output data is corrected with the ID signal for the sector packet by the Pi and Po codes,
The correction process can be performed again with the IEC code.

[0073]

As described above, according to the present invention, the second
Since the error correction code of 1 has a structure protected by the first error correction code, the error correction capability can be made stronger. In addition, the complexity of the hardware that processes extremely large product codes and interleave lengths can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining generation of an outer code according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining inter-block interleaving according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining block interleaving according to an embodiment of the present invention.

FIG. 4 is a diagram showing a basic configuration of a data forming apparatus of the present invention.

FIG. 5 is a diagram showing a configuration of a physical sector according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a data forming apparatus according to the present invention.

7 is a structural example of data after sector packet processing in the apparatus of FIG.

8 is a structural example of data to which a line identification code is added in the device of FIG.

9 is a diagram for explaining an interleaving process in the apparatus of FIG.

FIG. 10 is a block diagram showing the configuration of a data reproducing device according to the present invention.

11 is a diagram showing timings of various signals in the apparatus of FIG.

12 is a diagram showing timings of various signals in the apparatus of FIG.

FIG. 13 is a diagram showing a configuration of a conventional data forming device.

[Explanation of symbols]

 1 ... Information data multiplexing unit 2 ... Sector packet processing unit 3 ... Delay device 4 ... Information data error detection code generation unit 5 ... ID generation counter 6 ... ID error detection correction code Generation unit 7 ... Outer code (Po) generation unit 8 ... In-block interleave processing unit 9 ... Line number generation hexadecimal counter 10 ... Inner code (Pi) generation unit 11 ... Delay circuit 12 Conversion conversion unit 13 Modulation circuit 14 Synchronization signal detection circuit 15 Synchronization window generation unit 16 Reproduction synchronization signal generation unit 17 AND circuit 18 Internal code error Detection / correction processing unit 19 ………… Sequential sequence compensation circuit 20 ………… Line number check circuit 21 ………… Presettable hexadecimal counter 22 ………… Delay circuit 23 ………… Internal block deinterleave processing unit 24 ………… Outside Sign (Po) Ri detection correction processing unit 25 ......... sector packet processor 41 ......... Intra feedback delay device

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H04L 1/00 F 12/56

Claims (14)

[Claims] 1. A step of dividing data into data packets of a fixed length and forming a sector packet composed of a plurality of divided data packets, and a second error added to a sector packet immediately preceding the sector packet. Generating a first error correction code of each sequence in a sector packet to which a correction code is added and forming a first code sequence added to each data packet; and dividing the first code sequence in a division order. A step of performing an interleave process by superposing a plurality of overlapped sector packets, and a step of generating a second error correction code of each sequence after the interleave process and forming a second code sequence that is added to each sequence And a data forming method comprising: 2. A step of dividing data into data packets of a fixed length and forming a sector packet composed of a plurality of divided data packets, and a second error added to the sector packet immediately before the sector packet. Generating a first error correction code of each sequence in a sector packet to which a correction code is added and forming a first code sequence added to each data packet; and dividing the first code sequence in a division order. The step of performing intra-block interleaving processing on the overlapped sector packets within each block, the step of superposing multiple steps of the sector packets subjected to intra-block interleaving processing and performing block interleaving processing on a block-by-block basis, and after the block interleaving processing The second error correction code of each series of is generated and added to each series. Data forming method characterized by comprising the steps of forming a No. series. 3. A sector packet forming means for dividing data into data packets of a fixed length and forming a sector packet composed of a plurality of divided data packets, and a sector packet added to the sector packet one before the sector packet. A first code sequence forming means for generating a first error correction code of each sequence in a sector packet formed by adding 2 error correction codes and forming a first code sequence formed by adding it to each data packet; , Interleave processing means for performing interleave processing by stacking a plurality of sector packets in which the first code sequence is superposed in the division order, and second error correction codes of each sequence after interleave processing are generated and added to each sequence. And a second code sequence forming means for forming a second code sequence formed by: 4. A sector packet forming means for dividing data into data packets of a fixed length and forming a sector packet composed of a plurality of divided data packets, and a sector packet added to the sector packet one before the sector packet. A first code sequence forming means for generating a first error correction code of each sequence in a sector packet formed by adding 2 error correction codes and forming a first code sequence formed by adding it to each data packet; , A sector packet in which the first code sequence is superposed in the order of division is intra-block interleave processing means for performing inter-block interleaving processing in each block, and sector packets for which intra-block interleaving processing has been performed are superposed in a plurality of stages to make block unit Block interleave processing means for performing block interleave processing in Second code sequence forming means for generating a second error correction code of each sequence after the sub-processing and forming a second code sequence added to each sequence, Forming equipment. 5. A data packet is divided into data packets of a certain length, and a sector packet composed of a plurality of divided data packets and a second error correction code added to the sector packet immediately before the sector packet are added. The first error correction code generated for each sequence in the sector packet and added to the sector packet, and the second error correction code generated for each sequence after the interleaving process and added to the sector packet A disc comprising: a code; 6. A data packet is divided into data packets of a certain length, and a sector packet composed of a plurality of divided data packets and a second error correction code added to the sector packet immediately before the sector packet are added. The first error correction code generated for each series in the sector packet and added to the sector packet, and generated for each series after intra-block interleaving processing and block interleaving processing and added to the sector packet. A second error correction code, and a disk. 7. Arbitrary positive integers k, m, n, pi and k
(K × m-po) for positive integer po smaller than × m
An original data packet composed of symbols × n rows, and a second
From the pi symbol × n-row-configured second parity symbol generated and added by the coding means of ## EQU1 ## to generate and add a po symbol × n-row first parity symbol, and a code length (k × m + pi) First error correction code n of symbol
No set of sequences, (k × m + pi) symbols ×
first encoding means for forming a first error correction code sequence of n rows, and a portion of pi symbols × n rows of the encoded packet data arranged in a matrix to form the first correction code sequence (K × m) symbols × n rows except for k are divided into k blocks each having a size of m symbols × n rows, and the divided k blocks are k blocks × k rows block matrix. Block delay arranging means for arranging as one diagonal element block of, and k blocks of a plurality of original data packets to be sequentially and sequentially transmitted while sequentially performing the first encoding and block delay arrangement. From one row, that is, (k × m) symbols after block delay arrangement × n-row matrix, pi symbols ×
A second parity symbol of n rows is generated and added to form a set of the second error correction code n series each having a code length of (k × m + pi) symbols, and (k × m + pi) symbols × n rows of Second coding means for forming a second error correction code, and matrix rows after forming the second error correction code sequence by the second coding means are arranged in n rows by (k × m + pi) symbols in the row direction. Means for sequentially outputting and transmitting the minutes as final encoded packet data which is the second error correction code sequence. 8. The data transmission device according to claim 7, wherein the symbol arrangement order of the original packet data composed of (k × m-po) symbols × n rows is (k × m-p) in the row direction.
o) A data transmission device characterized in that it has a symbol × n rows. 9. The data transmission device according to claim 7, wherein the first coding means for forming the first error correction code n sequence having the code length (k × m) symbols is (k × m-po) symbols. The original data packet matrix of × n rows is included on the left end side (k
Xm) the row numbers of a matrix of n × n symbols from 0 to n−1,
When the column number is changed from 0 to k × m−1, the row having the row number 0 is rotatably arranged in the row corresponding to the row number n, and is converted into a row circular matrix capable of handling the rows having the row numbers n and above. Of (k × m-
po) original data symbols are obtained by increasing the row number and the column number by 1 from the i-th row and 0-th column (i + k × m−po).
-1) Convert and arrange at the position of row (k × m-po-1) column,
The i-th first error correction code is obtained by increasing the row number and the column number by 1 from the i-th row and 0-th column (i + k × m).
-Po-1) rows (kxm-po-1) up to (kxm)
-Po) original data symbols and line numbers 0 to n-
1. Pi symbol generated by the second encoding means rearranged from the row number k × m to k × m + po−1 and the second parity symbol of n rows × i is formed as a row circular matrix i (I + pi−1) row (k × m + pi) obtained by incrementing the row number and the column number by 1 from the row (k × m) column
-1) Generates po first parity symbols from pi second parity symbols up to (-1) columns, and (i +
Po from (k + m-po) rows (k * m-po) columns to (i + k * m-1) rows (k * m-1) columns obtained by increasing the row number and the column number by one. A data transmission device characterized by inserting and arranging as a first parity symbol of the above to form a code. 10. The data transmission device according to claim 9, wherein when the first encoding means performs the first encoding after the block delay arrangement, the first encoding means performs the block delay arrangement after the first encoding. A data transmission device characterized in that a result equivalent to that of the above is obtained. 11. The data transmission device according to claim 7, wherein the second coding means for forming a second error correction code n sequence having a code length (k × m + pi) symbols is (k) after the block delay arrangement. × m) A data transmission device characterized by adding pi second parity symbols for each row of (symbols × n) rows. 12. The data transmission device according to claim 7, wherein m is equal to n. 13. The data transmission device according to claim 7, wherein the means for sequentially outputting and transmitting the second error correction code sequence as final encoded packet data has a code length of one second error correction code sequence (k. Xm + pi) A data transmission device, characterized in that it forms a synchronization frame in which the length of an integer fraction of a symbol is one unit. 14. The data transmission device according to claim 7, wherein all row and column relationships are exchanged.