JP3304217B2 - Error correction coding circuit, error correction decoding circuit, error correction coding / decoding circuit, and digital device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction coding circuit, an error correction decoding circuit, an error correction coding / decoding circuit using a product code as an error correction code, and a digital communication apparatus using the same. The present invention relates to a digital recording device.

[0002]

2. Description of the Related Art Digital communication systems include digital communication systems and digital broadcasting systems that transmit digital data such as images and sounds over a communication line or wirelessly.

[0003] Digital recording devices include a magnetic tape device, a magnetic disk device, and an optical disk device.

In the above-mentioned digital storage device or digital communication device, an error correction technique is used as a technique for securing data reliability.

[0005] Error correction refers to an error occurring in data, for example, in the case of a digital recording device, a recorded bit "1".
Is reproduced to '0' or '0' to '1'.

[0006] In general, errors occurring in a digital recording device or a digital communication device include two types of errors, a random error and a burst error.

[0007] Here, a random error is an error that appears on a bit basis almost at random, whereas a burst error is an error that occurs continuously over a plurality of bits for a certain period.

One of the coding methods for efficiently correcting such two types of errors is to arrange information (data) in a two-dimensional array and perform error correction coding in different directions a plurality of times. Methods for performing are known.

For example, as an example of double encoding in which error correction encoding is performed twice, there is a product code used in a digital VTR or the like.

[0010] The product code means that information is arranged in a two-dimensional array,
Double error correction coding is performed in two vertical and horizontal directions.

Hereinafter, the procedure of product code encoding and its correction capability will be briefly described taking a digital VTR as an example.

In a digital VTR, a Reed-Solomon code is used as an error correction code.

The Reed-Solomon code is an error correction code for correcting a plurality of bits as one symbol and correcting in symbol units. For example, a digital VTR for business uses a Reed-Solomon code having eight bits as one symbol.

In the Reed-Solomon code, when the parity added to the information is 2t symbols, up to t symbols can be corrected if the position of the error is not known, and up to 2t symbols if the position of the error is known in advance.

The correction when the error position is unknown is called random correction, and the correction when the error position is known in advance is called erasure correction.

The details of the Reed-Solomon code are described in "Code Theory" by Hideki Imai (IEICE, 19th edition).
90).

FIG. 22 is a diagram for explaining a method of encoding a product code.

Hereinafter, a method of encoding a product code will be described with reference to FIG.

As an example of the product code, the C1 code is (n1, k
1) RS code and C2 code are examples of (n2, k2) RS code.

Here, the (n, k) RS code is a Reed-Solomon code having a code length of n and the number of information symbols is k.

First, information to be recorded is arranged in a two-dimensional array (k1 symbols × k2 symbols) as shown in FIG.

Here, one of the grids in FIG. 22 corresponds to one symbol.

Next, C2 code error correction coding is performed in the vertical direction, and (n2-k2) symbol parity is added.
Generate a code word of the (n2, k2) RS code.

Next, the C1 code is coded in the horizontal direction, (n1-k1) symbol parity is added, and (n1,
k1) Generate a code word of the RS code.

The symbol of the (n1 × n2) symbol obtained by the two-stage encoding of the C1 code and the C2 code is a product code.

Hereinafter, in the present specification, a two-dimensional block of (n1 × n2) symbols is referred to as a product code block.

The data of the product code block obtained by such encoding is usually recorded on the magnetic tape in the direction of the arrow in the figure in order from the upper row, using the code word of the C1 code as a unit.

On the other hand, at the time of reproduction, data continuously reproduced from the magnetic tape is arranged in a two-dimensional array in the same order as the data at the time of recording, and error correction decoding is performed in the order of C1 code and C2 code.

In the C1 code, the parity number is (n1-k)
1) Since it is a symbol, the number of symbols that can be corrected is a maximum of (n1-k1) / 2 symbols.

Further, an error detection flag is set for all symbols of the code word that could not be corrected by the error correction decoding of the C1 code.

In the error correction decoding of the C2 code, the number of error detection flags added at the time of decoding the C1 code is (n2-k).
2) When the number is equal to or less than the number, the erasure correction is performed with the error detection flag position as the error position.

In the C2 code, the parity number is (n2-k)
2), the maximum (n2-k) can be obtained by erasure correction.
2) Up to symbols can be corrected.

Continuous on the magnetic tape ((n2-k2)
× n1) The error of the symbol is (n2−
k2) Since it is a symbol error, it can be corrected.

That is, the product code can correct a burst error of ((n2-k2) × n1) symbols generated on the magnetic tape.

When the number of error detection flags is (n2-k)
2) If the number exceeds 2, random correction is performed as in the case of the C1 code.

In the coding method of the product code, a method of improving the error correction efficiency without changing the configuration of the product code block has been conventionally known.

Without changing the structure of the product code block,
A conventional method for further improving the error correction capability will be briefly described below.

First, N (N is an integer of 2 or more) product code blocks are arranged in the horizontal direction as shown in FIG. 23, and data is recorded on the magnetic tape in the direction of the arrow in the figure in order from the top.

In this way, the data of the code word of the C1 code of the different product code blocks is recorded continuously.

This is equivalent to performing data rearrangement in C1 codeword units between different product code blocks.

By this data rearrangement, continuous burst errors on the magnetic tape are distributed to N product code blocks, and the length of the burst error is apparently 1 / N in each product code block.

For example, if (n1 ×
A burst error having a symbol length of N) is a burst error of n1 symbols in each product code block.

Therefore, the length of the burst error that can be corrected is N times ((n2-k2) .times.n1.times.N) symbols when data of each product code block is collectively recorded.

That is, the data rearrangement in units of code words makes it possible to more effectively utilize the ability of the product code to correct burst errors.

[0045]

In the above-described conventional data rearranging method, data is rearranged in units of codewords of the C1 code. This rearrangement has a length exceeding the code length of the C1 code. Burst errors can be spread over multiple product code blocks.

However, since the codewords are rearranged collectively, burst errors having a length equal to or less than the code length generated in the codeword of the C1 code are not dispersed.

Therefore, the conventional method cannot always sufficiently utilize the correction capability of the error correction code, and may not be able to obtain a target error rate.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide an error correction coding circuit / error correction decoding circuit with a code length of C1 code. An object of the present invention is to provide a technique capable of efficiently performing error correction for a short length burst error.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0050]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) Regarding information data arranged in a (k1 × k2) two-dimensional array, C2 of (n2, k2) (where n2 is a code length) is set for each of k2 information symbols in each column.
In addition to performing error correction coding using two codes, (n1, k1) (where n1
1 is a code length), and performs error correction encoding using a C1 code.
A product code generating means for generating a product code composed of (n1 × n2) symbols; and N codewords (N is one of a plurality of C1 codewords included in the product code of the (n1 × n2) symbol) K (1 ≦ K <n) code words of 2 or more integers
The present invention is characterized by comprising a data rearranging means for performing data rearrangement with the continuous symbol of 1) as one unit and forming N new data strings composed of n1 symbols.

(2) In the means (1), the N
The codewords are included in at least two or more different product codes.

(3) In the means of (1) or (2), an ID information adding means for adding information relating to the data rearrangement of the new data string is further provided.

(4) In the means (1) to (3), the data rearranging means includes at least a plurality of memories and a control unit for controlling writing / reading of the plurality of memories. Based on the control of the control unit, N (N is an integer equal to or greater than 2) codewords of N (N is an integer of 2 or more) among C1 codewords of the product code of the (n1 × n2) symbol are used.
<K <n1) consecutive symbols are written in a plurality of memories in the order of rearrangement of data, and data is read from the plurality of memories to form N new data strings composed of n1 symbols. And

(5) N (N is an integer of 2 or more) out of n1 rows of a data block composed of (n1.times.n2) symbols encoded by the means (1) to (4). Data rearranging means for performing data rearrangement using K (1 ≦ K <n1) continuous symbols as a unit in the data sequence of (1) and reproducing a product code composed of the original (n1 × n2) symbols. And the reproduced (n1 × n
In the product code of the symbol 2), error correction decoding of the C1 code is performed for each of k2 rows, and C2 is performed for each of the k1 columns.
Product code decoding means for performing error correction decoding of the code.

(6) In the means of (5), the data rearranging means includes at least a plurality of memories and a control unit for controlling writing / reading of the plurality of memories, (N1 × n
2) In K data (1 ≦ K <n1) continuous symbols of N (N is an integer of 2 or more) data columns in n1 rows of a data block composed of symbols, By writing data to a plurality of memories in the sorting order and reading data from the plurality of memories, the original (n1
× n2) It is characterized by reproducing a product code of a symbol.

(7) With respect to the information data arranged in the (k1 × k2) two-dimensional array, C2 of (n2, k2) (where n2 is the code length) is set for each of k2 information symbols in each column.
In addition to performing error correction coding using two codes, (n1, k1) (where n1
1 is a code length), and performs error correction encoding using a C1 code.
A product code generating means for generating a product code composed of (n1 × n2) symbols; and N codewords (N is one of a plurality of C1 codewords included in the product code of the (n1 × n2) symbol) K (1 ≦ K <n) code words of 2 or more integers
First data rearranging means for rearranging data using the continuous symbols of 1) as one unit and forming N new data strings composed of n1 symbols;
× n2) n of a data block composed of symbols
Of N data columns (N is an integer of 2 or more) in one row,
Second data rearranging means for performing data rearrangement using K (1 ≦ K <n1) continuous symbols as one unit and reproducing a product code composed of the original (n1 × n2) symbols; Product code decoding for performing error correction decoding of the C1 code for each of k2 rows and error correction decoding of the C2 code for each of the k1 columns of the product code of the reproduced (n1 × n2) symbols. Means.

(8) In the means (7), the N
The codewords are included in at least two or more different product codes.

(9) In the means of (7) or (8), an ID information adding means for adding information on data rearrangement of the new data string is further provided.

(10) In the means of (7) to (9), the first data reordering means and the second
Data rearrangement means, at least comprises a plurality of encoding memories, a plurality of decoding memories, and a control unit for controlling writing / reading of the plurality of encoding memories and the decoding memories, Based on the control of the control unit, N (N is an integer of 2 or more) codewords of N (N is an integer of 2 or more) of C1 codewords of the product code of the (n1 × n2) symbol are used.
≦ K <n1) is written to a plurality of encoding memories in the order of data rearrangement, and data is read out from the plurality of encoding memories to form a new data string composed of n1 symbols into N Individualized,
Based on the control of the control unit, K (1 ≦ K <n) of N (N is an integer of 2 or more) data columns in n1 rows of a data block composed of the (n1 × n2) symbols
By writing the consecutive symbols of 1) as a unit into a plurality of decoding memories in the order of data rearrangement and reading out the data from the plurality of decoding memories, the product code of the original (n1 × n2) symbol is obtained. It is characterized by reproducing.

(11) In the means of the above (10), the plurality of encoding memories and the plurality of decoding memories are constituted by the same plurality of memories.

[0062]

According to each of the above means, after forming a product code in the error correction coding circuit, N (N is 2 or more) of a plurality of C1 code (or C2 code) code words included in the product code are used. ) Of K code words (1 ≦ K <n1) as a unit.

In the error correction decoding circuit, before performing error correction decoding of the product code, N (N is an integer of 2 or more) data of n1 rows of the (n1 × n2) symbol data block are used. The data is rearranged in units of K (1 ≦ K <n1) consecutive symbols in the column, and reproduced in the original product code data arrangement.

Thus, n1 of the recording medium or the communication path is
L symbols (L <n1) generated in the symbol range
Can be distributed to N codewords almost every L / N symbols.

As a result, when the C1 code is a code that can correct up to t symbols per codeword, it is possible to correct even if an error of about Nt symbols occurs in the range of n1 symbols. The number of errors that can be corrected by the C1 code can be apparently increased by about N times.

[0066]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

The present invention can be applied to a digital communication apparatus and a digital recording apparatus for performing error correction using a product code. In the following embodiments, the present invention is applied to a digital recording apparatus. The case will be described.

[Embodiment 1] FIG. 1 is a diagram showing a schematic configuration of an error correction encoding circuit and a digital recording apparatus using an error correction decoding circuit according to an embodiment (Embodiment 1) of the present invention. It is.

The digital recording device shown in FIG. 1 is a digital recording device used as an input / output device of a computer.

The error correction coding circuit according to the first embodiment comprises a product code forming means 33 and a data synthesizing means, and the error correction decoding circuit according to the first embodiment comprises a data decomposition means 7 and a product code And decoding means 33.

In the error correction encoding circuit according to the first embodiment, first, the data arrangement means 31 arranges the recording information from the computer in a two-dimensional array (k1 symbols × k2 symbols).

Next, after the C2 code and the C1 code are coded by the C2 code coder 1 and the C1 code coder 2, the data combining unit 3 rearranges data in symbol units.

Then, in the recording / reproducing system 4, the data encoded by the error correction encoding circuit of the first embodiment is recorded on a recording medium.

In the error correction decoding circuit of the first embodiment, the data sequence reproduced by the recording / reproducing system 4 at the time of reproduction is rearranged by the data decomposing means 5, and the original product code data is reproduced. I do.

Thereafter, the product code is decoded by the C1 code decoding means 6 and the C2 code decoding means 7, and the data transmission means 3 is decoded.
2 sends the playback information to the computer.

In the error correction coding circuit according to the first embodiment, after the recording information from the computer is arranged in the two-dimensional array (k1 symbol × k2 symbol) by the data arranging means 31, the C2 encoding means 1, encoding of the C2 code is performed.
When the recording information (k1 symbol) for one codeword of two codes is input, the C2 code is coded for it and k
It is also possible to arrange the recording information of k1 symbols × n2 symbols in a two-dimensional array when the encoding of the C2 code for the recording information of 1 symbol × k2 symbols is completed.

FIG. 2 is a diagram for explaining the operation of the data synthesizing means and the data decomposing means.

Next, the operation of the data synthesizing means and the data decomposing means will be described with reference to FIG.

FIG. 2 shows that data should be synthesized and decomposed (9 ×
6) A symbol product code block is shown. In FIG. 2, the C1 code is a (9, 5) RS code, and the C2 code is a (6, 4) RS code.

Here, the (n, k) RS code is a Reed-Solomon code having a code length of n symbols and the number of information symbols of k.

In the C1 code, up to two symbol errors can be corrected. In the C2 code, a two-symbol error is used when an error detection flag is used when decoding the C1 code, or when no error detection flag is used. Can correct an error of one symbol.

In FIG. 2, numbers A1, A2,..., A54 are assigned to 54 symbols constituting the product code block, and codewords of the C1 code are codewords 1, 2,. Assume that it is 6.

In the first embodiment, two consecutive codewords (codeword 1 and codeword 2, codeword 3 and codeword 4, and codeword 5
And codeword 6) as one group, and perform data synthesis for each group.

The data synthesizing means 3 rearranges the data so that the data of the two codewords is alternated in units of one symbol as shown in the synthesis block of FIG.

As a result, two new data blocks having the same length as the code word are generated for each group.

For example, from codeword 1 and codeword 2, (A
1, A10, A2, A11, A3, A12, A4, A1
3, A5), (A14, A6, A15, A7, A16,
A8, A17, A9, A18) are combined.

These two data blocks are referred to as compound word 1 and compound word 2, respectively.

Similarly, compound words 3, 4,..., 6 are combined.

Next, the data of the data block of (9 × 6) symbols after the data synthesis thus synthesized are recorded on the recording medium from left to right in order from the top (A1, A1).
0, A2, A11, A3, A12, A4, A13, A
5, A14, A6, A15, A7, A16, A8, A1
7, A9, A18,...).

On the other hand, during reproduction, the data decomposing means 5
To rearrange the data, and reproduce and reproduce the data of the product code block before the data synthesis.

FIG. 3 is a diagram for explaining the effects of the data synthesis and data decomposition shown in FIG.

Next, the effects of the data synthesis and data decomposition shown in FIG. 2 will be described with reference to FIG.

The composite block in FIG. 3 shows a data block before data decomposition during reproduction.

Here, it is assumed that an error has occurred in a hatched symbol.

That is, in the first row from the top, 4 symbols, 3
In the fourth row, errors of 3 symbols have occurred, and in the fifth row, errors of 4 symbols have occurred.

For comparison, consider the case where such a distribution error occurs in the product code block.

In this case, 1, 3, 4, 5
The error of the stage cannot be corrected, and an error detection flag is added to these four stages.

In the C2 code decoding, since the number of error detection flags added at the time of C1 decoding exceeds 2, erasure correction cannot be performed and random correction is performed.

As a result, the error can be corrected for the code word of the C2 code in which the error is one symbol or less, but the error of the other code words (code words in the fourth, fifth, sixth and seventh columns from the left) can be corrected. The error will remain uncorrected.

That is, if an error of distribution occurs in a product code block in which data synthesis is not performed, as shown in FIG. 3, an error of 11 symbols remains after decoding of the product code.

On the other hand, if a distribution error occurs in the product code block on which data synthesis has been performed as in the synthesis block shown in FIG. 3, the data distribution is performed before decoding the product code. , Are converted into an error distribution like the product code block shown in FIG.

When decoding is performed on the product code block shown in FIG. 3, an error can be corrected by decoding the C1 code except for the fourth stage from the top.

The fourth stage can be corrected at the time of decoding the C2 code by setting an error detection flag.

That is, when data synthesis is performed, all errors in the synthesis block shown in FIG. 3 can be corrected.

Therefore, when an error of distribution such as the combined block shown in FIG. 3 occurs, the error can be corrected by 11 symbols more when data combining is performed than when no data combining is performed.

In the above description, for ease of understanding, a case has been described in which all errors can be corrected by rearranging the data. However, depending on the type of error, the data may be rearranged. It may not be possible to correct all errors, and even in such a case, the correction capability is still improved.

In the first embodiment, the data synthesis is
Although the description has been given of the case where the processing is performed using two codewords of 1, the data synthesis is not necessarily performed using two codewords, and data of three or more codewords may be synthesized.

It is not always necessary to combine data using consecutive codewords, and codewords separated from each other may be combined.

Furthermore, the data rearrangement method at the time of data synthesis is not necessarily limited to the method described in the above embodiment.

For example, from the codeword 1 and the codeword 2 in FIG. 2 as a composite word 1 (A1, A11, A3, A13, A5, A
15, A7, A17, A9), as compound word 2 (A1
0, A2, A12, A4, A14, A6, A16, A
8, A18) may be generated.

FIG. 4 is a circuit diagram showing an example of the circuit configuration of the data synthesizing means / data decomposing means in the first embodiment.

In FIG. 4, 8 is a data synthesizing unit, 9 is a data decomposing unit, and 10 is a control unit.
Memory A13, Memory B14, Memory C15, Memory D
16 and a multiplexer 11 for selecting and outputting one of the four memory outputs.

The data decomposing unit 9 stores the data in the memory E17,
It comprises a memory F18, a memory G19, a memory H20, and a multiplexer 12 for selecting and outputting one of the four memory outputs.

Each of the memories A to H (13 to 20) has a data capacity capable of storing data of at least one codeword.

Taking the data synthesis shown in FIG. 2 as an example,
The operation of the data synthesizing unit 8 and data decomposing unit 9 shown in FIG. 4 will be described.

First, the operation of the data synthesizing section 8 will be described.

FIG. 5 is a time chart showing the operation of data synthesizing section 8 shown in FIG.

FIG. 6 is a partially enlarged view of the time chart shown in FIG.

Note that "W" and "R" in the time charts of FIGS. 5 and 6 respectively indicate that data is written to the memory and data is read from the memory.

However, "W '" indicates that writing to the memory is performed only in the first half or the second half of the period as shown in FIG.

In the time chart of FIG.
The number in parentheses below “W” indicates a memory address.

Here, it is assumed that the inputs to the data synthesizing section are in the order of codewords 1, 2, 3,... As shown in FIG.

First, code word 1 is constructed (A1, A2,
A1, A2, A3, A4, and A5 of the symbols A3, A4, A5, A6, A7, A8, and A9) are stored in the memory A1.
A3, A6, A
7, A8 and A9 are written to even addresses of the memory B14.

Next, code word 2 is formed (A10, A1
1, A12, A13, A14, A15, A16, A1
7, A18) of the symbols A10, A11, A1
2, A13 are written to even addresses of the memory A13, and A14, A15, A16, A17, A18 are
The data is written to an odd address of the memory B14.

At the time when writing of all the symbols of the code word 2 to the memory is completed, the memory A13 stores the combined word 1 including the first half symbols of the code words 1 and 2 and the memory B1.
4 stores a composite word 2 composed of the latter half symbols of the code words 1 and 2.

Further, the symbols of the code words 3 and 4 are similarly written into the memory C15 and the memory D16, and the composite words 3 and 4 are generated.

Thereafter, codewords 5 and 6 are stored in memory A13 and memory B14, and codewords 7 and 8 are stored in memory C15 and memory D1.
6, memory A13 and memory B14, and so on.
The data is similarly written while alternately switching the combination of the memory C15 and the memory D16.

On the other hand, the composite words 1, 2,... Generated on the memory A13, the memory B14, the memory C15, and the memory D16.
3 and 4 are read out as recording data through the multiplexer 11.

The control of the multiplexer 11 is performed by the control unit 10. During the period when the code word 3 is input to the data synthesizing unit 8, that is, the period when the synthesized word 1 is output, the memory A
13 during the period when the code word 4 is input to the data synthesizing unit 8, that is, during the period when the synthesized word 2 is output.
Select 14.

Next, the operation of the data decomposition section 9 will be described.

The data decomposing unit 9 converts the data arrangement of the composite block shown in FIG. 2 to the data arrangement of the product code block shown in FIG.

FIG. 7 is a time chart showing the operation of data decomposition section 9 shown in FIG.

FIG. 8 is a partially enlarged view of the time chart shown in FIG.

Note that “W” and “R” in the time charts of FIGS. 7 and 8 represent data writing to the memory and data reading from the memory, respectively, as in the time charts shown in FIGS. I have.

Further, “W ″” indicates that writing to the memory is performed every other symbol as shown in FIG.

Here, it is assumed that the input to the data decomposition section 9 is in the order of the composite words 1, 2, 3,...

First, a compound word 1 is constructed (A1, A1
0, A2, A11, A3, A12, A4, A13, A
5) every other symbol A1, A2, A3, A
4, A5 are sequentially written to successive addresses of the memory E17, and similarly, A10, A11, A12, A1
3 are sequentially written to the memory F18.

Compound word 2 (A14, A6, A15, A7,
A16, A8, A17, A9, A18), every other symbol A6, A7, A8, A9 is stored in the memory E17.
Is written after the data of the compound word 1 of A14,
A15, A16, A17, and A18 are written after the data of the compound word 1 in the memory F18.

When writing of all the symbols of the composite word 2 is completed, the symbols constituting the code words 1 and 2 are stored in the memories E17 and F18 in the same order as before the data decomposition.

Similarly, for compound words 3 and 4, memory G
19. Data is similarly decomposed using the memory H20 to obtain code words 3 and 4.

The memory E is used to decompose the composite words 5 and 6.
17, a memory F18, and a memory G19 and a memory H20 are used for data decomposition of the compound words 7 and 8, respectively.

The same applies to the subsequent compound words in the memory E
17 and memory F18, and memory G19 and memory H20.
Data decomposition is performed while alternately switching types of combinations.

On the other hand, the code word 1 formed on the memory,
2, 3, and 4 are output through the multiplexer 12.

As described above, data synthesis and data decomposition can be executed by using the data synthesizing unit / data decomposing unit shown in FIG.

As a result, a highly reliable digital recording device can be realized.

Although FIG. 4 shows the data synthesizing unit and the data decomposing unit when synthesizing and decomposing data of two codewords, the data synthesizing unit which synthesizes and decomposes data of three or more codewords -The disassembly section can be similarly configured.

The structure of a data synthesizing / decomposing unit for synthesizing / decomposing data of L code words (L is an integer of 2 or more) is as follows.
Each of the data synthesizing unit and the data decomposing unit includes a combination of 2L memories capable of storing data for one codeword and a multiplexer for selecting one of the outputs of the 2L memories. It has a control unit for controlling the synthesizing unit and the data decomposing unit.

FIG. 9 is a circuit diagram showing another example of the circuit configuration of the data synthesizing means / data decomposing means according to the first embodiment, wherein a memory used for data synthesizing and data decomposing is shared. is there.

In FIG. 9, 21 and 22 are multiplexers, 23 is a control unit, and the multiplexer 21 is
Either the output of the code encoder or the reproduced data is selected and input to the memories A to D (13 to 16), and the multiplexer 22 selects one of the outputs of the memories A to D (13 to 16) And output.

The control unit 23 also stores the memories A to D (13
To 16), to control the operations of the multiplexers 21 and 22.

The multiplexer 21 is controlled by a control unit to select an encoder output of the C1 code at the time of recording, and to select reproduction data at the time of reproduction, and the memories A to D (13 to 1).
The output of 6) is selected by the multiplexer 22 and output as data after data synthesis or data after data decomposition.

Each of the memories A to D (13 to 16) has a data capacity capable of storing data of at least one codeword.

In the circuit shown in FIG. 9, the operation at the time of data synthesis is the same as that of the circuit shown in FIG.
It is represented by the time chart of FIG.

On the other hand, the operation at the time of data decomposition is shown in FIGS.
In the time chart, memories E to H (17 to 20)
Are replaced with the memories A to D (13 to 16), respectively.

According to the circuit shown in FIG. 9, the same function as the circuit shown in FIG. 4 can be realized with a smaller amount of hardware.

[Embodiment 2] In Embodiment 2, code words of a plurality of different product code blocks are combined with each other. The configuration of the error correction coding circuit and the error correction decoding circuit is as follows. , Are the same as in the previous embodiment.

FIG. 10 is a diagram showing the data arrangement of the product code block before data synthesis in the second embodiment.

The left block shown in FIG. 10 is a product code block 1 and the right block is a product code block 2.

However, it is assumed that the product code block 1 is coded before the product code block 2 in time.

These product code blocks (1, 2)
1 code is (9, 5) RS code, C2 code is (6, 4) R
It is assumed that the block is a product code block composed of S codes.

The symbols constituting each product code block (1, 2) are numbered similarly to the product code block shown in FIG.

The symbol numbers of the product code block 1 and the product code block 2 are prefixed with A and B, respectively, to distinguish the data of the two product code blocks (1, 2).

FIG. 11 is a diagram showing the data arrangement of the product code block after data synthesis according to the second embodiment.

A procedure for combining two product code blocks (1, 2) and generating two combined blocks having the same size as the product code block will be described below with reference to FIGS.

First, the codewords (A1, A1) of the first stage of the product code block 1 and the product code block 2 shown in FIG.
2, A3, A4, A5, A6, A7, A8, A9),
(B1, B2, B3, B4, B5, B6, B7, B8,
B9) to generate two compound words.

For example, when the method shown in the first embodiment is used as this synthesizing method, two synthetic words (A1, B1, A2, B2, A3, B3, A4, B
4, A5), (B5, A6, B6, A7, B7, A8,
B8, A9, B9) are generated.

These two compound words are arranged continuously in the upper two stages of the compound block 1 as shown in FIG.

The second and third stages of the product code blocks 1 and 2
Similarly, the stage is synthesized and arranged on the arrangement of the synthesis block 1.

On the other hand, the fourth to sixth stages of the product code blocks 1 and 2 are combined and then arranged on the array of the combined block 2.

The two synthesized blocks thus generated are recorded on the recording medium in the order of the synthesized block 1 and the synthesized block 2.

FIG. 12 is a diagram showing an error distribution of data before data decomposition in the second embodiment, and FIG. 13 is a diagram showing an error distribution of data after data decomposition in the second embodiment.

Next, the effect of data synthesis in the second embodiment will be described with reference to FIGS.

For example, consider a case where an error as shown in FIG. 12 occurs in a composite block obtained by reproducing from a recording medium.

In the combining block 1, errors of four symbols occur in the second stage from the top, three symbols occur in the third stage, and three symbols occur in the fifth stage.

In the combining block 2, a burst error of 36 symbols has occurred.

For comparison, first consider the case where the distribution error shown in FIG. 12 occurs when data synthesis is not performed.

First, in the composite block 1, the errors in the second, third, and fifth stages from the top cannot be corrected by C1 decoding, and an error detection flag is added.

In C2 decoding, since the number of error detection flags exceeds 2, random correction without using error detection flags is performed.

As a result, the errors in the second, third and sixth columns from the left are corrected, and errors of seven symbols in the fourth, fifth and seventh columns remain.

The error that has occurred in the composite block 2 is C
An error cannot be corrected even by two-step error correction decoding of one code and C2 code.

That is, when data synthesis is not performed, errors of a total of 43 (= (7 + 36)) symbols remain in two blocks.

On the other hand, if an error in the distribution shown in FIG. 12 occurs in a synthesized block after data synthesis, data decomposition is performed before product code decoding.

As a result, the error distribution shown in FIG. 12 is converted into the error distribution shown in FIG.

When decoding is performed in this state, regarding the product code block 1, first, 2, 3, 3
The error in the stage is corrected, and an error detection flag is added to the fifth and sixth stages.

Next, in the C2 code decoding, all errors in the fifth and sixth stages from the top are corrected by performing erasure correction using the error detection flag added at the time of C1 decoding.

For the product code block 2, the first, second and third errors from the top are corrected by C1 decoding, and an error detection flag is added to the fifth and sixth stages.

Next, in the C2 decoding, the errors in the fifth and sixth stages from the top are corrected by performing erasure correction using the error detection flag added at the time of the C1 decoding, and all errors in the distribution of FIG. 12 are corrected. it can.

That is, when data combining is performed, both relatively short burst errors and long burst errors can be corrected efficiently, and more errors can be corrected than when no data combining is performed.

In the above description, for ease of understanding, a case has been described in which all errors can be corrected by rearranging the data. However, depending on the type of error, the data may be rearranged. It may not be possible to correct all errors, but even in such a case, the correction capability is still improved.

In the second embodiment, a case has been described in which data synthesis is performed using data of two different product code blocks. However, the number of product code blocks for performing data synthesis is not necessarily two. There may be three or more.

Further, it is not always necessary to combine code words of the same stage in different product code blocks, and code words of different stages may be combined.

The rearrangement of data at the time of data synthesis does not necessarily have to be performed in units of one symbol, but may be performed in units of two or more symbols.

Further, as in the first embodiment, the data rearrangement rule is not limited to one, and includes all rearrangements in which the number of symbols smaller than the code length n1 of the continuous C1 code is one unit.

FIG. 14 is a circuit diagram showing an example of the circuit configuration of the data synthesizing means / data decomposing means in the second embodiment.

The circuit shown in FIG. 14 includes memories A to H (13
20) is the same as the circuit shown in FIG.

The operation of the data synthesizing unit 8 and the data decomposing unit 9 shown in FIG. 14 will be described by taking the data synthesizing shown in FIGS. 10 and 11 as an example.

First, the operation of the data synthesizing unit 8 will be described.

FIG. 15 is a time chart showing the operation of data synthesizing section 8 shown in FIG.

FIG. 16 is a partially enlarged view of the time chart shown in FIG.

However, “W” and “R” are the same as those in FIGS.
As in the time chart of FIG. 2, data writing to the memory and data reading from the memory are shown.

When inputs are given to the data synthesizing section 8 in the order of product code block 1 and product code block 2, the first 27 symbols of product code block 1 are stored in memory A13.
, The latter 27 symbols are stored in the memory B1.
4 is written to each of the odd addresses.

The first 27 symbols of the product code block 2 are written to even addresses of the memory A13, and the second 27 symbols are written to even addresses of the memory B14.

When all the symbols of the product code block 2 have been written into the memory, the combined block 1 is stored in the memory A13 and the combined block 2 is stored in the memory B14.

FIG. 17 is a time chart showing the operation of data decomposition section 9 shown in FIG.

FIG. 18 is a partially enlarged view of the time chart shown in FIG.

It is to be noted that “W ″” in FIG.
As shown in the figure, the execution of writing to the memory is performed every other symbol.

When input data is given to the data decomposition section 9 in the order of the composite blocks 1 and 2, the composite block 1
The odd-numbered symbol and the even-numbered symbol are written to the first half continuous addresses of the memory E17 and the memory F18, respectively.

Regarding the combined block 2, contrary to the combined block 1, the even-numbered symbols are written to the memory E17 and the odd-numbered symbols are written to the memory F18.

The symbols of the composite block 2 are stored in the memory E1
7. In the second half address of the memory F18, the composite block 1
Is written following the symbol.

FIG. 19 is a circuit diagram showing another example of the circuit configuration of the data synthesizing means and data decomposing means according to the second embodiment, wherein a memory used for data synthesizing and data decomposing is shared. is there.

The circuit shown in FIG. 19 includes memories A to D (13
16) is the same as the circuit shown in FIG. 9 except that each has a data capacity of one product code block.

In the circuit shown in FIG. 19, the operation at the time of data synthesis is represented by the time charts of FIGS. 15 and 16 used for describing the operation of the circuit shown in FIG.

On the other hand, the operation at the time of data decomposition is shown in FIGS.
In the time chart of FIG. 8, memories E to H (17 to 2)
0) is replaced with memories A to D (13 to 16), respectively.

According to the circuit shown in FIG. 19, the same function as that of the circuit shown in FIG. 14 can be realized with a smaller amount of hardware.

[Embodiment 3] FIG. 20 shows a schematic configuration of an error correction encoding circuit and a digital recording apparatus using an error correction decoding circuit according to another embodiment (Embodiment 3) of the present invention. FIG.

In the third embodiment, ID information adding means 24 for adding ID information relating to a compound word to a compound word generated by data combining, and ID information checking means for checking ID information of reproduced data before data decomposition. 25 is added to the first embodiment.

For example, when combining N (N is an integer of 2 or more) codewords, as ID information, (1) what combination is used in the array of product code blocks, 2) Information indicating the order of the codeword among the N synthesized words obtained by synthesis is used.

FIG. 21 is a diagram showing an example of the ID information in the third embodiment in the case of the data combining of FIG. 2 used in the description of the first embodiment.

In the example of FIG. 2, two consecutive code words in the product code block are combined to generate two composite words.

The code word of C1 per product code block is 6
There are three combinations of codewords, codewords 1 and 2, codewords 3 and 4, and codewords 4 and 5.

Therefore, of the ID information, the above (1) becomes a value indicating any one of the three types, and can be expressed by 2 bits.

Further, the value of (2) is a value indicating one of two composite words generated by the combination of the code words shown in (1), and can be expressed by 1 bit.

Therefore, in the case of the data synthesis shown in FIG. 2, 3-bit ID information including (1) and (2) is added to each synthesized word.

On the other hand, at the time of reproduction, before decomposing the data, the ID information added to the composite word is checked, and based on the result, the data is written to the memory and the data is decomposed.

Also, since the normal ID information is added to the head of the composite word, in the third embodiment, the reproduction data is written to the memory based on the ID information.

Therefore, it is possible to prevent data from being written to an erroneous address when the head of a composite word cannot be found correctly due to loss of synchronization or the like.

Therefore, according to the third embodiment, a more reliable digital data recording apparatus can be realized as compared with the case where no ID information is used.

Further, after the ID information is added by the ID information adding means 24, there may be provided a means for protecting the ID information, for example, a means for encoding the ID information with an error detection code. It is possible.

Here, the error detection code is a code which can be corrected only by detecting an error.

At the time of reproduction, error detection is performed on the ID information prior to the ID information inspection, and if it is determined that there is no error, data is written to the memory according to the ID information.

When it is determined that there is an error, the data of the compound word is discarded without writing to the memory, or the same data is reproduced again from the recording medium.

[0233] ID information may be encoded by an error correction code instead of an error detection code.

In this case, at the time of reproduction, first, error correction decoding of the ID information portion is performed, and after an error occurring in the ID information portion is corrected, data decomposition can be performed according to the ID information.

If the error occurred in the ID information portion and could not be corrected, as in the case of the error detection code described above, the data of the composite word was discarded without writing to the memory, or Play the same data again.

When means for protecting ID information is provided as described above, more reliable data synthesis and data decomposition can be performed.

Although the embodiments of the present invention have been described by taking a digital recording device as an example, it goes without saying that the present invention is applicable to a digital communication device as shown in FIG.

As described above, the present invention has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof.

[0239]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in a product code that performs two-stage encoding using a C2 code and a C1 code, the correction capability of the C1 code without changing the specifications (code length and parity number) of the error correction code. Can be improved.

(2) According to the present invention, a digital communication device or a digital recording device having a low error rate and high reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a digital recording device using an error correction encoding circuit and an error correction decoding circuit according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a diagram for explaining the operation of the data synthesizing means and the data decomposing means.

FIG. 3 is a diagram for explaining the effects of data synthesis and data decomposition shown in FIG. 2;

FIG. 4 is a circuit diagram illustrating an example of a circuit configuration of a data synthesizing unit and a data decomposing unit according to the first embodiment.

FIG. 5 is a time chart showing an operation of the data synthesizing unit 8 shown in FIG.

FIG. 6 is a partially enlarged view of the time chart shown in FIG. 5;

7 is a time chart showing an operation of the data decomposing unit 9 shown in FIG.

FIG. 8 is a partially enlarged view of the time chart shown in FIG. 7;

FIG. 9 is a circuit diagram showing another example of the circuit configuration of the data synthesizing unit / data decomposing unit in the first embodiment.

FIG. 10 is a diagram illustrating a data arrangement of a product code block before data synthesis according to the second embodiment.

FIG. 11 is a diagram illustrating a data arrangement of a product code block after data synthesis according to the second embodiment.

FIG. 12 is a diagram illustrating an error distribution of data before data decomposition according to the second embodiment.

FIG. 13 is a diagram illustrating an error distribution of data after data decomposition in the second embodiment.

FIG. 14 is a circuit diagram illustrating an example of a circuit configuration of a data synthesizing unit and a data decomposing unit according to the second embodiment.

FIG. 15 is a time chart illustrating an operation of the data synthesizing unit 8 illustrated in FIG. 14;

FIG. 16 is a partially enlarged view of the time chart shown in FIG. 15;

FIG. 17 is a time chart illustrating an operation of the data decomposing unit 9 illustrated in FIG. 14;

18 is a partially enlarged view of the time chart shown in FIG.

FIG. 19 is a circuit diagram showing another example of the circuit configuration of the data synthesizing unit / data decomposing unit in the second embodiment.

FIG. 20 is another embodiment (third embodiment) of the present invention.
1 is a diagram showing a schematic configuration of a digital recording device using an error correction encoding circuit and an error correction decoding circuit.

FIG. 21 is a diagram illustrating an example of ID information according to the third embodiment in the case of the data combining of FIG. 2 used in the description of the first embodiment.

FIG. 22 is a diagram for describing a method of encoding a product code.

FIG. 23 is a diagram for explaining a conventional method for further improving the error correction capability without changing the configuration of the product code block.

FIG. 24 is a block diagram showing a schematic configuration of a digital communication device using radio, which is used in a digital communication system.

[Explanation of symbols]

1 ... C2 coding means, 2 ... C1 coding means, 3
... Data synthesizing means, 4 ... Recording / reproducing system, 5 ... C2 code decoding means, 6 ... C1 code decoding means, 7 ... Data decomposing means, 8 ... Data synthesizing section, 9 ... Data decomposing section, 10, 23
... Control unit, 11, 12, 21, 22 ... Multiplexer,
13-20: memory, 24: ID information adding means, 25:
ID information inspection means, 31 data arrangement means, 32 data transmission means, 33 product code generation means, 34 product code decoding means.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-4-154222 (JP, A) JP-A-64-89719 (JP, A) JP-A-64-89782 (JP, A) JP-A 8- 23318 (JP, A) JP 62-48409 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G11B 20/00 H04L 1/00

Claims (10)

(57) [Claims] 1. For information data arranged in a (k1 × k2) two-dimensional array, a C2 code of (n2, k2) (where n2 is a code length) is used for each of k2 information symbols in each column. Perform error correction coding, and perform k1
Error correction coding is performed using a C1 code of (n1, k1) (where n1 is a code length) for each information symbol, and (n1
A product code generating means for generating a product code composed of (1 × n2) symbols; and N codewords (N is 2) among a plurality of C1 codewords included in the product code of the (n1 × n2) symbol. Data rearrangement in which K (1 ≦ K <n1) consecutive symbols of codewords of the above (integral) are rearranged as one unit, and N new data strings composed of n1 symbols are formed. And an error correction coding circuit. 2. The method according to claim 1, wherein the N code words are included in at least two or more different product codes.
3. An error correction encoding circuit according to claim 1. 3. The N codewords comprise N different product codes.
The error correction coding circuit according to claim 1, wherein the error correction coding circuit is included in each of the codes. 4. The data rearranging means according to claim 1, wherein said N is two, and said data rearranging means includes a symbol for each of a first Cl code and a second Cl code.
3. The error correction coding circuit according to claim 1, wherein the error correction coding circuit is a means for alternately rearranging the error correction codes. 5. A method for rearranging data of said new data string.
ID information adding means for adding information related to
The method according to any one of claims 1 to 4, wherein
2. The error correction coding circuit according to claim 1. 6. The method according to claim 1, wherein said data rearranging means includes a plurality of memos.
And control for controlling writing / reading of the plurality of memories.
And at least a (n1 × n2) symbol based on the control of the control unit.
N (N is 2 or more) among the code words of the C1 code of the product code
K (1 ≦ K <n1) consecutive codewords
Write symbols to multiple memories in the order of data sorting
By reading data from the plurality of memories.
Ri, N number of new data row consists of n1 symbol
6. The method according to claim 1, wherein the first electrode is formed.
2. The error correction encoding circuit according to claim 1. 7. The method according to claim 1, wherein:
Encoded by the described error correction encoding circuit (n
1 × n2) of a data block composed of symbols
N data columns (N is an integer of 2 or more) in n1 rows
Of K (1 ≦ K <n1) consecutive symbols
And rearranges the data and returns the original (n1 × n2)
Data rearrangement to reproduce product code composed of symbols
Means and the product of the reproduced (n1 × n2) symbols
Performs error correction decoding of the C1 code for each k2 rows of the code.
Error correction decoding of C2 code for each of k1 columns
And a product code decoding means for performing
Correction decoding circuit. 8. A (k1 × k2) two-dimensional array
K2 information symbols for each column
C2 code of (n2, k2) (where n2 is the code length)
Error correction coding using the
(N1, k1) for each information symbol (where n1 is
Error correction coding using a C1 code having a code length of (n)
Generate a product code composed of 1 × n2) symbols
Product code generating means, and a plurality of product codes included in the product code of the (n1 × n2) symbols.
N (N is an integer of 2 or more) of the code words of the C1 code
Let K (1 ≦ K <n1) consecutive symbols of a codeword be
Data is rearranged as one unit, and from n1 symbol
First data forming N new data strings to be constructed
Rearranging means, and a data table composed of the (n1 × n2) symbols.
N (N is an integer of 2 or more) data of n1 rows of the lock
K (1 ≦ K <n1) consecutive symbols in the data sequence
Data is rearranged as one unit, and the original (n1 × n
2) A second method for reproducing a product code composed of the symbols of
Data rearranging means, and a product code of the reproduced (n1 × n2) symbols,
Error correction decoding of C1 code is performed for each of k2 rows, and
And a product for performing error correction decoding of the C2 code for each of k1 columns
Error correction code comprising code decoding means
Encoding / decoding circuit. 9. The method according to claim 1, wherein the N code words are at least two or more.
9. The method according to claim 8, wherein the code is included in the different product codes.
3. An error correction encoding / decoding circuit according to claim 1. 10. The method according to claim 1, wherein
An error correction coding circuit described in claim 7 and
Error correction decoding circuit
Digital recording device.