JPH04232663A - Data decoding device - Google Patents

Abstract

PURPOSE:To obtain a data decoding device which can excellently connect main data and withstand strong vibrations by obtaining the synchronizing signal output of auxiliary information based on the detecting timing of a specific mark added to the main data and based on external clock. CONSTITUTION:A sub-code synchronization detection circuit 20 performs writing/ reading-out on a RAM 15 on the basis of the clock of a PLL system obtained from reproduced signals after adding a specific mark to main data in accordance with the detecting output of the synchronizing signal of sub-codes. Then it is tried to obtain the synchronizing signal output of the sub-codes on the basis of the detecting output of the specific code read out from the RAM 15 and an external clock 19. Therefore, when the main data are divided at the timing of the auxiliary information, a reproducible punctuating point is obtained even when a jitter exists and overlapping or destruction of the main data does not occur.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding apparatus for decoding data that has been subjected to error correction encoding.

0002

2. Description of the Related Art Conventionally, as a format for recording PCM data on an optical disk after performing error correction encoding processing and adding auxiliary information, for example, the so-called CI
There is a so-called compact disc (CD) signal format in which PCM digital audio data (main data) is subjected to error correction encoding processing using RC (cross-interleaved Reed-Solomon code) and a subcode is added as the above-mentioned auxiliary information. do.

FIG. 5 shows the signal format of the above-mentioned CD. That is, in the signal format of FIG. 5,
One frame is made up of a frame synchronization pattern, a subcode, digital audio data, and a parity bit used for error correction in order from the beginning. The one frame includes 24 channel bits in a frame synchronization pattern,
1 byte for subcode (1 byte is 14 channel bits by EFM (8-14 modulation)) and 32 bytes for each digital audio data and parity bit.
There are 3 channel bits for connection between each byte after the above frame synchronization pattern, resulting in a total of 588 bits.
The channel is a bit.

Furthermore, as shown in FIG. 6, 98 subcodes constitute one block (that is, 98 frames).
is configured. The first 2 of this block
Two synchronization patterns, S0 and S1, are arranged in each subcode, and each subcode for the remaining 96 frames has a so-called P channel (P1) of 1 bit each.
~P96), Q channel (Q1 ~Q96), and other information are arranged. For example, the P channel is used to record the so-called inter-song portion between two pieces of music.
1”.

[0005] Furthermore, if we take out only the subcodes in FIG. 6 and explain them, as shown in FIG.
A block of 96 bytes is formed with one synchronization pattern at the beginning, and among these, P1 to P96
and Q1 to Q96 are used for access. Further, the 6 bits R to W are used for special purposes such as still images and character display. Furthermore, the frequency and period of this one subcode frame are each 7.3
5kHz÷98=75Hz and 13.3msec.

[0006] As shown in FIG. 8, the Q channel is
The 96 bits for the above 96 frames are 4 control bits, 4 address bits, 72 data bits, and C
It is divided into 16 bits of RC (or CRCC; cyclic code). Furthermore, the 4 bits of the above address contain (00
There are three cases: 01), (0010), and (0011), and the remaining two are manufacturer codes and the like.

[0007] Here, the above (0001), that is, "1"
At this time, the 72-bit data has a format as shown in FIG. In other words, the format shown in FIG. 9 starts with the movement number (track mark),
It consists of an index mark, the elapsed time within a movement using minutes, seconds, and frame numbers, and 0, and absolute time using minutes, seconds, and frame numbers. Note that the absolute time is the elapsed time when the data recorded on the disc is reproduced from the beginning to the end.

[0008] When a CD of the above format is played back by a conventional playback device, the EFM modulated signal (binary signal) played from the disc is first converted into a clock based on this binary signal. Detected (clock recovery). This clock regeneration is normally accomplished by a PLL (phase locked loop) configuration, and the frequency of this clock (hereinafter referred to as PLL clock) is 4.32.
The frequency is 18 MHz (7.35 kHz x 588). In the conventional playback device described above, binary data is taken in by the PLL system clock, and the EFM demodulation is performed. At this time, the frame synchronization pattern is also detected from the binary data, and the subcode data after the frame synchronization pattern is demodulated.

[0009] The data after the EFM demodulation is the CIR
Error correction and detection based on C is performed, and erroneous data is corrected. Thereafter, digital/analog conversion is performed to obtain an analog audio signal.

0010

By the way, the data that has been subjected to the error correction encoding process is usually decoded by using a RAM. That is, RAM
The interleaving is resolved by controlling the read address of the data. Generally, the write address of this RAM is formed based on the above-mentioned PLL system clock, whereas the read address is formed using a clock from a crystal oscillator of an external circuit (hereinafter referred to as the crystal system clock). There is.

However, since the PLL system clock is formed based on the reproduced signal from the disk as described above, it is usually affected by jitter caused by the rotation of the motor or the eccentricity of the disk. On the other hand, since the crystal clock has almost no jitter, there is a time difference between the PLL clock and the crystal clock corresponding to this jitter.

[0012] Furthermore, the main data such as the digital audio data is composed only of PCM data, and the main data itself does not include time information. For this reason, for example, if a subcode with time information is used as described above and the main data is separated at the timing of this subcode, a reproducible separation point will be obtained due to the jitter. I can't. Therefore, the data in the RAM may overlap or be corrupted by the amount of jitter described above. That is, if, for example, digital audio data as main data is to be connected at the timing of the sub-code, it is not possible to obtain reproducible divisions as described above, resulting in skipping or the like.

Furthermore, in a system that compensates for the case where data cannot be obtained due to a reading error or a pickup being out of focus, for example, the data recorded in the RAM is read out in bursts at double speed. As described above, since the main data does not have time information, if the data is connected for convenience at the timing of the subcode, data will be lost or overlapped by the amount of jitter described above.

[0014] For this reason, for example, if vibrations are applied to the playback device during playback, data connection failures may occur, resulting in, for example, sound skipping.

The present invention has been proposed in view of the above-mentioned circumstances, and it is possible to connect the main data of data read from a disc on which signals are recorded in the CD format to prevent data loss or overflow. It is an object of the present invention to provide a data decoding device that can be realized without wrapping and is resistant to vibrations.

[0016]

[Means for Solving the Problems] A data decoding device of the present invention has been proposed in order to achieve the above-mentioned object, and the data decoding device of the present invention has been proposed to achieve the above-mentioned object. A data decoding device that reproduces data from a disc recorded with data in a format to which auxiliary information including auxiliary information is added, and decodes the main data in the reproduced data using a RAM, the data decoding device comprising: After adding a specific mark to the main data according to the detection output of the synchronization signal of the auxiliary information, the main data with the specific mark added is written to the RAM based on the clock obtained from the reproduction signal. Including/
The synchronization signal output of the auxiliary information is obtained based on the detection output of the specific mark read out from the RAM and the external clock.

[0017]

[Operation] According to the data decoding device of the present invention, after adding a specific mark to the main data according to the detection output of the auxiliary information, it is decoded using the RAM, and the detection timing of this specific mark and external Since the synchronous signal output of the auxiliary information is obtained based on the clock, the auxiliary information and the main data can be obtained in synchronization.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the data decoding apparatus of the present invention will be described with reference to the drawings. As shown in FIG. 1, the data decoding device according to the embodiment of the present invention, for example, generates main data (audio data) obtained by processing PCM digital audio data using error correction coding (CIRC) and auxiliary information including absolute time information of the main data. The main data and subcode are reproduced from a disk on which data in a format to which a subcode is added is recorded, and the main data is written to/read from the RAM 15 and the error correction code is decoded. It is a data decoding device. In this data decoding device, a subcode sync detection circuit 2
0, a specific mark (for example, L6n, A and L6
Add 1 bit to the upper side of n, B and set this bit to “1”
After the main data to which the specific mark has been added is written to/read from the RAM 15 based on the PLL system clock obtained from the reproduction signal, the main data is read from the RAM 15. The synchronization signal output of the subcode is obtained based on the detection output of the specific mark and an external clock (the crystal clock).

That is, in FIG. 1, input terminal 1
For example, a signal read from a CD by an optical pickup is binarized via an RF amplifier (EF
M signal) is supplied. This input EFM signal is supplied to the latch circuit 11. Here, the clock input terminal of the latch circuit 11 is connected to a phase detection circuit (P
A PLL system clock (EFM bit clock) formed by a loop consisting of a PLL circuit 31 (DO) 30 and an external circuit is supplied. This latch circuit 11
The output of is sent to an edge detection circuit 12, and edge information from the edge detection circuit 12 is sent to a 23-bit shift register. This shift register 13 has an output for each stage, and detects a frame synchronization signal (that is, an EFM synchronization signal) using all 23 bits. This allows the decoder to be synchronized. In addition,
It is also possible to configure the PLL circuit 31 described above to be included in the device of this embodiment.

The 23-bit shift register 13 outputs 14 bits of data and sends it to the EFM demodulation circuit 14. The EFM demodulation circuit 14 has a terminal 9.
A crystal timing generation circuit 19 operates based on an external clock supplied from a crystal oscillator in an external circuit via
A crystal clock is supplied from therefore,
The EFM demodulation circuit 14 performs a process of converting (demodulating) the 14-bit data into normal 8-bit data based on this crystal clock. This 8-bit data is sent to RAM15. Note that it is also possible to include the above-mentioned crystal oscillator within the device of this embodiment.

The write/read address data in the RAM 15 of the device of this embodiment is generated based on the PLL system clock. That is, this write/read address data is generated by the RAM address generation circuit 24, and the RAM address generation circuit 24 receives a timing clock from the PLL system timing generation circuit 23 to which the PLL system clock is supplied. It is designed to operate based on Therefore, the RAM address generation circuit 24 generates write/read address data for the RAM 15 based on the PLL system clock. Further, the read address data is address data for decoding the above-mentioned error correction encoded 8-bit data (decoding the error correction encoding, that is, removing interleaving). Furthermore, this RAM 15 is
It is possible to store data for the above 108 EFM frames, and therefore, from the RAM 15, these 10
The interleaved data is obtained every 8 EFM frames.

Thereafter, the interleaved data is sent to the error detection/correction circuit 16. In the error detection/correction circuit 16, as shown in FIG.
Two-stage read in the CIRC format
Error detection and correction of Solomon codes (C1, C2) is performed. This error detection/correction circuit 16 also operates based on the crystal clock. When an error is detected in the error detection/correction circuit 16, the interpolation circuit 17 performs average value calculation or pre-hold processing on the data, and then the data is transferred to the parallel or serial data via the buffer 18. is output as This buffer 18 operates based on the crystal clock, and therefore, the output of the buffer 18 is based on the crystal clock.

[0023] Furthermore, the data of the subcode is the EFM
After being extracted by the demodulation circuit 14, it is sent to the subcode demodulation circuit 21. The subcode demodulation circuit 21 performs subcode demodulation, and then the signal is sent to a CRC check (cyclic code error detection) circuit 22 . After error detection is performed by the CRC check circuit 22, the data is sent to the buffer 18.

By the way, in this buffer 18,
The main data and the subcode data are synchronized. In order to accomplish this, the following steps are performed in this embodiment.

That is, in this embodiment, 1 is placed on the upper side of each of the specific 2 bytes of the main data following S0 or S1 (S1 in this embodiment) of the subcode.
The bit is added and this bit is set to "1", and the subcode is synchronized based on these two bytes of "1" and the crystal clock. As the specific 2 bytes, as shown in Figure 3, we use the 2 bytes L6n,A and L6n,B of the main data that always follow S1 of the subcode of the EFM frame, and I am trying to set "1" above.

To do this, the 14-bit output from the shift register 13 is also sent to the subcode sync detection circuit 20. The subcode sync detection circuit 20 detects S1 of the subcode. The detection output from this subcode sync detection circuit 20 is such that only the two bytes following S1 are "H". In other words, these two bytes correspond to L6n,A and L6n,B of the main data. Therefore, by sending the detection output of this subcode sync detection circuit 20 to the RAM 15, the RAM 15
1 bit is added to the upper side of the 8 bits of L6n, A and L6n, B which are supplied simultaneously with the detection output.
The most significant bit of these 9 bits is set to "1". Therefore, this RAM 15 is
A RAM with at least a 9-bit processing unit is used.

Furthermore, the subcode sync detection circuit 20
Also includes a circuit for taking countermeasures when, for example, the detection error in S1 occurs. That is, the subcode sync detection circuit 20 also detects the above S0, and if a detection error of the above S1 occurs at this time, the next subcode byte after the previously detected S0 is detected. (ie, the subcode byte having the above S1), "H" corresponding to the above-mentioned detection output is output. Furthermore, when both S0 and S1 result in an error, the output before this error occurs, that is, the S0 or S1 detected in the previous frame.
The interpolation output ("H" corresponding to the above detection output) is output 13.3 ms (one frame) after the timing based on .

Here, in the case of the above L6n that comes once every 13.3 ms, the data supplied to the 9-bit RAM 15 will have "1" at the top, but in this embodiment, In the RAM 15, CIRC decoding processing similar to the conventional one is performed in this unit. That is, the interleaving is restored in units of 9 bits. The output of this RAM 15 is sent to the buffer 18 via the error detection/correction circuit 16 and the interpolation circuit 17.

Furthermore, in the buffer 18 of this embodiment,
A sync bit detection circuit 18a is arranged. This sync bit detection circuit 18a detects L6n, A and L6n of 2 bytes of the main data if "1" is set in the most significant bit (sync bit) of the output of the RAM 15.
, B, that is, logic that outputs "H" over one period of the clock LRCK for switching the L and R channels in FIG. Therefore, the output of the sync bit detection circuit 18a is used as the synchronization signal output (SBSY in FIG. 4) of the subcode.

Therefore, in the buffer 18, the main data is read based on the crystal clock, and the shift clock is raised in response to the synchronization signal output SBSY of the subcode shown in FIG. , by reading the data of the subcode from the CRC check circuit 22, the Q data (SUBQ) of the subcode and the SUBQ can be read out from the CRC check circuit 22.
It becomes possible to read the data (CRCF) etc. The subcode synchronization signal output SBSY is output from the terminal 3, the subcode Q data SUBQ is output from the terminal 4, and the main data is output from the terminal 6.

Furthermore, the crystal timing generation circuit 19 outputs the clock LRCK for switching the L and R channels via the terminal 7, and the system clock SCK is output via the terminal 8. There is.

Note that FIG. 4 shows the signal waveforms of each part of the device of this embodiment, and normally the LRCK and S
Main data is output in synchronization with CK. Also,
The subcode synchronization signal output SBSY is, for example, the above LRC.
When data of L6n at the beginning of an EFM frame with S1 is outputted in synchronization with K, L6n, R
It is output over one period of the above LRCK of 6n. Further, the above SUBQ and CRCF are read by an external clock SQCK supplied from the terminal 5.

As described above, in this embodiment, one bit is added to the most significant part of each of the two bytes of specific main data following S1 or S0 of the subcode, and this bit is set to "1". After writing/reading to/from the 9-bit RAM 15 and deinterleaving, the most significant "1" is detected and the subcode synchronization signal output SBSY is obtained based on this, so the main data and the subcode are It is now possible to synchronize with the code. Furthermore, since the buffer 18 operates based on a crystal clock, the main data and subcode are synchronized with this crystal clock. For this reason, when the main data is divided at the timing of the subcode, even if jitter exists, the main data will not overlap or be corrupted. That is, even if the main data is divided at the timing of this subcode, reproducible division points can be obtained. In addition, for example, when data cannot be obtained due to a reading error or the pickup is out of focus, the above-mentioned R
Even in a system that compensates by reading out data recorded in AM in bursts at double speed, there is no chance of main data being lost or overlapping. Furthermore, reading of the main data and auxiliary information can be done in the same manner as in the past. For this reason, even if vibrations are applied to the playback device during playback, for example, skipping of the sound will not occur, making it possible to obtain a playback device with high earthquake resistance.

In this embodiment, as described above, the subcode synchronization signal is output when the first sample value (main data) L6n of the EFM frame in which the subcode S1 exists as auxiliary information is output. Although an example has been described, S1 of this subcode and L6n of the first sample value may be other values as long as they are reproducible.

Furthermore, in the above-described embodiment, an example was shown in which the most significant bit (L6n) of the main data is used as a flag for outputting a subcode synchronization signal. It is also conceivable to use the byte of the interpolation pointer during interpolation in the interpolation circuit 17. That is, in this interpolation circuit 17, there is an interpolation pointer indicating that the sample value is an interpolation value, and normally only one bit out of eight bits is used. For this reason, this unused 7
One of the bits can be used as a flag for outputting the subcode synchronization signal.

Furthermore, it is also possible to configure the subcode and the subcode synchronization signal output to be switchable between a mode in which the subcode and the subcode synchronization signal output are output at the same timing as in the past, and a mode in which the subcode and the subcode synchronization signal are output at the same timing as in this embodiment. be.

[0037]

Effects of the Invention As described above, in the data decoding device of the present invention, after adding a specific mark to main data according to the detected output of auxiliary information, it is decoded using a RAM, and this specific mark is Since the synchronized signal output of the auxiliary information is obtained based on the mark detection timing and the external clock, the auxiliary information and the main data can be obtained in synchronization. If the data is separated, even if jitter exists, a reproducible separation point can be obtained, and the main data will not overlap or be corrupted. Furthermore, in a system that compensates for the case where data cannot be obtained due to a reading error or the pickup being out of focus, etc., the data recorded in the RAM is read out in bursts at double speed, the main data may be lost. There is no overlap. Furthermore, reading of the main data and auxiliary information can be done in the same manner as in the past. For this reason, for example, if vibrations are applied to the playback device during playback, it is possible to obtain a highly earthquake-resistant data decoding device that does not cause poor data connection and, for example, sound skipping. become able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a schematic configuration of a data decoding device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining CIRC.

FIG. 3 is a diagram showing an EFM frame.

FIG. 4 is a waveform diagram showing signal waveforms of each part of the device of this embodiment.

FIG. 5 is a diagram showing a CD signal format.

FIG. 6 is a diagram showing a subcode frame.

FIG. 7 is a diagram for explaining the contents of a subcode.

FIG. 8 is a diagram showing a frame structure of a Q channel.

FIG. 9 is a diagram showing a 72-bit data format.

[Explanation of symbols]

11... Latch circuit 12... Edge detection circuit 13... Shift register 14... EFM demodulation circuit 15... RAM 16... Error detection/correction circuit 17... - Interpolation circuit 18...Buffer 18a...Sync bit detection circuit 19...Crystal timing generation circuit 20...Subcode sync detection circuit 21...Subcode demodulation circuit 22...・CRC check circuit 23...PLL timing generation circuit 24...
RAM address generation circuit 30...phase detection circuit

Claims (1)

[Claims] Claim 1: Data is reproduced from a disc recorded in a format in which auxiliary information including time information of the main data is added together with main data obtained by error correction encoding processing of PCM data, and the data is reproduced using a RAM. In a data decoding device that performs decoding processing of the main data in the playback data of the lever, a specific mark is added to the main data according to the detection output of the synchronization signal of the auxiliary information, and then the specific mark is added. The main data is stored in the RAM based on the clock obtained from the reproduced signal.
A data decoding device characterized in that the data decoding device writes/reads data to/from the RAM and obtains a synchronization signal output of the auxiliary information based on the detection output of the specific mark read from the RAM and an external clock.