JPH0766315A - Ceramic lid substrate for semiconductor package and ceramic lid - Google Patents
Ceramic lid substrate for semiconductor package and ceramic lidInfo
- Publication number
- JPH0766315A JPH0766315A JP5235389A JP23538993A JPH0766315A JP H0766315 A JPH0766315 A JP H0766315A JP 5235389 A JP5235389 A JP 5235389A JP 23538993 A JP23538993 A JP 23538993A JP H0766315 A JPH0766315 A JP H0766315A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- solder
- glass frit
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
- H05K3/247—Finish coating of conductors by using conductive pastes, inks or powders
- H05K3/248—Finish coating of conductors by using conductive pastes, inks or powders fired compositions for inorganic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12486—Laterally noncoextensive components [e.g., embedded, etc.]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12528—Semiconductor component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
- Y10T428/12611—Oxide-containing component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12861—Group VIII or IB metal-base component
- Y10T428/12868—Group IB metal-base component alternative to platinum group metal-base component [e.g., precious metal, etc.]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子をパッケー
ジ本体の内部に収容した後、その本体に被せて半田付け
により封着（接合）し、内部に収容した半導体素子を密
封するためのセラミック製リッド基板およびこれに半田
層を形成してなるセラミック製リッド（以下、「リッド
基板」若しくは「リッド」ともいう）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic for encapsulating (bonding) a semiconductor element housed inside a package body, then covering the body by soldering (sealing), and sealing the semiconductor element housed inside. The present invention relates to a lid substrate made of ceramic and a lid made of ceramic (hereinafter, also referred to as “lid substrate” or “lid”) in which a solder layer is formed on the lid substrate.
【０００２】[0002]
【従来の技術】この種のリッドの代表的なものとして
は、図５に示す断面構造のものがある。このものは、リ
ッド５１のパッケージ本体に対面する面５３の周縁５４
に沿って、半田層を設ける下地としてガラスフリット
（粉体）Ｇ入りのＡｇ−Ｐｄペーストを印刷、焼成して
金属層（厚膜メタライズ）５６を形成したものである。
そして、このものは、次工程で溶融した半田中に浸漬す
る等して金属層５６の上にのみ選択的に半田層Ｈを形成
することにより、封着に供するようにしたものである。2. Description of the Related Art A typical lid of this type has a sectional structure shown in FIG. This has a peripheral edge 54 of a surface 53 of the lid 51 facing the package body.
A metal layer (thick film metallization) 56 is formed by printing and firing an Ag-Pd paste containing glass frit (powder) G as a base on which a solder layer is provided.
Then, this product is used for sealing by selectively forming the solder layer H only on the metal layer 56 by immersing it in the molten solder in the next step.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記従来のリ
ッド５１においては、金属層５６の表面に無数のガラス
フリットＧが存在（露出）しているために、半田層Ｈを
形成すると、図５に示したように、半田層Ｈ中に多数の
ボイドＶを生成させてしまう。これは、半田がガラスフ
リットＧに濡れないため、その形成過程で発生するフラ
ックスのガスが、ガラスフリットＧに接する部位でボイ
ドＶとなるためと考えられる。そして、図６Ａ〜Ｃに示
すように、このリッド５１でもってパッケージ本体１１
を封着する場合には次のような問題があった。すなわ
ち、半田Ｈが半導体パッケージの内外に飛散するため、
封止不良や外観不良を起こしたり、或いはリードピンや
半導体素子に半田が付着することによる短絡を起こすな
どの不良が多発し、歩留まりの低下を招いていた。ま
た、半田の飛散に至らなくとも大きなボイドとして残る
と、その部位において封止性能が低下し、気密性の低下
を招いてしまう。こうした問題は、半田層Ｈ中にボイド
Ｖがあることに起因するもので、封止過程において多数
のボイドＶが結合したり熱膨張によって大きなボイドＶ
ａに成長し、その中のガスが外に逃げようとするために
発生すると考えられる。However, in the above-described conventional lid 51, since the innumerable glass frits G are present (exposed) on the surface of the metal layer 56, when the solder layer H is formed, as shown in FIG. As shown in FIG. 3, many voids V are generated in the solder layer H. It is considered that this is because the solder does not wet the glass frit G, and the gas of the flux generated during the formation of the solder becomes the void V at the portion in contact with the glass frit G. Then, as shown in FIGS. 6A to 6C, the package main body 11 is held by the lid 51.
There was the following problem when sealing the. That is, since the solder H is scattered inside and outside the semiconductor package,
Frequent defects such as poor sealing, poor appearance, and short circuits due to solder sticking to the lead pins and semiconductor elements have resulted in a decrease in yield. Further, if the solder remains as large voids even if the solder is not scattered, the sealing performance is deteriorated at that portion and the airtightness is deteriorated. Such a problem is caused by the presence of voids V in the solder layer H, and a large number of voids V are combined or large voids V due to thermal expansion in the sealing process.
It is thought that it is generated because it grows to a and the gas in it tries to escape to the outside.
【０００４】本発明は、こうした問題点を解消すべく案
出したものであって、半田層形成用の金属層が銀パラジ
ウム合金など貴金属を含有し、ガラスフリットにより焼
付け形成されてなるセラミック製リッド基板において、
形成する半田層中にボイドを生成させないようにし、も
って、封着時における半田の飛散を防止して封止不良を
なくし、半導体パッケージの不良の低減と共に歩留まり
の向上を図らんとするものである。The present invention has been devised in order to solve such problems, and a metal lid for forming a solder layer contains a noble metal such as a silver-palladium alloy and is formed by baking with a glass frit. On the board,
It is intended to prevent voids from being generated in the solder layer to be formed, prevent the solder from scattering at the time of sealing and eliminate defective sealing, and reduce the defects of the semiconductor package and improve the yield. .
【０００５】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の第１の手段に係るリッド基板は、セラミ
ック基板のパッケージ本体に対面する面の周縁に沿っ
て、貴金属を含有する金属からなる金属層がガラスフリ
ットにより焼付け形成され、前記金属層の上に、半田層
の形成される面として、ガラスフリットを含有しない金
属による金属層を形成したものである。そして、リッド
としては、セラミック基板と、このセラミック基板のパ
ッケージ本体に対面する面の周縁に沿って形成された金
属層と、この金属層の上に形成された半田層とを有して
なるものにおいて、少なくとも前記金属層の前記セラミ
ック基板と接する部位は、貴金属を含有する金属からな
るものとし、前記金属層と前記セラミック基板との界面
にガラスフリットが存在する一方、前記金属層と前記半
田層との界面にガラスフリットが存在していないことに
ある。In order to achieve the above object, the lid substrate according to the first means of the present invention contains a noble metal along the periphery of the surface of the ceramic substrate facing the package body. A metal layer made of a metal is formed by baking with a glass frit, and a metal layer containing no glass frit is formed on the metal layer as a surface on which a solder layer is formed. The lid includes a ceramic substrate, a metal layer formed along the periphery of the surface of the ceramic substrate facing the package body, and a solder layer formed on the metal layer. In at least the portion of the metal layer in contact with the ceramic substrate is made of a metal containing a noble metal, while a glass frit is present at the interface between the metal layer and the ceramic substrate, the metal layer and the solder layer. There is no glass frit at the interface with.
【０００６】また、第２の手段に係るリッド基板は、セ
ラミック基板のパッケージ本体に対面する面の周縁に沿
って、貴金属を含有する金属からなる金属層がガラスフ
リットにより焼付け形成され、前記金属層の半田層の形
成される面にガラスフリットが存在していないことにあ
る。そして、リッドとしては、セラミック基板と、この
セラミック基板のパッケージ本体に対面する面の周縁に
沿って形成された金属層と、この金属層の上に形成され
た半田層とを有してなるものにおいて、前記金属層は貴
金属を含有する金属からなるものとし、前記金属層と前
記セラミック基板との界面にガラスフリットが存在する
一方、前記金属層と前記半田層との界面にガラスフリッ
トが存在していないことにある。In the lid substrate according to the second means, a metal layer made of a metal containing a noble metal is formed by baking with a glass frit along the periphery of the surface of the ceramic substrate facing the package body. There is no glass frit on the surface on which the solder layer is formed. The lid includes a ceramic substrate, a metal layer formed along the periphery of the surface of the ceramic substrate facing the package body, and a solder layer formed on the metal layer. In the above, the metal layer is made of a metal containing a noble metal, and while the glass frit is present at the interface between the metal layer and the ceramic substrate, the glass frit is present at the interface between the metal layer and the solder layer. Not in that.
【０００７】[0007]
【作用】上記の第１および第２の手段に係るリッド基板
を溶融した半田中に浸漬すると、その金属層の表面であ
って半田層が形成される面に半田層が形成されるが、こ
の面にガラスフリットが存在若しくは露出していないか
ら、半田層中にボイドが生成されることが防止される。
また、上記いずれのリッドにおいても、前記金属層は半
田層が形成される下地であるが、その金属層と半田層と
の界面にガラスフリットが存在していないために、半田
層中にボイドは生成されないか、生成されても無視でき
る程度のものであり、したがって、封着時における半田
の飛散を防止する作用をする。かくして、本発明に係る
リッドでもって封着するときには、封止不良などの半導
体パッケージの不良の低減が図られる。When the lid substrate according to the first and second means is dipped in molten solder, a solder layer is formed on the surface of the metal layer on which the solder layer is formed. Since no glass frit is present or exposed on the surface, formation of voids in the solder layer is prevented.
Further, in any of the above lids, the metal layer is a base on which a solder layer is formed, but since there is no glass frit at the interface between the metal layer and the solder layer, voids are present in the solder layer. It is not generated, or even if it is generated, it is negligible, and therefore acts to prevent the solder from scattering during sealing. Thus, when sealing is performed with the lid according to the present invention, defects in the semiconductor package such as defective sealing can be reduced.
【０００８】[0008]
【実施例】本発明の第１の手段に係るリッド基板および
リッドを具体化した実施例について、図１ないし図４を
参照して詳細に説明する。本例におけるリッド基板１
は、一辺約２７ｍｍで略正方形に形成されたセラミック
基板２からなり、パッケージ本体に対面する面３の周縁
面（幅２ｍｍ）４と側面（厚さ０．７ｍｍ）５とに、次
記するようにして金属層６が形成されている。ただし、
本例では、金属層６の幅を、各辺の中央部の内側に凹部
１６を設けて部分的に幅狭としている（図２参照）。な
お、本例のセラミック基板２は、プレス成形による９０
％アルミナを焼成してなるものである。Embodiments of the lid substrate and the lid according to the first means of the present invention will be described in detail with reference to FIGS. 1 to 4. Lid substrate 1 in this example
Is composed of a ceramic substrate 2 having a side of about 27 mm and formed in a substantially square shape. The peripheral surface (width 2 mm) 4 and side surface (thickness 0.7 mm) 5 of the surface 3 facing the package body are described below. Thus, the metal layer 6 is formed. However,
In this example, the width of the metal layer 6 is partially narrowed by providing a recess 16 inside the center of each side (see FIG. 2). The ceramic substrate 2 of this example is 90
% Alumina is fired.
【０００９】本例においては、セラミック基板２の周縁
面４と側面５に、第１層目の金属層６ａとして、ガラス
フリット（図中黒丸）Ｇを１５重量％含む、Ａｇ−Ｐｄ
ペーストを１５μｍの厚さでスクリーン印刷して焼成、
形成し、その上に、第２層目の金属層６ｂとして、ガラ
スフリットを含まないＡｇ−Ｐｄペーストを１５μｍの
厚さで同様にして形成し、厚さ３０μｍの半田層形成用
の金属層６としたものである。すなわち、第１層目の金
属層６ａは、貴金属として銀パラジウム合金ペーストか
らなり、それに含まれるガラスフリットＧをセラミック
基板（質）２の表面に拡散、浸透させ、そのガラスフリ
ットＧによりセラミック質に密着（結合）させるための
ものであり、第２層目の金属層６ｂは、第１層の金属層
６ａに含まれるガラスフリットＧを露出させないように
覆うと共に、半田層形成用の直接の下地をなすためのも
のである。In this example, Ag-Pd containing 15% by weight of a glass frit (black circle in the figure) G as the first metal layer 6a on the peripheral surface 4 and the side surface 5 of the ceramic substrate 2 was used.
The paste is screen-printed with a thickness of 15 μm and baked,
Then, an Ag—Pd paste containing no glass frit is similarly formed thereon with a thickness of 15 μm as a second metal layer 6b, and a metal layer 6 for forming a solder layer with a thickness of 30 μm is formed. It is what That is, the first metal layer 6a is made of a silver-palladium alloy paste as a noble metal, and the glass frit G contained therein is diffused and permeated into the surface of the ceramic substrate (quality) 2, and the glass frit G transforms it into a ceramic material. The second metal layer 6b is for closely contacting (bonding), covers the glass frit G contained in the first metal layer 6a so as not to be exposed, and is a direct base for forming the solder layer. It is for making.
【００１０】しかして、上記の構成の本例のリッド１
を、フラックスに浸漬させた後、溶融半田中に浸漬して
引上げて冷却固化させ、周縁面４と側面５の金属層６ｂ
に所定厚さの半田層Ｈを選択的に形成した。この際、金
属層６の表面、つまり第２層目の金属層６ｂにはガラス
フリットＧが存在（露出）していないから半田が完全に
濡れる。かくして、図３に示すよう、ガラスフリットの
存在に起因して生成されるボイドのない半田層Ｈを備え
たリッド１を得ることができた。因みに、本例で使用し
た半田は、その組成がＰｂが８５ｗｔ％，Ｓｎが５ｗｔ
％，Ｂｉが７ｗｔ％，残部がＡｇ，Ｉｎからなるもの
で、固相線温度は２４０℃、液相線温度は２８０℃のも
のである。なお本例では、金属層６の幅を各辺の中央で
狭くしたため、図示はしないが溶融した半田の表面張力
により金属層６の幅の広い部位が狭い部位に相対して半
田が厚くつき、狭い部位が薄くなって半田層を内外に横
断する凹溝（ガスパス）となり、パッケージ内の高圧化
を防止するように設定されている。Thus, the lid 1 of the present example having the above-mentioned structure
Of the metal layer 6b on the peripheral surface 4 and the side surface 5 after being immersed in a flux and then immersed in molten solder and pulled up to be solidified by cooling.
Then, a solder layer H having a predetermined thickness was selectively formed. At this time, since the glass frit G is not present (exposed) on the surface of the metal layer 6, that is, the second metal layer 6b, the solder is completely wetted. Thus, as shown in FIG. 3, it was possible to obtain the lid 1 including the solder layer H having no void generated due to the presence of the glass frit. By the way, the solder used in this example has a composition of 85 wt% Pb and 5 wt% Sn.
%, Bi is 7 wt%, and the balance is Ag and In, and the solidus temperature is 240 ° C. and the liquidus temperature is 280 ° C. In this example, since the width of the metal layer 6 is narrowed at the center of each side, although not shown in the drawing, due to the surface tension of the molten solder, the wide portion of the metal layer 6 is thicker than the narrow portion of the solder, The narrow portion is thinned to form a concave groove (gas path) that traverses the solder layer inward and outward, and is set to prevent a high pressure in the package.
【００１１】さて、次に、本例のリッド基板１の具体的
な効果を確認するために、比較例（従来のリッド）とし
て、ガラスフリットを１５重量％含むＡｇ−Ｐｄペース
トを１５μｍの厚さで前同様にして形成した金属層の上
に、同様にして半田層を形成してなるリッドをつくり、
半田層中のボイドの数を金属顕微鏡により比較してみ
た。ただし試料数は各々１０個とした。結果は表１（左
欄）に示したとおりである。Next, in order to confirm the specific effect of the lid substrate 1 of this example, as a comparative example (conventional lid), an Ag-Pd paste containing 15% by weight of glass frit was formed to a thickness of 15 μm. In the same way as above, on the metal layer formed in the same way as above, make a lid formed by similarly forming a solder layer,
The number of voids in the solder layer was compared by a metallurgical microscope. However, the number of samples was 10, respectively. The results are as shown in Table 1 (left column).
【表１】 表１に示した結果の通り、ボイドの数は、本例のものは
いずれも、０〜６個／ｃｍ2 であったのに対し、比較例
のものはいずれも、１００００〜２５０００個／ｃｍ2
であった。さらに、こうして得たリッド（各々１００
個）により、パッケージ本体（図示しない）を封着し
て、封止時の半田の飛散の発生率を比較した。結果は表
１（右欄）に示したとおりで、半田の飛散は、本例のも
のは０％であったが、比較例は１０％（個）みられた。
これらのことは、とりもなおさず本発明の効果を実証す
るものである。一方、本例程度のボイドの数は飛散の原
因とならないことが理解される。[Table 1] As shown in the results shown in Table 1, the number of voids was 0 to 6 / cm @ 2 in all of the examples, whereas the number of voids was 10,000 to 25,000 / cm @ 2 in all of the comparative examples.
Met. In addition, the lids thus obtained (each 100
The package main body (not shown) was sealed with each other, and the occurrence rates of solder scattering at the time of sealing were compared. The results are shown in Table 1 (right column), and the solder scattering was 0% in this example, but was 10% in the comparative example.
These facts at all prove the effect of the present invention. On the other hand, it is understood that the number of voids of this example does not cause scattering.
【００１２】なお、金属層６の幅は本例のように各辺の
中央で狭くするなど、部分的又は間欠的に、狭く又は広
く変化して形成しておくとよい。こうしておけば、前記
したように、半田層の形成過程でそれを横断する凹溝が
自動的にできるからである。また、本例では、セラミッ
ク基板２におけるパッケージ本体に対面する面３の周縁
面４およびこれと交差する側面５に、金属層６を形成し
た場合を例示したが、周縁面４のみに形成しておいても
よい。ただし、本例のように両面に形成する場合には、
その両面４，５が交差する角（稜線部位）には面取を付
与しておくとよい。面取が付与されてないと角に金属層
がうまく形成されないためにセラミックが露出し、それ
に起因するメニスカス不良が発生することがあるが、面
取を付しておけば防止できるからである。因みに、面取
は、丸みの場合には約Ｒ２５〜１５０μｍの範囲内で、
また４５度面取などによる場合は、約Ｃ２５〜１５０μ
ｍの範囲内で付すとよい。The width of the metal layer 6 may be narrowed or widened partially or intermittently, such as by narrowing the width at the center of each side as in this example. This is because, as described above, when the solder layer is formed, a groove crossing the solder layer is automatically formed in the process of forming the solder layer. Further, in this example, the metal layer 6 is formed on the peripheral surface 4 of the surface 3 of the ceramic substrate 2 facing the package body and the side surface 5 intersecting with the peripheral surface 4, but it is formed only on the peripheral surface 4. You can leave it. However, when forming on both sides like this example,
It is advisable to chamfer the corners (ridge line portions) where the two surfaces 4 and 5 intersect. If chamfering is not applied, the metal layer is not properly formed at the corners, and the ceramic may be exposed, resulting in defective meniscus. However, chamfering can prevent this. Incidentally, chamfering is within the range of about R25 to 150 μm in the case of roundness,
When chamfering at 45 degrees, C25-150μ
It is good to add it within the range of m.
【００１３】上記実施例では、金属層６を２層構造と
し、第２層目の金属層６ｂをガラスフリットを含有しな
い金属により形成し、その表面を半田層の形成される面
としたが、本発明の第１の手段に係るリッド基板におい
ては、金属層の数にかかわらず半田層の形成される面に
ガラスフリットが存在していなければよい。半田層中に
ボイドが生成されないからである。すなわち、３層以上
の金属層からなる構造とし、最外側の金属層をガラスフ
リットが含まれてない金属厚膜とすることでも具体化で
きる。In the above embodiment, the metal layer 6 has a two-layer structure, the second metal layer 6b is formed of a metal not containing glass frit, and the surface thereof is the surface on which the solder layer is formed. In the lid substrate according to the first means of the present invention, it is sufficient that the glass frit does not exist on the surface on which the solder layer is formed, regardless of the number of metal layers. This is because voids are not generated in the solder layer. That is, it can be embodied by having a structure composed of three or more metal layers and forming the outermost metal layer as a thick metal film containing no glass frit.
【００１４】また本発明の第２の手段に係るリッド基板
およびリッドを具体化した実施例としては、次のものを
挙げることができる。すなわち、図４に示したリッド基
板１のように、セラミック基板２にガラスフリットＧを
含む例えばＡｇ−Ｐｄペーストを一層、印刷、焼成して
金属層６を形成した後、その金属層６の表面を適度の濃
度（３〜５％）のフッ酸溶液などに所定時間（数十
秒）、浸漬する等して洗浄することで、表面に露出して
いるガラスフリットのみを選択的に溶解（エッチング）
して除去し、半田層の形成される面にガラスフリットが
存在しないように処理する。そして、この処理後に、前
例と同様にして半田層Ｈを形成すれば、金属層６と半田
層Ｈとの界面にガラスフリットの存在していないリッド
を得ることができる。本例においては、金属層６の焼付
け形成工程が一度で済む分、こうした溶解装置（設備）
を有する場合には効率的である。なおこの場合、或いは
前例のような複数層構造における金属厚膜（第１層）の
厚さは、５〜２５μｍ程度が適当である。５μｍ未満で
あると、薄過ぎるためにセラミック側に拡散されるガラ
スフリットの量不足となって密着強度が低くなるためで
ある。また２５μｍを超えるようだと、厚過ぎるために
焼成過程で厚膜中のガラスフリットがセラミック側に拡
散されきれず、表面側にガラスフリットが多く残ってし
まい、その上に形成される半田層形成用の金属層中にガ
ラスフリットが大量に拡散して表面に露出してしまうこ
とがあるからである。The following can be mentioned as specific examples of the lid substrate and the lid according to the second means of the present invention. That is, like the lid substrate 1 shown in FIG. 4, one layer of, for example, Ag—Pd paste containing the glass frit G is printed and fired on the ceramic substrate 2 to form the metal layer 6, and then the surface of the metal layer 6 is formed. The glass frit exposed on the surface is selectively dissolved (etching) by rinsing by dipping in a hydrofluoric acid solution with an appropriate concentration (3-5%) for a predetermined time (tens of seconds). )
And removed so that the glass frit is not present on the surface on which the solder layer is formed. Then, after this process, if the solder layer H is formed in the same manner as in the previous example, it is possible to obtain a lid in which no glass frit is present at the interface between the metal layer 6 and the solder layer H. In this example, since the baking formation process of the metal layer 6 is completed once, such a melting device (equipment)
Is efficient if it has In this case, or in the multi-layer structure as in the previous example, the thickness of the metal thick film (first layer) is preferably about 5 to 25 μm. This is because if the thickness is less than 5 μm, the amount of glass frit diffused to the ceramic side becomes insufficient because the thickness is too thin, and the adhesion strength decreases. On the other hand, if it exceeds 25 μm, the glass frit in the thick film cannot be diffused to the ceramic side during the firing process because it is too thick, and a large amount of glass frit remains on the surface side, forming the solder layer formed on it. This is because a large amount of glass frit may be diffused in the metal layer for use and exposed on the surface.
【００１５】なお、上記実施例では、セラミック基板に
ガラスフリットにより焼付け形成される貴金属を含有す
る金属層として、Ａｇ−Ｐｄペーストを印刷焼成（厚膜
メタライズ）した場合を例示したがこれに限定されるも
のではない。金（Ａｕ）、銀（Ａｇ）、白金（Ｐｔ）、
パラジウム（Ｐｄ）、或いはロジウム（Ｒｈ）などの貴
金属、又はＡｇ−Ｐｔ合金などの合金のペーストを印刷
し、焼付け形成することでも具体化できる。また、貴金
属又はその合金に他の卑金属を含有する合金（ペース
ト）を印刷して焼付け形成することでも具体化できる。
また、本発明の第１の手段を具体化した上記実施例で
は、２層構造とし、第１層目、第２層目ともに同質のも
のを印刷焼成したが、本発明においては、異質のもので
複数層構造とすることも可能である。さらに、本発明に
おいては、半田層の形成される面をなす金属層は、半田
層が濡れて形成されるものであればよい。したがってコ
ストアップとはなるものの、例えばセラミック基板に接
する部位つまり第１層目にガラスフリット入り前記金属
ペーストを印刷、焼成して金属厚膜とし、その上に、Ｎ
ｉ鍍金をした後、さらに金、半田、又は錫を鍍金するこ
とでも具体化できる。ただし、金鍍金についてはＮｉ鍍
金を介さなくともよい。In the above embodiment, the case where the Ag-Pd paste was printed and fired (thick film metallization) as the metal layer containing the noble metal formed by baking the glass frit on the ceramic substrate was illustrated, but the present invention is not limited to this. Not something. Gold (Au), silver (Ag), platinum (Pt),
It can also be embodied by printing a paste of a noble metal such as palladium (Pd) or rhodium (Rh) or an alloy such as an Ag-Pt alloy and baking it. It can also be embodied by printing an alloy (paste) containing another base metal on a noble metal or its alloy and baking it.
Further, in the above-described embodiment in which the first means of the present invention is embodied, the two-layer structure is used, and the same first and second layers are printed and fired, but in the present invention, different ones are used. It is also possible to have a multi-layer structure. Further, in the present invention, the metal layer forming the surface on which the solder layer is formed may be any layer as long as the solder layer is wet. Therefore, although the cost is increased, for example, the metal paste containing glass frit is printed and fired on a portion in contact with the ceramic substrate, that is, on the first layer to form a thick metal film.
It can also be embodied by plating i, then gold, solder, or tin. However, the gold plating does not have to be through the Ni plating.
【００１６】なお、本発明に係るリッドに形成される半
田層は、Ｐｂ−Ｓｎ系、Ｐｂ−Ｓｎ−Ａｇ系、Ｐｂ−Ｉ
ｎ−Ａｇ系のものなど適宜のものを使用できるし、その
形成手法は、半田プリフォームを載せてリフローさせる
ことでも形成できる。また、本発明におけるリッド基板
を成すセラミックとしては、アルミナ以外に、窒化アル
ミ、ムライト、ジルコニアなどが挙げられる。The solder layer formed on the lid according to the present invention is made of Pb-Sn system, Pb-Sn-Ag system, Pb-I.
An appropriate material such as an n-Ag-based material can be used, and the formation method can also be formed by placing a solder preform and reflowing. In addition to alumina, examples of ceramics that form the lid substrate in the present invention include aluminum nitride, mullite, and zirconia.
【００１７】[0017]
【発明の効果】以上の説明から明らかなように、本発明
に係る半導体パッケージ用のセラミック製リッド基板の
第１および第２の手段においては、溶融した半田中に浸
漬したりして金属層の表面に半田層を形成する場合、そ
の表面にガラスフリットが存在していないから、形成さ
れる半田層中にボイドが生成されることが有効に防止さ
れる。また、本発明に係るリッドは、いずれにおいて
も、半田層の下地としての金属層と半田層との界面にガ
ラスフリットが存在していないために、半田層中のボイ
ドが著しく少なく、したがって、パッケージ本体を封着
した場合には、半田層中のボイドに起因する半田の飛
散、さらにはこれによる短絡や外観不良が有効に防止さ
れる。この結果、半導体パッケージの歩留まりの向上や
低コスト化を図ることができる。また封止後においても
半田層中に大きなボイドを残さないため、気密性の高い
高品質の半導体パッケージを得ることができる。さら
に、こうした効果により、従来不向きとされていた大型
パッケージのリッドにも安価なセラミックが適すること
となり、そのコストの大幅な低減が期待される。As is apparent from the above description, in the first and second means of the ceramic lid substrate for a semiconductor package according to the present invention, the metal layer of the metal layer is formed by being immersed in molten solder. When the solder layer is formed on the surface, no glass frit is present on the surface, so that the formation of voids in the formed solder layer is effectively prevented. Further, in any of the lids according to the present invention, since there is no glass frit at the interface between the metal layer and the solder layer as the base of the solder layer, the voids in the solder layer are extremely small, and therefore the package When the main body is sealed, the solder is effectively prevented from scattering due to voids in the solder layer, and further short-circuiting and poor appearance due to the scattering. As a result, the yield of semiconductor packages can be improved and the cost can be reduced. Further, since a large void is not left in the solder layer even after the sealing, it is possible to obtain a high quality semiconductor package having high airtightness. Furthermore, due to these effects, an inexpensive ceramic is suitable for a lid of a large package, which is conventionally unsuitable, and it is expected that the cost will be significantly reduced.
【図１】本発明に係る半導体パッケージ用のセラミック
製リッド基板を具体化した実施例を説明する要部拡大断
面図である。FIG. 1 is an enlarged sectional view of an essential part for explaining an embodiment in which a ceramic lid substrate for a semiconductor package according to the present invention is embodied.
【図２】図１のリッド基板のパッケージ本体に対面する
面を説明する平面図である。FIG. 2 is a plan view illustrating a surface of the lid substrate of FIG. 1 facing a package body.
【図３】図１のリッド基板に半田層を形成してなるセラ
ミック製リッドを説明する断面図である。FIG. 3 is a cross-sectional view illustrating a ceramic lid formed by forming a solder layer on the lid substrate of FIG.
【図４】本発明の第２の手段に係る半導体パッケージ用
のセラミック製リッド基板およびセラミック製リッドを
具体化した実施例を説明する要部拡大断面図である。FIG. 4 is an enlarged sectional view of essential parts for explaining an embodiment in which a ceramic lid substrate for a semiconductor package and a ceramic lid according to a second means of the present invention are embodied.
【図５】従来の半導体パッケージ用のセラミック製リッ
ドの部分断面拡大図である。FIG. 5 is an enlarged partial cross-sectional view of a conventional ceramic lid for a semiconductor package.
【図６】図５のリッドで封着する過程を説明する部分断
面図である。FIG. 6 is a partial cross-sectional view illustrating a process of sealing with the lid of FIG.
１ 半導体パッケージ用のセラミック製リッド基板 ２ セラミック基板 ３ パッケージ本体に対面する面 ４ 周縁面 ５ 側面 ６ 金属層 ６ａ 第１層目の金属層（貴金属を含有する金属からな
る金属層） ６ｂ 第２層目の金属層（半田層の形成される面として
の金属層） Ｈ 半田層 Ｖ ボイド Ｇ ガラスフリット1 Ceramic Lid Substrate for Semiconductor Package 2 Ceramic Substrate 3 Surface Facing Package Body 4 Peripheral Surface 5 Side 6 Metal Layer 6a First Metal Layer (Metal Layer Containing Noble Metal) 6b Second Layer Eye metal layer (metal layer as the surface on which the solder layer is formed) H Solder layer V Void G Glass frit
Claims (4)
する面の周縁に沿って、貴金属を含有する金属からなる
金属層がガラスフリットにより焼付け形成され、前記金
属層の上に、半田層の形成される面として、ガラスフリ
ットを含有しない金属による金属層が形成されているこ
とを特徴とする、半導体パッケージ用のセラミック製リ
ッド基板。1. A metal layer made of a metal containing a noble metal is formed by baking with a glass frit along the periphery of the surface of the ceramic substrate facing the package body, and a solder layer is formed on the metal layer. A ceramic lid substrate for a semiconductor package, characterized in that a metal layer made of a metal containing no glass frit is formed on the surface.
のパッケージ本体に対面する面の周縁に沿って形成され
た金属層と、この金属層の上に形成された半田層とを有
してなる半導体パッケージ用のセラミック製リッドであ
って、少なくとも前記金属層の前記セラミック基板と接
する部位は貴金属を含有する金属からなり、前記金属層
と前記セラミック基板との界面にガラスフリットが存在
する一方、前記金属層と前記半田層との界面にガラスフ
リットが存在していないことを特徴とする、半導体パッ
ケージ用のセラミック製リッド。2. A semiconductor package comprising a ceramic substrate, a metal layer formed along a peripheral edge of a surface of the ceramic substrate facing the package body, and a solder layer formed on the metal layer. A ceramic lid for use, wherein at least a portion of the metal layer in contact with the ceramic substrate is made of a metal containing a noble metal, and a glass frit is present at an interface between the metal layer and the ceramic substrate, while the metal layer is provided. A ceramic lid for a semiconductor package, characterized in that no glass frit is present at the interface between the solder layer and the solder layer.
する面の周縁に沿って、貴金属を含有する金属からなる
金属層がガラスフリットにより焼付け形成され、前記金
属層の半田層の形成される面にガラスフリットが存在し
ていないことを特徴とする、半導体パッケージ用のセラ
ミック製リッド基板。3. A metal layer made of a metal containing a noble metal is formed by baking along a peripheral edge of a surface of the ceramic substrate facing the package body, and a glass layer is formed on the surface of the metal layer on which the solder layer is formed. Ceramic lid substrate for semiconductor packages, characterized by the absence of frit.
のパッケージ本体に対面する面の周縁に沿って形成され
た金属層と、この金属層の上に形成された半田層とを有
してなる半導体パッケージ用のセラミック製リッドであ
って、前記金属層は貴金属を含有する金属からなり、前
記金属層と前記セラミック基板との界面にガラスフリッ
トが存在する一方、前記金属層と前記半田層との界面に
ガラスフリットが存在していないことを特徴とする、半
導体パッケージ用のセラミック製リッド。4. A semiconductor package comprising a ceramic substrate, a metal layer formed along the periphery of the surface of the ceramic substrate facing the package body, and a solder layer formed on the metal layer. A ceramic lid for use, wherein the metal layer is made of a metal containing a noble metal, and a glass frit is present at the interface between the metal layer and the ceramic substrate, while at the interface between the metal layer and the solder layer. Ceramic lid for semiconductor packages, characterized by the absence of glass frit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23538993A JP3369665B2 (en) | 1993-08-27 | 1993-08-27 | Ceramic lid substrate and ceramic lid for semiconductor package |
| MYPI94002182A MY112400A (en) | 1993-08-27 | 1994-08-19 | Ceramic lid assembly for semiconductor packages. |
| US08/690,460 US5825086A (en) | 1993-08-27 | 1996-07-29 | Ceramic lid assembly for semiconductor packages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23538993A JP3369665B2 (en) | 1993-08-27 | 1993-08-27 | Ceramic lid substrate and ceramic lid for semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0766315A true JPH0766315A (en) | 1995-03-10 |
| JP3369665B2 JP3369665B2 (en) | 2003-01-20 |
Family
ID=16985363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23538993A Expired - Fee Related JP3369665B2 (en) | 1993-08-27 | 1993-08-27 | Ceramic lid substrate and ceramic lid for semiconductor package |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5825086A (en) |
| JP (1) | JP3369665B2 (en) |
| MY (1) | MY112400A (en) |
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|---|---|---|---|---|
| JP2008192964A (en) * | 2007-02-07 | 2008-08-21 | Denso Corp | Mounting method of semiconductor chip |
| WO2013137214A1 (en) * | 2012-03-14 | 2013-09-19 | 日本特殊陶業株式会社 | Ceramic substrate and process for producing same |
| JP2014049561A (en) * | 2012-08-30 | 2014-03-17 | Kyocera Corp | Package for housing electronic element, and electronic device |
| WO2017135139A1 (en) * | 2016-02-01 | 2017-08-10 | 三菱マテリアル株式会社 | METAL MEMBER WITH Ag UNDERLAYER, INSULATED CIRCUIT BOARD WITH Ag UNDERLAYER, SEMICONDUCTOR DEVICE, INSULATED CIRCUIT BOARD WITH HEATSINK, AND METHOD OF MANUFACTURING METAL MEMBER WITH Ag UNDERLAYER |
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|---|---|---|---|---|
| DE19910078A1 (en) | 1999-03-08 | 2000-09-28 | Bosch Gmbh Robert | Process for increasing the manufacturing reliability of soldered connections |
| TW200527620A (en) * | 2004-02-04 | 2005-08-16 | Siliconware Precision Industries Co Ltd | Semiconductor package |
| EP4060723A1 (en) * | 2014-10-01 | 2022-09-21 | Materion Corporation | Cover lid with selective and edge metallization |
| US10756298B2 (en) | 2017-11-03 | 2020-08-25 | OLEDWorks LLC | Solder hermetic sealing for OLEDs |
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| US3590468A (en) * | 1969-02-19 | 1971-07-06 | Sperry Rand Corp | Glassy phase method for making pure alumina-to-metal hermetic seals |
| GB1514595A (en) * | 1975-03-03 | 1978-06-14 | Hughes Aircraft Co | Package for hermetically sealing electronic circuits |
| JPS5498178A (en) * | 1978-01-20 | 1979-08-02 | Hitachi Ltd | Electronic device |
| US4291815B1 (en) * | 1980-02-19 | 1998-09-29 | Semiconductor Packaging Materi | Ceramic lid assembly for hermetic sealing of a semiconductor chip |
| US4356047A (en) * | 1980-02-19 | 1982-10-26 | Consolidated Refining Co., Inc. | Method of making ceramic lid assembly for hermetic sealing of a semiconductor chip |
| JPS60115247A (en) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | Semiconductor device |
| JPS60173861A (en) * | 1984-02-20 | 1985-09-07 | Hitachi Ltd | Semiconductor device |
| US4748085A (en) * | 1985-11-16 | 1988-05-31 | Narumi China Corporation | Multilayer ceramic circuit board fired at a low temperature |
| JPH0653253B2 (en) * | 1986-11-08 | 1994-07-20 | 松下電工株式会社 | Roughening method of ceramic substrate |
| US4746583A (en) * | 1986-11-21 | 1988-05-24 | Indium Corporation | Ceramic combined cover |
| US4851301A (en) * | 1988-02-12 | 1989-07-25 | Motorola, Inc. | Solder bonding with improved peel strength |
| JPH02250359A (en) * | 1989-03-24 | 1990-10-08 | Hitachi Ltd | Semiconductor device |
| JP2927010B2 (en) * | 1991-03-01 | 1999-07-28 | 株式会社日立製作所 | Semiconductor package |
-
1993
- 1993-08-27 JP JP23538993A patent/JP3369665B2/en not_active Expired - Fee Related
-
1994
- 1994-08-19 MY MYPI94002182A patent/MY112400A/en unknown
-
1996
- 1996-07-29 US US08/690,460 patent/US5825086A/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008192964A (en) * | 2007-02-07 | 2008-08-21 | Denso Corp | Mounting method of semiconductor chip |
| WO2013137214A1 (en) * | 2012-03-14 | 2013-09-19 | 日本特殊陶業株式会社 | Ceramic substrate and process for producing same |
| US9006582B2 (en) | 2012-03-14 | 2015-04-14 | Ngk Spark Plug Co., Ltd. | Ceramic substrate and process for producing same |
| JPWO2013137214A1 (en) * | 2012-03-14 | 2015-08-03 | 日本特殊陶業株式会社 | Ceramic substrate and manufacturing method thereof |
| JP2014049561A (en) * | 2012-08-30 | 2014-03-17 | Kyocera Corp | Package for housing electronic element, and electronic device |
| WO2017135139A1 (en) * | 2016-02-01 | 2017-08-10 | 三菱マテリアル株式会社 | METAL MEMBER WITH Ag UNDERLAYER, INSULATED CIRCUIT BOARD WITH Ag UNDERLAYER, SEMICONDUCTOR DEVICE, INSULATED CIRCUIT BOARD WITH HEATSINK, AND METHOD OF MANUFACTURING METAL MEMBER WITH Ag UNDERLAYER |
| JP2017139260A (en) * | 2016-02-01 | 2017-08-10 | 三菱マテリアル株式会社 | METAL MEMBER WITH Ag GROUND LAYER, INSULATION CIRCUIT BOARD WITH Ag GROUND LAYER, SEMICONDUCTOR DEVICE, INSULATION CIRCUIT BOARD WITH HEAT SINK, AND METHOD OF MANUFACTURING METAL MEMBER WITH Ag GROUND LAYER |
| US10734297B2 (en) | 2016-02-01 | 2020-08-04 | Mitsubishi Materials Corporation | Ag underlayer-attached metallic member, Ag underlayer-attached insulating circuit substrate,semiconductor device, heat sink-attached insulating circuit substrate, and method for manufacturing Ag underlayer-attached metallic member |
Also Published As
| Publication number | Publication date |
|---|---|
| MY112400A (en) | 2001-06-30 |
| US5825086A (en) | 1998-10-20 |
| JP3369665B2 (en) | 2003-01-20 |
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| LAPS | Cancellation because of no payment of annual fees |