JP2654872B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a lead frame provided with a multi-layered coating of a dissimilar metal useful for preventing thermal diffusion, electromigration and battery corrosion of metals. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, high integration and high performance have progressed, and accordingly, semiconductor packages have been reduced in size or the number of pins of the same size has been increased. Therefore, a QFP (Qua) whose partial cross section is shown in FIG.
d Flat Package) type semiconductor device 1
In the case of 0, for example, the outer lead pitch is required to be 0.3 mm and the number of pins is required to be 200 to 300 pins. Therefore,
The width and spacing of the outer leads 11 and the inner leads 12 are reduced, and the thickness of the surface coating layer of the outer leads 11 and the inner leads 12 is reduced to cope with the increase in the number of pins within the same size. It was necessary to prevent electromigration. The conventional chip-shaped semiconductor device 10 uses a lead frame metal member formed by etching or pressing a metal strip material such as a Cu-Fe or Ni-Fe alloy into a required shape. . The lead frame includes an element mounting portion 14 on which the semiconductor element 13 is mounted, and the semiconductor element 1
3 are connected to each other by an inner lead 12 for forming an electric conduction circuit by connecting the pad portions 15 of the third via a wire 16 and a connecting portion for holding the same, and constitute an external connection terminal corresponding to the inner lead 12. The outer lead 11 is provided. The lead frame is provided with a base plating layer 17 of Ni or the like on the entire surface.
A in the wire bonding part 18 and the element mounting part 14
A partial plating 19 of a noble metal such as g is formed. Therefore, in manufacturing the semiconductor device 10, generally, the semiconductor element 13 is bonded to the element mounting portion 14 of the lead frame, one end of the wire 16 is bonded to the pad portion 15 of the semiconductor element 13, and the like. After the ends are connected to the wire bonding portions 18 at the tips of the inner leads 12 to form an electric circuit, they are covered with an insulating resin 20 and sealed. Then, after separating and forming a connecting portion (not shown) having the outer lead 11 protruding around the insulating resin 20, a solder coating layer 21 is formed on the protruding outer lead 11 to manufacture a semiconductor device. .

[0003]

According to the plating coating structure of the lead frame used in the semiconductor device 10 according to the conventional example, the width and the interval of the outer lead 11 and the inner lead 12 are narrowed corresponding to the above-mentioned multi-pin structure. Accordingly, it is necessary to reduce the thickness of the plating layer on the surface. However, when the coating layer is made thinner, there is a disadvantage that a large number of pinholes, which become a major defect against corrosion of the plating coating layer, are generated depending on the plating solution and plating conditions. Further, when the pinhole is present in the plating coating layer, a potential difference is generated between the base metal layer and the uppermost plated metal layer through the pinhole, and a local battery is formed. A battery action occurs between the metal layer and the plating metal layer, and the metal of the base metal layer dissolves and precipitates and oxidizes through the pinholes, contaminating the surface of the plating metal on the uppermost layer and reducing solder wettability. In addition, there is a disadvantage that the base metal layer is corroded. In addition, the spacing between the leads of the outer leads 11 and the inner leads 12 is reduced in accordance with the increase in the number of pins, and Ag or the like forming the partial plating layer 19 formed at the tip of the inner leads 12 is made of the insulating resin 20. However, there is a disadvantage that the lead is short-circuited due to deposition on the coating sealing portion made of, causing electromigration. In addition, there is a problem that the quality and reliability of the semiconductor device are deteriorated, such as formation of a solder bridge between the leads of the outer leads 11. Therefore, in the semiconductor device 10 according to the conventional example described above, there is a problem that the quality and long-term reliability of the semiconductor device are reduced, and the cost is increased due to a decrease in yield. The present invention reduces the thickness of the cover layer of a lead frame using a semiconductor device, reduces pinholes that are a major defect against local cell action corrosion and surface contamination, further prevents electromigration, Electrical conductivity which is a prerequisite,
An object of the present invention is to provide a high-quality semiconductor device that satisfies low contact properties, bonding properties, and solder wettability and can maintain long-term reliability.

[0004]

According to the present invention, there is provided a semiconductor device comprising:
The semiconductor device according to the above item, a lead frame made of a metal member provided with an element mounting portion on which required shape processing is performed, an inner lead and an outer lead, a semiconductor element mounted on the element mounting portion, and the semiconductor device. A wire forming an electrical conduction circuit by connecting a pad portion of the element and the tip of the inner lead, and an insulating synthetic resin covering and sealing a predetermined area of the lead frame including the semiconductor element, the wire and the inner lead A Ni strike layer is provided on the surface of the metal member of the lead frame, and a Pd layer is formed on the Ni strike layer, and the uppermost portion is a Pd layer, and the Sn-Co alloy layer and the Pd layer Are sequentially laminated, and a plurality of thin plating layers having a two-layer structure are formed. In addition, the semiconductor device according to claim 2 is a lead frame made of a metal member having an element mounting portion on which required shape processing has been performed, an inner lead and an outer lead,
A semiconductor element mounted on the element mounting portion, a wire for connecting a pad portion of the semiconductor element and the tip of the inner lead to form an electrical conduction circuit, and the semiconductor element, the wire and the inner lead; In a semiconductor device having an insulating synthetic resin for covering and sealing a predetermined region of a lead frame, a Ni strike layer is provided on a surface of a metal member of the lead frame, and an uppermost portion is provided on the Ni strike layer. A plurality of thin plating layers of a two-layer structure in which a Ni—Co alloy layer and a Pd layer are sequentially stacked are formed as Pd layers.

[0005]

In the semiconductor device according to the first and second aspects,
Since the metal member forming the lead frame has a plurality of two-layer thin plating layers formed of a Pd layer on the upper portion, the metal member penetrates the metal coating layer provided with the plurality of two-layer thin plating layers. As a result, the number of pinholes reaching the metal member can be reduced, so that the metal member is less likely to diffuse and stain the surface of the metal coating layer.
Since the uppermost layer is a Pd layer, an oxide film is not formed, the solder wettability is improved, and a short circuit between leads due to electromigration is prevented. Further, between the uppermost layer and the metal member, an Sn—Co alloy layer for alleviating the potential difference between the uppermost Pd layer and the metal member is connected to the Pd layer.
Since an intermediate plating layer composed of a d layer or a Ni—Co alloy layer and a Pd layer is provided, it has an effect of preventing battery corrosion between metal members and each plating layer and precipitation oxidation of the uppermost Pd layer. Further, since the Ni strike layer is provided on the surface of the metal member, heat diffusion to the metal coating layer such as Cu contained in the metal member can be prevented, and further, contamination of the plating solution due to leaching of the Cu or the like can be prevented. . Further, if residual stress in the metal member is removed, there is an effect of preventing stress corrosion cracking.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will now be described with reference to the accompanying drawings to provide an understanding of the present invention. Here, FIG. 1 shows a partial cross-sectional view of a semiconductor device 23 according to one embodiment of the present invention. The semiconductor device 23 according to one embodiment of the present invention includes an element mounting portion 24 and an inner lead 2.
5 and a lead frame including outer leads 26;
The semiconductor element 2 bonded to the element mounting portion 24
7, a wire 29 forming one end of an electric circuit by being connected to the pad 28 of the semiconductor element 27 at one end and the other end to the inner lead 25, and an insulating synthetic resin 30 for covering and sealing these. It is configured.

The lead frame is made of a Cu-Fe (or Ni-Fe) metal member, and has an element mounting portion 24, inner leads 25, and outer leads 26 formed by pressing or etching.
In addition, when the press working is performed, a stress relief annealing process is performed to remove the residual stress. And
In the lead frame, a metal coating layer 31 is formed by plating together with a connecting portion (not shown) formed outside the outer lead 26. Each of the metal coating layers 31 forms a base layer made of a thin plating layer. A plurality of thin plating layers having a two-layer structure in which a Ni strike layer 32, a Sn—Co alloy layer 33, and a Pd layer 34 are sequentially stacked,
The Pd layer is exposed at the top. Here, the Ni strike layer 32 is provided in order to prevent thermal diffusion of Cu and the like contained in the metal member and to prevent plating solution contamination. Then, the Sn—Co alloy layer 33 and the Pd layer 34 in the middle part cover the pinholes of the underlayer, and the metal member and the uppermost Pd layer 3 are stochastically formed.
4 prevents the generation of a local battery. And even if the local battery is formed between the metal member and the uppermost layer even if the upper and lower pinholes are continuous, the potential difference between them is reduced by providing the intermediate layer, and the battery member corrodes and acts on the metal member. In addition to preventing the deposition and oxidation of metal in the upper layer, the short circuit between the leads due to electromigration is eliminated and the reliability of the semiconductor device is improved.

After bonding the semiconductor element 27 to the element mounting part 24 of the lead frame on which the metal coating layer 31 is formed, the pad part 28 of the semiconductor element 27 and the tip part 35 of the inner lead 25 are connected to a wire. 29 form an electric circuit. Thereafter, the tip of the element mounting portion 24, the semiconductor element 27, the inner lead 25, and the outer lead 26 are covered and sealed with the insulating synthetic resin 30, and the tip of the outer lead 26 protruding from the covered sealing region is provided. The semiconductor device 23 is completed by separating the connecting portion (not shown) integrally joined.

Thus, the Sn—Co alloy layer 3
Since a plurality of thin plating layers having a two-layer structure composed of the Pd layer 3 and the Pd layer 34 are formed, the penetration of pinholes can be stochastically eliminated, so that the corrosion resistance is improved and the uppermost Pd layer 34 is not contaminated. Therefore, the solder wettability is improved. In addition, the S
It is also possible to form a Ni-Co alloy layer instead of the n-Co alloy layer, and similar effects can be expected.

[0010]

As is apparent from the above description, the semiconductor device according to the first and second aspects of the present invention comprises a Sn-Co alloy layer and a Pd layer or a Ni-Co alloy layer and a Pd layer in the middle.
Since a lead frame in which a plurality of thin layers having a layer structure are formed is used, pinholes penetrating through the coating layer of the metal member are stochastically reduced. Therefore, corrosion due to the local battery action between the metal member and the uppermost layer due to the pinhole can be prevented, and contamination due to precipitation and oxidation of the metal member on the uppermost layer can be prevented. Therefore, it is possible to provide a high-quality semiconductor device that satisfies electric conductivity, low contact property, bonding property, and solder wettability, which are essential conditions of the semiconductor device, and can maintain long-term reliability. Further, since the Pd layer is formed on the uppermost layer, an oxide film is not formed, so that the solder wettability is improved, and furthermore, a short circuit between leads due to electromigration can be prevented. Further, since the lowermost layer is provided with the Ni strike layer, it is possible to prevent thermal diffusion of Cu and the like contained in the metal member, and further, to prevent contamination of the plating solution in the plating process.

[Brief description of the drawings]

FIG. 1 is a partial sectional view of a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor device according to a conventional example.

[Explanation of symbols]

Reference Signs List 23 semiconductor device 24 element mounting part 25 inner lead 26 outer lead 27 semiconductor element 28 pad part 29 wire 30 insulating synthetic resin 31 metal coating layer 32 Ni strike layer 33 Sn-Co alloy layer 34 Pd layer 35 tip

Claims (2)

(57) [Claims] An element mounting portion on which required shape processing has been performed;
A lead frame made of a metal member having an inner lead and an outer lead, a semiconductor element mounted on the element mounting portion, and a pad portion of the semiconductor element connected to a tip of the inner lead to form an electric conduction circuit A semiconductor device comprising: a wire to be formed; and an insulating synthetic resin that covers and seals a predetermined region of the lead frame including the semiconductor element, the wire, and the inner lead. A plurality of thin plating layers having a two-layer structure in which an uppermost part is a Pd layer and a Sn-Co alloy layer and a Pd layer are sequentially stacked on the Ni strike layer. A semiconductor device characterized by the above-mentioned. 2. An element mounting portion on which required shape processing has been performed.
A lead frame made of a metal member having an inner lead and an outer lead, a semiconductor element mounted on the element mounting portion, and a pad portion of the semiconductor element connected to a tip of the inner lead to form an electric conduction circuit A semiconductor device comprising: a wire to be formed; and an insulating synthetic resin that covers and seals a predetermined region of the lead frame including the semiconductor element, the wire, and the inner lead. A plurality of thin plating layers each having a two-layer structure in which a Ni-Co alloy layer and a Pd layer are sequentially stacked on the Ni strike layer. A semiconductor device characterized by the above-mentioned.