JPH04335558A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04335558A JPH04335558A JP3135483A JP13548391A JPH04335558A JP H04335558 A JPH04335558 A JP H04335558A JP 3135483 A JP3135483 A JP 3135483A JP 13548391 A JP13548391 A JP 13548391A JP H04335558 A JPH04335558 A JP H04335558A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- lead frame
- metal
- metal member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 68
- 239000010410 layer Substances 0.000 claims abstract description 87
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 238000007747 plating Methods 0.000 claims abstract description 26
- 239000011247 coating layer Substances 0.000 claims abstract description 21
- 150000002739 metals Chemical class 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 229910000531 Co alloy Inorganic materials 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 229910020810 Sn-Co Inorganic materials 0.000 abstract description 5
- 229910018757 Sn—Co Inorganic materials 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000003825 pressing Methods 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 229910017827 Cu—Fe Inorganic materials 0.000 abstract description 2
- 229910003271 Ni-Fe Inorganic materials 0.000 abstract description 2
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000005260 corrosion Methods 0.000 description 12
- 230000007797 corrosion Effects 0.000 description 12
- 238000011109 contamination Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000007789 sealing Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001556 precipitation Methods 0.000 description 4
- 239000010953 base metal Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- 230000007774 longterm Effects 0.000 description 3
- 229920003002 synthetic resin Polymers 0.000 description 3
- 239000000057 synthetic resin Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002386 leaching Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002345 surface coating layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置に係り、特に
金属の熱拡散、エレクトロ・マイグレーション及び電池
作用腐食の防止に有用な異種金属の多層被膜を備えたリ
ードフレームを使用して構成された半導体装置に関する
。[Industrial Application Field] The present invention relates to a semiconductor device, which is constructed using a lead frame provided with a multilayer coating of dissimilar metals, which is particularly useful for preventing metal thermal diffusion, electromigration, and battery corrosion. Related to semiconductor devices.
【従来の技術】近年、半導体デバイスにおいては、高集
積化、高性能化が進みこれに伴って半導体パッケージの
小型化または同一サイズの多ピン化が行われている。そ
のため図２にその一部断面を示すようなＱＦＰ（Ｑｕａ
ｄ Ｆｌａｔ Ｐａｃｋａｇｅ）タイプの半導体装
置１０では、例えば、アウターリードピッチ０．３ｍｍ
、ピン数は２００〜３００ピンが要求されている。従っ
て、アウターリード１１、インナーリード１２のリード
幅や間隔を狭くし、更にアウターリード１１、インナー
リード１２の表面被膜層の厚みを薄くして前記同一サイ
ズ内の多ピン化に対応すると共に電気作用腐食、エレク
トロ・マイグレーションを防ぐ必要があった。また、従
来のチップ化された半導体装置１０は、Ｃｕ−Ｆｅ系ま
たはＮｉ−Ｆｅ系合金等の金属条材をエッチングまたは
プレス加工で所要の形状に形成したリードフレームの金
属部材が用いられている。前記リードフレームは、半導
体素子１３を搭載する素子搭載部１４と、前記半導体素
子１３のパット部１５をワイヤ１６を介して接続して電
気導通回路を形成するインナーリード１２と、これを保
持する連結部で相互に連結され、前記インナーリード１
２に対応して外部接続端子を構成するアウターリード１
１とを備えている。前記リードフレームは、全面にＮｉ
等の下地めっき層１７を備えると共に、インナーリード
１２のワイヤボンディング部１８及び素子搭載部１４に
はＡｇ等の貴金属の部分めっき１９が形成されている。
従って、該半導体装置１０の製造にあっては、一般的に
このリードフレームの素子搭載部１４に半導体素子１３
をボンディングし、該半導体素子１３のパット部１５に
ワイヤ１６の一端をボンディングし、他端を前記インナ
ーリード１２先端のワイヤボンディング部１８に接続し
て電気回路を構成した後、それらを絶縁性樹脂２０で被
覆封止している。そして、該絶縁性樹脂２０の周辺に突
出したアウターリード１１を備えた図示しない連結部を
分離成形した後、該突出したアウターリード１１に半田
被覆層２１を形成して半導体装置を製造している。2. Description of the Related Art In recent years, semiconductor devices have become more highly integrated and have higher performance. This has led to the miniaturization of semiconductor packages or the increase in the number of pins of the same size. Therefore, a QFP (Qua
For example, in the semiconductor device 10 of the d Flat Package type, the outer lead pitch is 0.3 mm.
, the number of pins is required to be 200 to 300 pins. Therefore, by narrowing the lead width and spacing between the outer leads 11 and inner leads 12, and further reducing the thickness of the surface coating layer of the outer leads 11 and inner leads 12, it is possible to cope with the increase in the number of pins within the same size and to increase the electrical effect. It was necessary to prevent corrosion and electromigration. Further, the conventional chip-shaped semiconductor device 10 uses a metal member of a lead frame, which is formed by etching or pressing a metal strip such as a Cu-Fe alloy or a Ni-Fe alloy. . The lead frame includes an element mounting portion 14 on which the semiconductor element 13 is mounted, an inner lead 12 that connects the pad portion 15 of the semiconductor element 13 via a wire 16 to form an electrically conductive circuit, and a connection that holds the inner lead 12. The inner leads 1 are connected to each other at the inner leads 1
Outer lead 1 that constitutes an external connection terminal corresponding to 2.
1. The lead frame is entirely covered with Ni.
In addition, a partial plating 19 of noble metal such as Ag is formed on the wire bonding portion 18 and the element mounting portion 14 of the inner lead 12. Therefore, in manufacturing the semiconductor device 10, the semiconductor element 13 is generally mounted on the element mounting portion 14 of the lead frame.
After bonding one end of the wire 16 to the pad portion 15 of the semiconductor element 13 and connecting the other end to the wire bonding portion 18 at the tip of the inner lead 12 to form an electric circuit, they are bonded to an insulating resin. It is covered and sealed with 20. After separately molding a connecting portion (not shown) having outer leads 11 protruding around the insulating resin 20, a solder coating layer 21 is formed on the protruding outer leads 11 to manufacture a semiconductor device. .
【０００３】0003
【発明が解決しようとする課題】前記従来例に係る半導
体装置１０に用いたリードフレームのめっき被覆構成で
は、前述した多ピン化に対応してアウターリード１１や
インナーリード１２の幅や間隔が狭くなり、それに伴っ
て表面のめっき被覆層の厚みを薄くする必要がある。し
かしながら、被覆層を薄くするとめっき液やめっき条件
によって、前記めっき被覆層の腐食に対して大きな欠陥
となるピンホールが多数発生する欠点がある。更に、前
記ピンホールが前記めっき被覆層に存在すると前記ピン
ホールを通って素地金属層と最上層のめっき金属層との
間に電位差が生じ局部電池が形成され、この局部電池の
構成によって、素地金属層とめっき金属層との間で電池
作用が起こり素地金属層の金属が溶解して前記ピンホー
ルを通って析出酸化して最上層のめっき金属の表面を汚
染し、半田ぬれ性を低下させ、且つ、前記素地金属層を
腐食させる欠点があった。更に、金属部材内に加工段階
で残留応力が滞有すると、めっきの際に薬品で表面が侵
され、応力腐食割れを生じる欠点があった。また、前記
多ピン化に対応してアウターリード１１やインナーリー
ド１２のリード間の間隔が狭くなり、インナーリード１
２の先端に形成された部分メッキ層１９を形成するＡｇ
等が前記絶縁性樹脂２０からなる被覆封止部に析出して
エレクトロ・マイグレーションを引起しリードを短絡さ
せる欠点があった。そして、アウターリード１１のリー
ド間に半田のブリッジが形成される等の半導体装置の品
質及び信頼性を低下させる問題があった。従って、前記
した従来例に係る半導体装置１０においては、半導体装
置の品質、長期信頼性を低下させ、歩留りの低下による
コストが上昇するという問題点があった。本発明は、半
導体装置を用いたリードフレームの被覆層を薄くすると
共に局部電池作用腐食や表面汚染に対して大きな欠陥と
なるピンホールを減少させ、更にエレクトロ・マイグレ
ーションを防ぎ、しかも、半導体装置の必須条件である
電気伝導性、低接触性、ボンディング性、半田ぬれ性を
も満たし長期信頼性を維持できる高品質な半導体装置を
提供することを目的とする。[Problems to be Solved by the Invention] In the plating structure of the lead frame used in the conventional semiconductor device 10, the width and spacing of the outer leads 11 and inner leads 12 are narrow in response to the increase in the number of pins described above. Accordingly, it is necessary to reduce the thickness of the surface plating layer. However, when the coating layer is thinned, there is a drawback that a large number of pinholes are generated, which can be a major defect against corrosion of the plated coating layer, depending on the plating solution and the plating conditions. Furthermore, when the pinhole exists in the plating coating layer, a potential difference is generated between the base metal layer and the uppermost plating metal layer through the pinhole, forming a local battery. A battery action occurs between the metal layer and the plated metal layer, and the metal in the base metal layer dissolves and precipitates through the pinholes and oxidizes, contaminating the surface of the top layer of plated metal and reducing solder wettability. Moreover, there is a drawback that the base metal layer is corroded. Furthermore, if residual stress remains in the metal member during processing, the surface will be attacked by chemicals during plating, resulting in stress corrosion cracking. Additionally, in response to the increase in the number of pins, the intervals between the outer leads 11 and inner leads 12 have become narrower, and the inner leads 11 and 12 have become narrower.
Ag forming the partial plating layer 19 formed on the tip of 2
etc. are deposited on the coating sealing portion made of the insulating resin 20, causing electromigration and shorting the leads. Further, there are problems such as the formation of solder bridges between the leads of the outer leads 11, which deteriorates the quality and reliability of the semiconductor device. Therefore, the semiconductor device 10 according to the conventional example described above has the problem that the quality and long-term reliability of the semiconductor device are degraded, and the cost is increased due to a decrease in yield. The present invention reduces the thickness of the coating layer of a lead frame using a semiconductor device, reduces pinholes which can be a major defect against local battery corrosion and surface contamination, and prevents electromigration. The purpose of the present invention is to provide a high-quality semiconductor device that satisfies the essential conditions of electrical conductivity, low contact properties, bonding properties, and solderability, and can maintain long-term reliability.
【０００４】0004
【課題を解決するための手段】前記目的に沿う請求項第
１項記載の半導体装置は、所要の形状加工が行われた素
子搭載部、インナーリード及びアウターリードとを備え
表面に金属被覆層が形成された金属部材からなるリード
フレームと、前記素子搭載部に搭載された半導体素子と
、該半導体素子のパット部と前記インナーリード先端と
を連結して電気導通回路を形成するワイヤと、前記半導
体素子、前記ワイヤ及び前記インナーリードを含むリー
ドフレームの所定領域を被覆封止する電気絶縁性樹脂と
を有する半導体装置において、前記リードフレームの金
属部材は応力除去焼き鈍しがなされ、しかも該リードフ
レームの金属被覆層は異種金属の薄めっきを多層被覆し
て構成されている。そして、請求項第２項記載の半導体
装置は、請求項第１項記載の半導体装置において、前記
リードフレームを異種金属で多層被覆してなる金属被覆
層は、中間層にＳｎ−Ｃｏ合金層を有し、最上部がＰｄ
層で構成されている。請求項第３項記載の半導体装置は
、請求項第２項記載の半導体装置において、Ｓｎ−Ｃｏ
合金層とＰｄ層とを交互に多層被覆して構成されている
。また、請求項第４項記載の半導体装置は、請求項第１
項記載の半導体装置において、前記リードフレームを異
種金属で多層被覆してなる金属被覆層は、中間層にＮｉ
−Ｃｏ合金層を有し、最上部がＰｄ層で構成されている
。請求項第５項記載の半導体装置は、請求項第４項記載
の半導体装置においては、Ｎｉ−Ｃｏ合金層とＰｄ層を
交互に多層被覆して構成されている。更に、請求項第６
項記載の半導体装置は、請求項第１項〜第５項記載の半
導体装置において、金属部材の表面にＮｉストライク層
を備えて構成されている。[Means for Solving the Problems] A semiconductor device according to claim 1, which meets the above object, comprises an element mounting portion, inner leads, and outer leads which are processed into a required shape, and a metal coating layer is provided on the surface. A lead frame made of a formed metal member, a semiconductor element mounted on the element mounting part, a wire connecting the pad part of the semiconductor element and the tip of the inner lead to form an electrically conductive circuit, and the semiconductor element. In a semiconductor device having an electrically insulating resin that covers and seals a predetermined region of a lead frame including an element, the wires, and the inner leads, the metal member of the lead frame is stress-relieving annealed, and the metal member of the lead frame is The coating layer is formed by coating multiple layers of thin plating of different metals. The semiconductor device according to claim 2 is the semiconductor device according to claim 1, in which the metal coating layer formed by coating the lead frame with multiple layers of different metals includes an Sn-Co alloy layer as an intermediate layer. and the top is Pd
It is composed of layers. The semiconductor device according to claim 3 is the semiconductor device according to claim 2, wherein Sn-Co
It is constructed by alternately covering multiple layers of alloy layers and Pd layers. Further, the semiconductor device according to claim 4 is provided in claim 1.
In the semiconductor device described in 1., the metal coating layer formed by coating the lead frame in multiple layers with different metals includes Ni in the intermediate layer.
-Co alloy layer, and the top layer is composed of Pd layer. The semiconductor device according to claim 5 is the semiconductor device according to claim 4, which is constructed by alternately covering Ni--Co alloy layers and Pd layers in multiple layers. Furthermore, claim 6
The semiconductor device according to the first aspect is the semiconductor device according to the first to fifth aspects of the present invention, and is configured by including a Ni strike layer on the surface of the metal member.
【０００５】[0005]
【作用】請求項第１項〜第６項記載の半導体装置におい
ては、リードフレームを構成する金属部材の表面に薄め
っき層が多層被覆されているので、該金属被覆層を貫通
して前記金属部材に達するピンホールを減少でき、これ
によって前記金属部材と最上部のめっき金属層との間で
局部電池が発生せず、金属被覆層の表面を汚すことが極
めて減少する。特に、請求項第２項〜第５項記載の半導
体装置においては、最上層がＰｄ層となっているので、
酸化被膜が形成されず、半田ぬれ性が向上し、更にエレ
クトロ・マイグレーションによるリード間の短絡が防止
される。そして、最上層と金属部材間には、最上層の金
属と該金属部材との間の電位差を緩和するＳｎ−Ｃｏめ
っき層またはＮｉ−Ｃｏめっき層からなる中間めっき層
を備えているので、金属部材及び各めっき層間の電池作
用腐食及び最上層の金属の析出酸化を防ぐ作用を有する
。また、請求項第６項記載の半導体装置においては、金
属部材の表面にＮｉストライク層を備えているので、金
属部材に含まれるＣｕ等の金属被覆層への熱拡散を防止
でき、更に該Ｃｕ等の侵出によるめっき液の汚染を防止
できる。更に、金属部材内の残留応力が除去されている
ので、応力腐食割れを防止する作用がある。[Function] In the semiconductor device according to any one of claims 1 to 6, the surface of the metal member constituting the lead frame is coated with multiple thin plating layers. Pinholes reaching the component can be reduced so that no local batteries occur between the metal component and the top plated metal layer, and contamination of the surface of the metallization layer is greatly reduced. In particular, in the semiconductor device according to claims 2 to 5, since the uppermost layer is a Pd layer,
No oxide film is formed, solder wettability is improved, and short circuits between leads due to electromigration are prevented. Between the uppermost layer and the metal member, an intermediate plating layer consisting of a Sn-Co plating layer or a Ni-Co plating layer is provided to alleviate the potential difference between the uppermost layer metal and the metal member. It has the effect of preventing battery corrosion between the members and each plating layer and precipitation oxidation of the top layer metal. Further, in the semiconductor device according to claim 6, since the Ni strike layer is provided on the surface of the metal member, it is possible to prevent heat diffusion of Cu, etc. contained in the metal member to the metal coating layer, and furthermore, the Ni strike layer is provided on the surface of the metal member. It is possible to prevent contamination of the plating solution due to the leaching of etc. Furthermore, since residual stress within the metal member is removed, stress corrosion cracking can be prevented.
【０００６】[0006]
【実施例】続いて、添付した図面を参照しつつ、本発明
を具体化した実施例につき説明し、本発明の理解に供す
る。ここに、図１には本発明の一実施例に係る半導体装
置２３の部分断面図を示すが、本発明の一実施例に係る
半導体装置２３は、素子搭載部２４、インナーリード２
５及びアウターリード２６を備えるリードフレームと、
前記素子搭載部２４にボンディングされた半導体素子２
７と、該半導体素子２７のパット部２８に一端が連結さ
れ他端が前記インナーリード２５に連結して電気回路を
構成するワイヤ２９と、これらを被覆封止する絶縁性合
成樹脂３０とを有して構成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments embodying the present invention will be described with reference to the attached drawings to provide an understanding of the present invention. Here, FIG. 1 shows a partial cross-sectional view of a semiconductor device 23 according to an embodiment of the present invention.
5 and an outer lead 26;
Semiconductor element 2 bonded to the element mounting part 24
7, a wire 29 having one end connected to the pad portion 28 of the semiconductor element 27 and the other end connected to the inner lead 25 to form an electric circuit, and an insulating synthetic resin 30 covering and sealing these. It is configured as follows.
【０００７】前記リードフレームは、Ｃｕ−Ｆｅ系（ま
たはＮｉ−Ｆｅ系）の金属部材からなって、プレス加工
またはエッチング加工によって素子搭載部２４、インナ
ーリード２５、アウターリード２６が形成されている。
なお、プレス加工を施した場合には残留応力を除去する
ため、応力除去焼き鈍し処理が行われている。そして、
該リードフレームは、アウターリード２６の外側に形成
される図示しない連結部と共にめっき処理による金属被
覆層３１が形成されているが、該金属被覆層３１は、そ
れぞれ薄めっき層からなる下地層を形成するＮｉストラ
イク層３２と、中間層のＳｎ−Ｃｏ層３３と、最上層の
Ｐｄ層３４によって構成されている。ここで、前記Ｎｉ
ストライク層３２は、金属部材に含有するＣｕ等の熱拡
散及びめっき液汚染防止の為に設けられる。そして、中
間部のＳｎ−Ｃｏ層３３は、下地層のピンホールを覆っ
て確率的に金属部材と最上層のＰｄ層３４とによる局部
電池の発生を防止する。そして、仮に上下のピンホール
が連続して局部電池が前記金属部材と最上層との間に局
部電池が形成されても、中間層を設けることによってそ
れらの電位差を緩和し、金属部材層の電池作用腐食及び
最上層に金属の析出酸化を防止するようにすると共に、
エレクトロ・マイグレーションによるリード間の短絡を
無くし半導体装置の信頼性を向上している。The lead frame is made of a Cu--Fe (or Ni--Fe) metal member, and has an element mounting portion 24, inner leads 25, and outer leads 26 formed by pressing or etching. Note that when press working is performed, a stress-relieving annealing process is performed to remove residual stress. and,
In the lead frame, a metal coating layer 31 is formed by plating along with a connecting portion (not shown) formed on the outside of the outer lead 26, and each of the metal coating layers 31 forms a base layer made of a thin plating layer. It is composed of a Ni strike layer 32, an intermediate Sn--Co layer 33, and an uppermost Pd layer 34. Here, the Ni
The strike layer 32 is provided for thermal diffusion of Cu contained in the metal member and for prevention of plating solution contamination. The intermediate Sn--Co layer 33 covers the pinholes in the underlayer and stochastically prevents the occurrence of local batteries due to the metal member and the uppermost Pd layer 34. Even if the upper and lower pinholes are continuous and a local battery is formed between the metal member and the top layer, providing an intermediate layer will alleviate the potential difference between them, and the battery in the metal member layer To prevent corrosion and oxidation of metal precipitation in the top layer,
This improves the reliability of semiconductor devices by eliminating short circuits between leads due to electromigration.
【０００８】このように、金属被覆層が形成されたリー
ドフレームの素子搭載部２４に半導体素子２７をボンデ
ィングした後、該半導体素子２７のパット部２８とイン
ナーリード２５の先端部３５とをワイヤ２９によって連
結して電気回路を形成するようにしている。この後、前
記素子搭載部２４、半導体素子２７、インナーリード２
５及びアウターリード２６の先部を、絶縁性合成樹脂３
０によって被覆封止し、該被覆封止領域から突出したア
ウターリードの先端に一体として接合されている図示し
ない連結部を分離して、半導体装置２３が完成している
。After the semiconductor element 27 is bonded to the element mounting part 24 of the lead frame on which the metal coating layer is formed in this way, the pad part 28 of the semiconductor element 27 and the tip part 35 of the inner lead 25 are connected with the wire 29. are connected to form an electric circuit. After that, the element mounting section 24, the semiconductor element 27, the inner lead 2
5 and the tip of the outer lead 26 with an insulating synthetic resin 3.
The semiconductor device 23 is completed by covering and sealing the semiconductor device 23 by sealing the semiconductor device 23 by separating the connecting portion (not shown) which is integrally joined to the tip of the outer lead protruding from the covering and sealing region.
【０００９】なお、この実施例においては、中間層にＳ
ｎ−Ｃｏ層３３を一層配置したのみであるが、更にＳｎ
−Ｃｏ層とＰｄ層とを交互に形成して多重層とすること
も可能であり、これによって確率的にピンホールの貫通
がなくなるので、更に耐腐食性が向上し、最上層のＰｄ
層が汚染されないので半田ぬれ性が向上する。また、前
記Ｓｎ−Ｃｏ層の代わりにＮｉ−Ｃｏ層を形成すること
も可能であり、これによっても同様の作用効果を期待で
きる。[0009] In this embodiment, the intermediate layer has S
Although only one n-Co layer 33 is disposed, Sn
- It is also possible to form a multilayer by alternately forming Co layers and Pd layers, which stochastically eliminates the penetration of pinholes, further improving corrosion resistance.
Since the layer is not contaminated, solder wettability is improved. Furthermore, it is also possible to form a Ni--Co layer instead of the Sn--Co layer, and the same effects can be expected with this as well.
【００１０】0010
【発明の効果】請求項第１項〜第６項記載の半導体装置
は、以上の説明からも明らかなように、薄めっきが多層
被覆されたリードフレームが使用されているので、金属
部材の被覆層を貫通するピンホールが確率的に減少する
。従って、ピンホールに起因する前記金属部材と最上層
との局部電池作用による腐食を防止できると共に、金属
部材の最上層への析出酸化による汚染を防止できる。
また、金属部材に応力除去焼き鈍しを施しているので、
めっき被覆層の形成に際して応力腐食割れを防ぐ効果が
ある。従って、半導体装置の必須条件である電気伝導性
、低接触性、ボンディング性、半田ぬれ性をも満たし長
期信頼性を維持できる高品質な半導体装置を提供するこ
とができる。特に、請求項第２項〜第５項記載の半導体
装置においては、最上層にＰｄ層が形成されているので
、酸化被膜が形成されず半田ぬれ性が向上し、更にエレ
クトロ・マイグレーションによるリード間の短絡を防止
することができる。そして、中間層にＳｎ−Ｃｏ層また
はＮｉ−Ｃｏ層が設けられているので、電池作用腐食を
緩和し、金属の析出酸化を防ぐ効果がある。そして、請
求項第６項記載の半導体装置においては、最下層にＮｉ
ストライク層を備えているので、金属部材に含まれるＣ
ｕ等の熱拡散を防止でき、更にはめっき処理工程におい
て、めっき液の汚染を防止できる。[Effects of the Invention] As is clear from the above description, the semiconductor device according to claims 1 to 6 uses a lead frame coated with multiple layers of thin plating. The probability of pinholes penetrating the layer is reduced. Therefore, it is possible to prevent corrosion due to local battery action between the metal member and the uppermost layer due to pinholes, and it is also possible to prevent contamination due to precipitation oxidation on the uppermost layer of the metal member. In addition, since the metal parts are subjected to stress relief annealing,
It has the effect of preventing stress corrosion cracking when forming a plating coating layer. Therefore, it is possible to provide a high-quality semiconductor device that satisfies the essential conditions of a semiconductor device, such as electrical conductivity, low contact properties, bonding properties, and solderability, and can maintain long-term reliability. In particular, in the semiconductor device according to claims 2 to 5, since the Pd layer is formed as the uppermost layer, no oxide film is formed and solder wettability is improved. can prevent short circuits. Further, since the Sn--Co layer or the Ni--Co layer is provided in the intermediate layer, it has the effect of alleviating battery corrosion and preventing metal precipitation and oxidation. In the semiconductor device according to claim 6, the bottom layer includes Ni.
Since it is equipped with a strike layer, C contained in the metal member is
It is possible to prevent thermal diffusion of u, etc., and furthermore, it is possible to prevent contamination of the plating solution in the plating process.
【図１】本発明の一実施例に係る半導体装置の部分断面
図である。FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】従来例に係る半導体装置の部分断面図である。FIG. 2 is a partial cross-sectional view of a conventional semiconductor device.
２３ 半導体装置 ２４ 素子搭載部 ２５ インナーリード ２６ アウターリード ２７ 半導体素子 ２８ パット部 ２９ ワイヤ ３０ 絶縁性合成樹脂 ３１ 金属被覆層 ３２ Ｎｉストライク層 ３３ Ｓｎ−Ｃｏ層 ３４ Ｐｄ層 ３５ 先端部 23 Semiconductor device 24 Element mounting part 25 Inner lead 26 Outer lead 27 Semiconductor element 28 Pat part 29 Wire 30 Insulating synthetic resin 31 Metal coating layer 32 Ni strike layer 33 Sn-Co layer 34 Pd layer 35 Tip
Claims (6)
、インナーリード及びアウターリードとを備え表面に金
属被覆層が形成された金属部材からなるリードフレーム
と、前記素子搭載部に搭載された半導体素子と、該半導
体素子のパット部と前記インナーリード先端とを連結し
て電気導通回路を形成するワイヤと、前記半導体素子、
前記ワイヤ及び前記インナーリードを含むリードフレー
ムの所定領域を被覆封止する電気絶縁性樹脂とを有する
半導体装置において、前記リードフレームの金属部材は
応力除去焼き鈍しがなされ、しかも該リードフレームの
金属被覆層は、異種金属の薄めっきを多層被覆してなる
ことを特徴とする半導体装置。1. A lead frame made of a metal member having a metal coating layer formed on its surface, comprising an element mounting part, an inner lead, and an outer lead that have been processed into a required shape, and a lead frame that is mounted on the element mounting part. a semiconductor element, a wire connecting the pad portion of the semiconductor element and the tip of the inner lead to form an electrically conductive circuit, the semiconductor element;
In a semiconductor device having an electrically insulating resin that coats and seals a predetermined region of a lead frame including the wire and the inner lead, the metal member of the lead frame is stress-relieving annealed, and the metal coating layer of the lead frame is is a semiconductor device characterized by being coated with multiple layers of thin plating of dissimilar metals.
被覆してなる金属被覆層は、中間層にＳｎ−Ｃｏ合金層
を有し、最上部がＰｄ層で構成される請求項第１項記載
の半導体装置。2. The metal coating layer formed by coating the lead frame in multiple layers with dissimilar metals has an Sn--Co alloy layer as an intermediate layer, and a Pd layer on the top layer. Semiconductor equipment.
多層被覆してなる請求項第２項記載の半導体装置。3. The semiconductor device according to claim 2, wherein the semiconductor device is formed by alternately covering Sn--Co alloy layers and Pd layers in multiple layers.
被覆してなる金属被覆層は、中間層にＮｉ−Ｃｏ合金層
を有し、最上部がＰｄ層で構成される請求項第１項記載
の半導体装置。4. The metal coating layer formed by coating the lead frame in multiple layers with dissimilar metals has a Ni--Co alloy layer as an intermediate layer, and a Pd layer on the top layer. Semiconductor equipment.
層被覆してなる請求項第４項記載の半導体装置。5. The semiconductor device according to claim 4, wherein the semiconductor device is formed by alternately covering Ni--Co alloy layers and Pd layers in multiple layers.
備えた請求項第１項〜第５項記載の半導体装置。6. The semiconductor device according to claim 1, further comprising a Ni strike layer on the surface of the metal member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3135483A JP2654872B2 (en) | 1991-05-10 | 1991-05-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3135483A JP2654872B2 (en) | 1991-05-10 | 1991-05-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04335558A true JPH04335558A (en) | 1992-11-24 |
| JP2654872B2 JP2654872B2 (en) | 1997-09-17 |
Family
ID=15152778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3135483A Expired - Lifetime JP2654872B2 (en) | 1991-05-10 | 1991-05-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2654872B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0621633A2 (en) * | 1993-04-10 | 1994-10-26 | W.C. Heraeus GmbH | Leadframe for integrated circuits |
| WO1996034412A1 (en) * | 1995-04-27 | 1996-10-31 | National Semiconductor Corporation | Protective coating combination for lead frames |
-
1991
- 1991-05-10 JP JP3135483A patent/JP2654872B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0621633A2 (en) * | 1993-04-10 | 1994-10-26 | W.C. Heraeus GmbH | Leadframe for integrated circuits |
| EP0621633A3 (en) * | 1993-04-10 | 1995-01-11 | Heraeus Gmbh W C | Leadframe for integrated circuits. |
| US5486721A (en) * | 1993-04-10 | 1996-01-23 | W.C. Heraeus Gmbh | Lead frame for integrated circuits |
| JPH08111484A (en) * | 1993-04-10 | 1996-04-30 | W C Heraeus Gmbh | Lead frame |
| WO1996034412A1 (en) * | 1995-04-27 | 1996-10-31 | National Semiconductor Corporation | Protective coating combination for lead frames |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2654872B2 (en) | 1997-09-17 |
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