JPS61140160A - Lead frame for semiconductor - Google Patents

Lead frame for semiconductor

Info

Publication number
JPS61140160A
JPS61140160A JP59262293A JP26229384A JPS61140160A JP S61140160 A JPS61140160 A JP S61140160A JP 59262293 A JP59262293 A JP 59262293A JP 26229384 A JP26229384 A JP 26229384A JP S61140160 A JPS61140160 A JP S61140160A
Authority
JP
Japan
Prior art keywords
alloy
lead frame
semiconductor element
resin
fixing part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59262293A
Other languages
Japanese (ja)
Inventor
Osamu Yoshioka
修 吉岡
Ryozo Yamagishi
山岸　良三
Masaru Watanabe
勝 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP59262293A priority Critical patent/JPS61140160A/en
Publication of JPS61140160A publication Critical patent/JPS61140160A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To contrive the reduction of cost and the improvement of reliability by a method wherein an Ni alloy layer having one or more elements of B, P, Fe, and Co is provided on a metallic substrate, and the semiconductor element fixing part and inner lead terminals are provided with Pd or Pd-Ni alloy platings. CONSTITUTION:The substrate punched out of a copper strip is provided with an Ni-Fe alloy plated layer 13 as the base layer over the whole by electroplating. Further, Pd plated layers 14 are partly provided thereon at the mechanical part including the semiconductor element fixing part and inner lead terminals 8. An Si pellet 3 is brazed on the Pd plated layer 14 with an Ag paste solder 7 at the semiconductor element fixing part, and the Si pellet is wired to the inner lead terminals of the lead frame with Au fine wires 5. Thereafter, an IC package is constructed by sealing the whole with a resin 21.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用リードフレームに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体用に使用されるリードフレーム材として用いられ
る金属基体は鉄系合金としてコバール、４２合金、ステ
ンレスなど、銅または銅合金あるいは鉄材の上に銅を被
覆した材料等が主として使用されている。そして半導体
素子の接合ならびに金属細線のボンディングを容易に行
うようにするため、半導体素子固定部（タブ部）ならび
に金属細線により素子とリードの配線をする内部リード
端部（ポスト部）にＡｕあるいはＡｇの部分貴金属めっ
きを施している。即ち鉄系合金、例えば４２合金をリー
ドフレーム材に使用する場合にはＡｕあるいはＡｇめっ
きが行なわれ、銅合金をリードフレーム材として使用す
る場合にはＡｇめっきが行なわれる。Metal substrates used as lead frame materials for semiconductors are mainly made of iron-based alloys such as Kovar, 42 alloy, stainless steel, copper or copper alloys, or materials in which iron is coated with copper. In order to facilitate bonding of semiconductor elements and bonding of thin metal wires, Au or Ag is applied to the semiconductor element fixing part (tab part) and the internal lead end (post part) where the element and lead are wired using thin metal wires. Partially plated with precious metals. That is, when an iron-based alloy such as 42 alloy is used as the lead frame material, Au or Ag plating is performed, and when a copper alloy is used as the lead frame material, Ag plating is performed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、従来のリードフレームでは次の様な欠点
があった。即ち、部分Ａｕめっきしたリードフレームの
場合、貴金属であるＡｕを部分化したことにより、Ａｕ
の使用量は大巾に減少したが、それでも材料費の半分以
上をＡｕが占めている状況である。一方Ａｇめっきした
リードフレームではＡｇを部分化したことによシ材料費
にしめる割合は少なくなったが、Ａｇめっきにはマイグ
レーノー１ンの欠点がち９、鵬信頼性を要求される分野
には使われていないのが現状である。However, conventional lead frames have the following drawbacks. In other words, in the case of a lead frame that is partially plated with Au, by partially plating the precious metal Au, the Au
Although the amount of Au used has decreased significantly, Au still accounts for more than half of the material cost. On the other hand, with Ag-plated lead frames, the proportion of material costs has been reduced by dividing the Ag into parts, but Ag plating has the disadvantages of migraine no. 19. The current situation is that it is not used.

また半導体の封止方法には信頼性の高いセラミッり封止
があるがコスト高となる点から近年はシリコーン樹脂、
エポキシ樹脂、７リコー／ポリイミド樹脂等の樹脂封止
が主流となシつつある。しかし樹脂封止の場合、樹脂と
４２合金あるいは銅合金との密着が不充分で隙間から湿
気が浸入して半導体素子を侵す欠点があることから、樹
脂封止性を同上させることが大きな問題となっている。Ceramic encapsulation is a highly reliable method for encapsulating semiconductors, but due to its high cost, in recent years silicone resin,
Resin sealing such as epoxy resin and 7 Ricoh/polyimide resin is becoming mainstream. However, in the case of resin sealing, the adhesion between the resin and the 42 alloy or copper alloy is insufficient, and moisture can enter through the gaps and attack the semiconductor element, so improving the resin sealability is a big problem. It has become.

特に銅合金をリードフレーム材に使用する場合、樹脂と
の密着性が悪いため、４２合金と比較して材料が安価で
あるにもかかわらず、信頼性が低いということから、使
用される半導体装置は限定されている。In particular, when copper alloy is used as a lead frame material, it has poor adhesion with resin, so even though the material is cheaper than 42 alloy, it is less reliable, so it is used in semiconductor devices. is limited.

本発明の目的は前記した従来技術の欠点を解消し、半導
体装置の信頼性を向上させると同時に安価なリードフレ
ーム材を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above, improve the reliability of a semiconductor device, and at the same time provide an inexpensive lead frame material.

〔問題を解決するための手段〕[Means to solve the problem]

すなわち、本発明の要旨は金属基体の表面にＢ。 That is, the gist of the present invention is to apply B on the surface of a metal substrate.

Ｐ、Ｆｅ、Ｃｏのうち１つ以上の元素を含有するＮｉ合
雀層を設けた後、更にその上に、少なくとも半導体素子
を固定する領域および金属細線をボンディングする領域
にＰｄあるいはＮｉを含有するＰｄ合金めっき層を設け
たことにある。After providing the Ni composite layer containing one or more elements among P, Fe, and Co, Pd or Ni is further added thereon at least in the region for fixing the semiconductor element and the region for bonding the thin metal wire. This is because a Pd alloy plating layer is provided.

本発明による半導体用リードフレームの構成を従来のリ
ードフレームとの対比で図によって説明する。第２図は
ＩＣ用リードフレームの一例を示す平面図、第３図は従
来法の要部断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a semiconductor lead frame according to the present invention will be explained with reference to the drawings in comparison with a conventional lead frame. FIG. 2 is a plan view showing an example of an IC lead frame, and FIG. 3 is a sectional view of a main part of a conventional method.

第２図において１は金属基体、いわゆるリードフレーム
材で、鉄系合金としてコバール、４２合金、ステンＶス
など、銅または銅合金あるいは鉄材の上に銅を被覆した
材料等が主として使用されている。４は半導体素子固定
部（タブ部）でこの上に半導体素子であるＳｉベレット
を固定する領域であり、８は内部リード端子部で半導体
素子とリードの配線である金属細線５をボンディングす
る領域である。１０は外部リード部でるる。In Fig. 2, 1 is a metal base, a so-called lead frame material, which is mainly made of iron-based alloys such as Kovar, 42 alloy, stainless V steel, copper or copper alloys, or materials such as copper coated on iron materials. . Reference numeral 4 denotes a semiconductor element fixing part (tab part), which is an area on which a Si pellet, which is a semiconductor element, is fixed; and 8, an internal lead terminal part, which is an area to which a fine metal wire 5, which is a wiring between the semiconductor element and the lead, is bonded. be. 10 is an external lead part.

第３図において、４２合金からなる基体９の半導体素子
固定部４と内部リード端子部８上に部分的にＡｕめっき
層２を設けている。この様なリードフレームを用いてＩ
Ｃパッケージを作るには、その半導体素子固定部４に、
例えばＡｕ−８ｉ共晶うう材６を介してＳ１ペレツト３
を配設（ダイポンディング）シ、このＳｉベレット３と
リードフレームの内部リード端子部８のＡｕめつき層２
とをＡｕ金属細線５で接続配線（ワイヤボンディング）
シ、これをモールド樹脂２１で封止する。In FIG. 3, an Au plating layer 2 is partially provided on the semiconductor element fixing part 4 and the internal lead terminal part 8 of the base body 9 made of 42 alloy. Using this kind of lead frame,
To make a C package, the semiconductor element fixing part 4 is
For example, the S1 pellet 3 is passed through the Au-8i eutectic filling material 6.
(die bonding), this Si pellet 3 and the Au plating layer 2 of the internal lead terminal part 8 of the lead frame.
Connect wiring with Au metal thin wire 5 (wire bonding)
This is then sealed with mold resin 21.

第４図は従来のリードフレームの他の例を示す要部断面
図であって、銅合金リードフレーム１１上の半導体素子
固定部４、内部リード端子部８上に部分的にＡｇめつき
層１２を設けている。この場合Ａｇペーストろう材７を
介してＳｉベレット３を配設する。他は前記と同様にＩ
Ｃパッケージを構成する。このような従来技術において
、前記の如き、材料費が高いということと、樹脂封止の
場合、樹脂と４２合金あるいは銅合金との密着が不充分
で隙間から湿気が浸入して半導体素子を侵す等の欠点が
あった。FIG. 4 is a cross-sectional view of main parts showing another example of a conventional lead frame, in which an Ag plating layer 12 is partially formed on a semiconductor element fixing part 4 on a copper alloy lead frame 11 and an internal lead terminal part 8. has been established. In this case, the Si pellet 3 is placed through the Ag paste brazing material 7. Others are I as above
Configure the C package. In such conventional technology, as mentioned above, the material cost is high, and in the case of resin sealing, the adhesion between the resin and the 42 alloy or copper alloy is insufficient, causing moisture to enter through the gap and attack the semiconductor element. There were drawbacks such as.

これらの欠点を解決するための本発明の一実施例を第１
図に示す。A first embodiment of the present invention to solve these drawbacks is described below.
As shown in the figure.

第１図において、銅又は銅合金あるいは４２合金又は鉄
−クロムなどの鉄系合金からなる基体１１（１６）上に
耐酸化性が良好でかつ樹脂との密着性の良好なり　、Ｐ
　＊　Ｆ　ｅ　ｐ　Ｃｏのうち一つ以上の元素を含有す
る。Ｎｉ合金層１３を下地層として設は更にその上に少
なくとも半導体素子を固定する領域である半導体素子固
定部４と金属側ｉＨ５をボンディングする領域すなわち
、内部リード端子部８、上に部分的に、ＰｄあるいはＰ
ｄ−Ｎｉ合金めっき層１４１！：設けることにより低コ
スト化のみならず樹脂封止性を向上させることが出来た
のである。In FIG. 1, a substrate 11 (16) made of copper or a copper alloy, a 42 alloy, or an iron-based alloy such as iron-chromium is coated with a material having good oxidation resistance and good adhesion to the resin.
* Contains one or more elements of F e p Co. The Ni alloy layer 13 is provided as a base layer, and at least a region on which the semiconductor element fixing part 4, which is the region for fixing the semiconductor element, and the metal side iH 5 are bonded, that is, the internal lead terminal part 8, is partially covered. Pd or P
d-Ni alloy plating layer 141! By providing this, it was possible to not only reduce costs but also improve resin sealability.

〔作　用〕 本発明において、金属基休出にＢ　、　Ｐ　、　Ｆｅ、
Ｃ。[Function] In the present invention, B, P, Fe,
C.

のうち一つ以上の元素を肩するＮｉ合金層を設けたこと
が金属基体の耐酸化性を良好にしかつ樹脂との密着性向
上させ、従来の湿気の浸入を解決し、従来半導体素子固
定部と内部リード端子部にＡｕめっき層を設けていたの
が、ＰｄあるいはＰｄ−Ｎｉ合金めっき層に代へること
により低コストが可能になったのである。The provision of a Ni alloy layer that supports one or more of these elements improves the oxidation resistance of the metal substrate and improves its adhesion to the resin, solving the conventional problem of moisture intrusion and improving the conventional semiconductor element fixing part. By replacing the Au plating layer provided on the internal lead terminal portion with a Pd or Pd-Ni alloy plating layer, it became possible to reduce costs.

〔実泥例〕[Actual mud example]

厚さ０．２５４ＥＩの銅条を打抜いた基体上に電気めっ
き法によｐＮｉ−Ｆｅ合金めつき層を下地層として基体
全体に０．２ｍ設ける・さらにその上に半導体素子固定
部及び内部リード端子部を含む機磯部上に電気めっき法
によ、９Ｐｄめつき層を１μの厚で部分的に設けた（基
体としてＦｅ−Ｃｒ合金を用いた場合も同様にて作成す
る）、そして半導体素子固定部上にＳ１ベレツトをＡｇ
ペーストろう材を用いてＰｄめつき層上にろう接し、Ｓ
ｉベレットとリードフレームの内部リード端子部と金Ａ
ｕｉ［により配線する。その後全体を樹脂で封止してＩ
Ｃパッケージを構成する。A pNi-Fe alloy plating layer of 0.2 m is applied as a base layer over the entire base by electroplating on a base formed by punching out a copper strip with a thickness of 0.254EI.Furthermore, semiconductor element fixing parts and internal leads are formed on the base. A 9Pd plating layer with a thickness of 1 μm was partially provided on the surface of the machine including the terminal portion by electroplating (the same method is used when Fe-Cr alloy is used as the base material), and the semiconductor element is Ag the S1 beret on the fixed part.
Using a paste brazing material, solder the Pd plating layer and
i Bellet, internal lead terminal part of lead frame and gold A
Wire using ui[. After that, the whole thing is sealed with resin and I
Configure the C package.

ここで上記のように作成した本発明リードフレームと従
来列リードフレームについて、それぞれ大気中４００℃
×２分の加熱劣化を行ない、外部リードに形成させた酸
化膜の密着性を粘着テープビーリング法によ）調べた。Here, the lead frame of the present invention and the conventional row lead frame produced as described above were heated at 400°C in the atmosphere.
Heat deterioration was performed for 2 minutes, and the adhesion of the oxide film formed on the external lead was examined (using the adhesive tape beading method).

判定は○：剥離なしＸ：剥離あり。Judgment: ○: No peeling. X: Peeling.

また大気中４００ＣＸＺ分加熱劣化後それぞれのリード
フレームをモールド樹脂により封止した後、樹脂封止性
を３０気圧の水中に室温で３０時間放置して、水の浸入
距離によシ判定した。Further, each lead frame was sealed with a mold resin after being heated and degraded in the atmosphere for 400 CXZ minutes, and then resin sealability was evaluated by leaving it in water at 30 atm at room temperature for 30 hours, and determining the distance of water penetration.

○：水浸人がリード長の１７３未満 Δ：水浸人がリード長の１７３〜２／３×：水挺入がリ
ード長の２７３を越える。○: Water immersion is less than 173 of the lead length Δ: Water immersion is 173 to 2/3 of the lead length ×: Water penetration exceeds 273 of the lead length.

同、各リードフレームのコストはリードフレーム素材と
めつき代にｇ判断した０＠フレ一ムＡｇスポットと比較
して ○：はぼ同様、Δ：若干高価、Ｘ：数倍以上高価この辰
から判るＬうに、本発明のリード７し／−ムは樹脂と密
着性を改善しプラスチックパッケージの欠点である樹脂
封止性を向上させると同時に、Ａｇめっきに比較してマ
イグレーシヨンの不安もなく、コストの面からも有利で
あることが認められる。Similarly, the cost of each lead frame is determined based on the lead frame material and mating cost compared to 0@Frame Ag Spot. In addition, the lead 7/-m of the present invention improves adhesion with resin and improves resin sealability, which is a disadvantage of plastic packages, and at the same time, there is no fear of migration compared to Ag plating, and the cost is lower. It is recognized that this is advantageous from the viewpoint of

本発明によると、金属基体上にＢ　、　Ｐ　、　Ｆｅ、
Ｃ。According to the present invention, B, P, Fe,
C.

のうち一つ以上の元素を含有するＮｉ合金層を設ける目
的は実施例に示した如く樹脂との密着性を付与するため
に設けるものであって、金属基体とかかる合金めっき層
との密着性、あるいは耐蝕性向上のため、Ｎｉめつきあ
るいはＣｕ又は銅合金をめっきした金属基体を使用する
場合も本発明と同様な効果が得られる。The purpose of providing the Ni alloy layer containing one or more of the following elements is to provide adhesion to the resin as shown in the examples, and to improve the adhesion between the metal substrate and the alloy plating layer. Alternatively, the same effect as the present invention can be obtained when using a metal substrate plated with Ni or plated with Cu or a copper alloy in order to improve corrosion resistance.

〔発明の効果〕 本発明の効果は、高信頼性が要求されるプラスチック封
止の半導体装置には、４２合金のリードフレーム上に部
分Ａｕめっきした高価なものが使用されていたがＰｄを
使用することにより低コスト化を図ると同時にＡｇめつ
きと比較してマイグレーシヨンの不安がなくなった。[Effects of the Invention] The effects of the present invention are such that, in plastic-sealed semiconductor devices that require high reliability, an expensive one with partial Au plating on a 42 alloy lead frame was used, but Pd is used instead. By doing so, we are able to reduce costs and at the same time eliminate concerns about migration compared to Ag plating.

一方モールド樹脂を接する部分をＢ、Ｐ、Ｆｅ。On the other hand, the part that contacts the mold resin is made of B, P, and Fe.

ＣＯのうち一つ以上の元素を含有するＮｉ合金めっきし
たことによシ、樹脂との密着性が向上し樹脂封止性の面
から信頼性も向上した。この結果高価な４２合金でない
安価な銅合金あるいはＦｅ−ＣｒなどのＦｅ合金を適用
することも可能となり、低コスト化を図ることができる
。以上のように本発明は半導体装置の低コスト化および
信頼性向上を図ることが出来る新規な構成の半導体用リ
ードフレームを提供したものであり、その工業的価値は
きわめて大きい。By plating the Ni alloy containing one or more elements of CO, the adhesion to the resin was improved, and the reliability was also improved in terms of resin sealability. As a result, it is possible to use an inexpensive copper alloy or an Fe alloy such as Fe-Cr instead of the expensive 42 alloy, thereby reducing costs. As described above, the present invention provides a semiconductor lead frame with a novel configuration that can reduce the cost and improve the reliability of semiconductor devices, and its industrial value is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例に係るリードフレームの要部
断面図である◇第２図はＩＣ用リードフレームの一例を
示す平面図、第３図は従来のＩＣ用リードフレームの第
１図Ａ−Ａ“断面の要部断面図、第４図は従来のＩＣ用
リードフレームの他の実施例に係る要部断面図。 １；金属基体、２　：Ａｕめっき層、３：Ｓｉベレット
、４；半導体素子固定部（タブ部）、５：金属細線、６
：Ａｕ−８ｔ共晶ろう材、ｌＡｇペーストろう材、８：
内部リード端子部、９：４２合金リードフレーム、１０
：外部リード部、１１：銅合金リードフレーム、１２：
Ａｇめっき！、１３：Ｎｉ−Ｆｅ合金めっき層、１４：
Ｐｄめっき層、１６：Ｆｅ−Ｃｒ合金リードフレーム、
第　１　旧 茅３　旧Fig. 1 is a cross-sectional view of a main part of a lead frame according to an embodiment of the present invention. Fig. 2 is a plan view showing an example of an IC lead frame. Fig. 3 is a sectional view of a conventional IC lead frame. FIG. 4 is a cross-sectional view of a main part of another embodiment of a conventional IC lead frame. 1: Metal base, 2: Au plating layer, 3: Si pellet, 4; Semiconductor element fixing part (tab part), 5: Fine metal wire, 6
:Au-8t eutectic brazing filler metal, lAg paste brazing filler metal, 8:
Internal lead terminal section, 9:42 alloy lead frame, 10
: External lead part, 11: Copper alloy lead frame, 12:
Ag plating! , 13: Ni-Fe alloy plating layer, 14:
Pd plating layer, 16: Fe-Cr alloy lead frame,
1st old kaya 3rd old

Claims (1)

【特許請求の範囲】[Claims] （１）金属基体上にＢ、Ｐ、Ｆｅ、Ｃｏのうち一つ以上
の元素を含有するＮｉ合金層を設けた後、更にその上に
少なくとも半導体素子を固定する領域および金属細線を
ボンディングする領域にＰｄあるいはＮｉを含有するＰ
ｄ合金メッキ層を設けたことを特徴とする半導体用リー
ドフレーム。(1) After providing a Ni alloy layer containing one or more elements among B, P, Fe, and Co on a metal substrate, a region on which at least a semiconductor element is fixed and a region on which a thin metal wire is bonded P containing Pd or Ni
A lead frame for semiconductors characterized by being provided with a d-alloy plating layer.
JP59262293A 1984-12-12 1984-12-12 Lead frame for semiconductor Pending JPS61140160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59262293A JPS61140160A (en) 1984-12-12 1984-12-12 Lead frame for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59262293A JPS61140160A (en) 1984-12-12 1984-12-12 Lead frame for semiconductor

Publications (1)

Publication Number Publication Date
JPS61140160A true JPS61140160A (en) 1986-06-27

Family

ID=17373768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59262293A Pending JPS61140160A (en) 1984-12-12 1984-12-12 Lead frame for semiconductor

Country Status (1)

Country Link
JP (1) JPS61140160A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162461A (en) * 1990-10-24 1992-06-05 Hitachi Cable Ltd Lead frame for semiconductor device
US5134459A (en) * 1989-05-01 1992-07-28 Sumitomo Electric Industries, Ltd. Lead frame for semiconductor device
JPH04211153A (en) * 1990-02-26 1992-08-03 Hitachi Ltd Semiconductor package and lead frame
DE4311872A1 (en) * 1993-04-10 1994-10-13 Heraeus Gmbh W C Lead frames for integrated circuits
US5889317A (en) * 1997-04-09 1999-03-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package
KR100231826B1 (en) * 1996-12-31 1999-12-01 유무성 Multi-chip package and its manufacturing method
EP1126520A3 (en) * 2000-02-18 2002-11-20 Hitachi, Ltd. IC device and method of manufacturing the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134459A (en) * 1989-05-01 1992-07-28 Sumitomo Electric Industries, Ltd. Lead frame for semiconductor device
JPH04211153A (en) * 1990-02-26 1992-08-03 Hitachi Ltd Semiconductor package and lead frame
JPH04162461A (en) * 1990-10-24 1992-06-05 Hitachi Cable Ltd Lead frame for semiconductor device
DE4311872C2 (en) * 1993-04-10 1998-07-02 Heraeus Gmbh W C Lead frames for integrated circuits
EP0621633A2 (en) * 1993-04-10 1994-10-26 W.C. Heraeus GmbH Leadframe for integrated circuits
EP0621633A3 (en) * 1993-04-10 1995-01-11 Heraeus Gmbh W C Leadframe for integrated circuits.
US5486721A (en) * 1993-04-10 1996-01-23 W.C. Heraeus Gmbh Lead frame for integrated circuits
JPH08111484A (en) * 1993-04-10 1996-04-30 W C Heraeus Gmbh Lead frame
DE4311872A1 (en) * 1993-04-10 1994-10-13 Heraeus Gmbh W C Lead frames for integrated circuits
KR100231826B1 (en) * 1996-12-31 1999-12-01 유무성 Multi-chip package and its manufacturing method
US5889317A (en) * 1997-04-09 1999-03-30 Sitron Precision Co., Ltd. Leadframe for integrated circuit package
EP1126520A3 (en) * 2000-02-18 2002-11-20 Hitachi, Ltd. IC device and method of manufacturing the same
US6891253B2 (en) 2000-02-18 2005-05-10 Renesas Technology Corp. Semiconductor integrated circuit device and method of manufacturing the same
US7038306B2 (en) 2000-02-18 2006-05-02 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US7176056B2 (en) 2000-02-18 2007-02-13 Renesas Technology Corp. Semiconductor integrated circuit device and method of manufacturing the same
CN1312748C (en) * 2000-02-18 2007-04-25 株式会社日立制作所 Method for mfg. semiconductor integrated circuit device
CN100380650C (en) * 2000-02-18 2008-04-09 株式会社日立制作所 Semiconductor integrated circuit device and mfg. method thereof
US7397114B2 (en) 2000-02-18 2008-07-08 Renesas Technology Corp. Semiconductor integrated circuit device and method of manufacturing the same

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