JPH04162461A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH04162461A
JPH04162461A JP28648490A JP28648490A JPH04162461A JP H04162461 A JPH04162461 A JP H04162461A JP 28648490 A JP28648490 A JP 28648490A JP 28648490 A JP28648490 A JP 28648490A JP H04162461 A JPH04162461 A JP H04162461A
Authority
JP
Japan
Prior art keywords
plating layer
plating
alloy
lead frame
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28648490A
Other languages
Japanese (ja)
Other versions
JP2682226B2 (en
Inventor
Satoshi Chinda
聡 珍田
Osamu Yoshioka
修 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2286484A priority Critical patent/JP2682226B2/en
Publication of JPH04162461A publication Critical patent/JPH04162461A/en
Application granted granted Critical
Publication of JP2682226B2 publication Critical patent/JP2682226B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a lead frame base for a semiconductor device which can be soldered at a low temperature even without flux by providing a gloss Ni plating layer on a base of a lead frame made of copper or copper alloy, and laminating an Ni-Fe-P alloy plating layer thereon. CONSTITUTION:The thickness of an Ni-plating layer 2 to be provided on a substrate (Cu or Cu alloy) 1 for a semiconductor substrate needs 2mum or more so as to suppress diffusion of the Cu from a substrate material and to obtain wire bondability. An Ni-Fe-P alloy plating layer 3 is thinly provided with the layer 2 as a base, and two gloss Ni/Ni-Fe-P layers are laminated by plating on the substrate Cu. However, since the layer 3 is very hard and brittle, it is improper to solely adhere it thickly, and its thickness is set to about 0.20mum. As a result that composition is analyzed by collecting part of the Ni-Fe-P alloy plating layer, if about 1-5wt.% of Fe and 3-15wt.% of P are contained, it is discovered that solder wettability is best at a soldering temperature of 280 deg.C even without flux.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体装置用リードフレームのめっき構造に
係り、特にNiめっきのはんだぬれ性を改善したリード
フレームに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a plating structure of a lead frame for a semiconductor device, and particularly to a lead frame with improved solderability of Ni plating.

[従来の技術] 半導体用リードフレームのめっき膜に要求される機能は
、ワイヤボンディング性、ダイボンデインク性等にすぐ
れていることは勿論であるが、特に、アウターリードピ
ンのめっき膜について、基板実装上の点からすぐれたは
んだぬれ性が求められる。
[Prior Art] The functions required of the plating film for semiconductor lead frames include excellent wire bonding properties, die bonding properties, etc., but in particular, the plating film for outer lead pins is required for board mounting. From the above points, excellent solderability is required.

特に、高出力用ICでは組立時および使用時の熱衝撃に
耐えるため、下地にNiのめっき層を設け、素子搭載部
にのみに銀めっきを設けた部分めっきリードフレームが
使用されており、アウターリードピンは、Niめっきで
被覆されている。
In particular, high-output ICs use partially plated lead frames with a Ni plating layer on the base and silver plating only on the element mounting area, in order to withstand thermal shock during assembly and use. The lead pins are coated with Ni plating.

Niは、耐食性酸化被膜を形成し易く、はんだぬれ性は
不良なので、ぬれ性をよくするためにはフラックスを使
用しなければならない。
Ni easily forms a corrosion-resistant oxide film and has poor solder wettability, so flux must be used to improve the solder wettability.

Niめっき層とはんだ層の間に、リンを含んだ旧めっき
層を設ける公知例として、特開昭60−3312号公報
、特開昭61−22458号公報なとがあげられる。
Known examples of providing an old plating layer containing phosphorus between the Ni plating layer and the solder layer include JP-A-60-3312 and JP-A-61-22458.

いずれにしても、リートピンに溶融はんだを設けた後、
残留フラックスを除去するために、フロン系溶剤または
トリクロルエチレンに代表される塩素系有機溶剤で後洗
浄をしなければならない。
In any case, after applying molten solder to the Riet pin,
In order to remove residual flux, it is necessary to perform post-cleaning with a chlorofluorocarbon solvent or a chlorinated organic solvent such as trichlorethylene.

[発明が解決しようとする課題] 近年、地球的規模の環境問題等から、前記のフロンおよ
び有機溶剤の使用については、禁止もしくは制限される
傾向にあり、ICなど電子部品の後洗浄に対しては厳し
い状況になりつつある。
[Problem to be solved by the invention] In recent years, due to global environmental issues, etc., the use of fluorocarbons and organic solvents has tended to be prohibited or restricted. The situation is becoming increasingly difficult.

したがって、はんだ付けには非塩素系のフラックスを使
用するか、あるいはフラックスなしでもはんたぬれ性の
よいNiめっき方法を開発するがなとの手段をとらなけ
ればならない。
Therefore, it is necessary to use non-chlorine flux for soldering, or to develop a Ni plating method that provides good solder wettability even without flux.

、Niめっきのはんたぬれ性を改善するためには、めっ
きの光沢化が効果があることは経験的に認められている
か、現状では、光沢Niめっきの場合は、はんた付温度
が高いため、より低温のはんた付温度で、フラックスな
しの状態下でも接合可能なNiめっき手段の開発が求め
られていた。
In order to improve the solder wettability of Ni plating, is it empirically recognized that making the plating glossier is effective?Currently, in the case of bright Ni plating, the soldering temperature is Therefore, there has been a demand for the development of a Ni plating method that can be bonded at lower soldering temperatures and without flux.

本発明の目的は、光沢旧めっき層を設けた基板上に、フ
ラックスなしでもより低温化ではんだ付けが可能な半導
体装置用リードフレーム基体を提供することである。
An object of the present invention is to provide a lead frame base for a semiconductor device that can be soldered at a lower temperature without flux onto a substrate provided with a bright old plating layer.

[課題を解決するための手段] 上記課題を解決するための本発明に係る半導体装置用リ
ードフレームの構成は、銅または銅合金からなるリード
フレームの基体上に、光沢Niめめっき層を設け、これ
に積層してNj−re−P合金めっき層を設けるように
したことである。
[Means for Solving the Problems] The structure of the lead frame for a semiconductor device according to the present invention for solving the above problems includes providing a bright Ni plating layer on the base of the lead frame made of copper or copper alloy, The Nj-re-P alloy plating layer is laminated thereon.

[作用] 半導体装置用基板(CuまたはCu合金)上に設けるN
iめっきの厚さは、基板材料からのCuの拡散を抑え、
ワイヤボンディング性を確保するために2μm以上必要
である。
[Function] N provided on a semiconductor device substrate (Cu or Cu alloy)
The thickness of i-plating suppresses the diffusion of Cu from the substrate material,
A thickness of 2 μm or more is required to ensure wire bondability.

本発明によるNi−Fe−Pめっき層を、Niめっき層
を下地として薄く設け、基板Cuの表面に光沢Ni/N
i−Fe−Pの2層のめっきを積層する。
The Ni-Fe-P plating layer according to the present invention is thinly provided on the Ni plating layer as a base, and the surface of the substrate Cu is coated with glossy Ni/N.
Two layers of i-Fe-P plating are laminated.

たたし、Ni−Fe−Pめっき層は、非常に硬く脆い性
質のため、単独で厚付けすることは、加工」二は不適当
であり、約0.20μmの厚さとする。
However, since the Ni--Fe--P plating layer is extremely hard and brittle, it is inappropriate to form it thickly by itself, so the thickness is set to about 0.20 μm.

本発明で採用したNi−Fe−Pめっき層の1部を採取
して、組成分析を行った結果、Feは、1〜5wt%程
度、Pは、3〜l 5 w t%程度含有した場合には
、はんだぬれ性は最も良好であることがわかった。
A part of the Ni-Fe-P plating layer employed in the present invention was sampled and analyzed for its composition, and it was found that it contained about 1 to 5 wt% of Fe and about 3 to 15 wt% of P. It was found that the solder wettability was the best.

[実施例] 以下本発明の一実施例を試験結果にもとづいて説明する
[Example] An example of the present invention will be described below based on test results.

まず、基板となる銅合金寸法、50mmX20mmX0
.25mmの試料を脱脂および酸洗処理により、清浄化
し、これら試料に光沢Niめっきを約3μm厚さに設け
た。光沢旧めっき液の組成はっぎの通りである。
First, the dimensions of the copper alloy that will become the substrate are 50mm x 20mm x 0.
.. 25 mm samples were cleaned by degreasing and pickling, and bright Ni plating was provided on these samples to a thickness of about 3 μm. The composition of the bright old plating solution is as shown below.

Ni5O・6H20・・・・・240g/1Nicl 
 ・6H20・・・・・・40g/1H3PO3・・・
・・・40g/l 荏原ニーシライト#61・・・5 ml / 1同  
     上    # 63 ・・・ 1. 0 m
l /  1ついで、上記試料の上にNi−re−P合
金めっきを0,15μm厚さに設けた。めっき液の組成
はつぎの通りである。
Ni5O・6H20...240g/1Nicl
・6H20...40g/1H3PO3...
...40g/l Ebara Nishilite #61...5ml/1 same
Top #63...1. 0 m
l/1 Then, Ni-re-P alloy plating was provided on the sample to a thickness of 0.15 μm. The composition of the plating solution is as follows.

Ni50  ・6H20・・・・・・160g/1Ni
c1  ・6H20・・・・・・40g/1H3PO3
・・・・・・6g/l Fe50 ・7H20・・・・・・o〜10g/1図は
本発明の実施例のリードフレームの部分断面図である。
Ni50 ・6H20・・・160g/1Ni
c1 ・6H20...40g/1H3PO3
...6 g/l Fe50 7H20...o~10 g/1 The figure is a partial sectional view of a lead frame according to an embodiment of the present invention.

図において、1は、銅合金基体、2は、光沢Niめっき
、3は、Ni−Fe−P合金めっきである。
In the figure, 1 is a copper alloy base, 2 is a bright Ni plating, and 3 is a Ni-Fe-P alloy plating.

以下に、はんだ付は性試験について説明する。Below, the soldering test will be explained.

まず、はんだ浴槽(Sn62%、Pb38%共品)を準
備し、上記のようにして調整した2層めっきを施した試
料(フラックスは使用しない)をサンプルクリップに挟
み、自動昇降装置を用いて、所定の試験温度に加熱した
はんたを浴槽中に10秒間浸漬し、引上げ、各浴槽毎に
、各試料のはんだぬれ状態を目視観察した。
First, prepare a solder bath (both 62% Sn and 38% Pb), hold the two-layer plating sample prepared as described above (no flux is used) between sample clips, and use an automatic lifting device to Solder heated to a predetermined test temperature was immersed in a bathtub for 10 seconds, pulled out, and the state of solder wetting of each sample was visually observed in each bathtub.

浸漬温度(はんた浴温)は、夫々240.260.28
0.300および320℃の5温度である。
The immersion temperature (solder bath temperature) is 240.260.28, respectively.
There are 5 temperatures: 0.300 and 320°C.

はんだぬれ状態の目視観察の判断基準の以下の通りであ
る。
The criteria for visual observation of the solder wet state are as follows.

O印:全表面が均一に完全にぬれたもの△印:わずかに
めっき面が露出したもの×印:10%以上の面積ではん
だがはがれ、下地面がはっきり露出したもの なお、比較のために、Ni−Fe−Pめっき層を設けな
い光沢Niめっき層のみの試料についても同様な条件で
試験し評価した。
O mark: The entire surface is completely and uniformly wetted. △ mark: The plating surface is slightly exposed. A sample with only a bright Ni plating layer without a Ni-Fe-P plating layer was also tested and evaluated under the same conditions.

つぎに、上記試料は、実際の組立工程て熱履歴をうける
ので、上記試料に150°C×30分の加熱処理を施し
た後のはんたぬれ性試験を行った。
Next, since the above sample is subjected to a thermal history during the actual assembly process, the above sample was subjected to a heat treatment at 150° C. for 30 minutes and then subjected to a solder wettability test.

浸漬試験条件は、すべて前記の加熱処理前のものと同様
である。
All immersion test conditions were the same as those before the heat treatment described above.

浸漬試験は、各試験に対して5回以上実施した。The immersion test was conducted five or more times for each test.

以上述べるように、Ni/ Ni −Fe −Pの2層
めっきを設けた試料を(1)加熱前および(2)加熱処
理(150℃X30分)後について、5n−Pb共晶は
んた浴槽中に、試験温度240〜320’Cの5段階の
温度で浸漬試験後のはんだぬれ性の観察結果を下記の表
に示す。
As described above, a sample provided with two-layer plating of Ni/Ni-Fe-P was heated in a 5n-Pb eutectic solder bath (1) before heating and (2) after heat treatment (150°C x 30 minutes). The table below shows the observation results of solder wettability after the immersion test at five test temperatures ranging from 240 to 320'C.

上記の表からつぎのことかわかる。The following can be seen from the table above.

(1)光沢Niめっき層のみのものと比べて、Ni−F
e −P /光沢Niめっき層(めっき液にFeSO4
なし)のものは、はんた浴温はほとんど不変である。
(1) Compared to the one with only a bright Ni plating layer, the Ni-F
e-P/bright Ni plating layer (FeSO4 in plating solution)
(without), the solder bath temperature remains almost unchanged.

(2)同上条件で、めっき液にF e S O4・7H
20を1g/l添加するとはんだぬれ性は向上し、はん
だぬれ温度は20〜40℃低温となる。
(2) Under the same conditions as above, add FeSO4.7H to the plating solution.
When 1 g/l of 20 is added, the solder wettability is improved and the solder wetting temperature is lowered by 20 to 40°C.

(3)同上条件で、めっき液にFeSO4・7H20を
5g/l添加すると最も効果的であり、加熱処理前およ
び後ではんた浴温を240〜260℃に低下させること
ができる。
(3) Under the same conditions as above, it is most effective to add 5 g/l of FeSO4.7H20 to the plating solution, and the solder bath temperature can be lowered to 240 to 260°C before and after heat treatment.

(4)同上条件で、めっき液にFeSO4・7H20を
10g/l添加すると反って、はんだ浴温は上昇し、は
んたぬれ性は不適となる。
(4) If 10 g/l of FeSO4.7H20 is added to the plating solution under the same conditions as above, the solder bath temperature will rise and the solder wettability will become unsuitable.

以上の結果から、Ni−Fe−Pめっき層を設けること
により、フラックスなしでも、280℃のはんだ温度で
、はんたぬれ性を保つことができる。
From the above results, by providing the Ni-Fe-P plating layer, solder wettability can be maintained at a soldering temperature of 280° C. even without flux.

特にNi−Fe−Pめっき層を設ける時に、めっき液中
への、Fe50 ・7H20の(硫酸第1鉄)の添加量
によって、その効果を高めることができる。すなわち、
Fe50  ・7H20の添加量を1〜5g/Iにした
場合の効果が最高で、260℃でもはんだぬれ性は良好
であることがわかった。
In particular, when forming a Ni-Fe-P plating layer, the effect can be enhanced by changing the amount of Fe50.7H20 (ferrous sulfate) added to the plating solution. That is,
It was found that the effect was the best when the amount of Fe50.7H20 added was 1 to 5 g/I, and the solder wettability was good even at 260°C.

[発明の効果コ 本発明により半導体装置用リードフレーム基板に光沢N
i/ Ni −Fe −Pの2層めっきを設け、フラ 
[Effects of the Invention] The present invention improves gloss N on lead frame substrates for semiconductor devices.
i/Ni-Fe-P two-layer plating is provided, and the flat
.

ックスなしで、より低温ではんだ付けが可能になるため
、従来のように、残留フラックス除去のための有機溶剤
による後洗浄処理作業を省くことができる。このことは
、 (1)  フロン等の材料費および人工費が節減できる
ことは言うまでもなく、 (2)  フロンのよる環境破壊、塩素系溶剤による発
癌性の問題を回避できるという大きな効果がある。また
、 (3)  はんだ付は時にフラックスを使用しないから
、残留フラックスによる電子部品の腐食による故障を起
こすことがない。
Since soldering can be performed at a lower temperature without using flux, the conventional post-cleaning process using an organic solvent to remove residual flux can be omitted. This has the great effect of (1) saving material and labor costs for fluorocarbons, and (2) avoiding environmental damage caused by fluorocarbons and carcinogenicity caused by chlorinated solvents. In addition, (3) soldering does not use flux, so there is no risk of failure due to corrosion of electronic components due to residual flux.

また、より低温度で、はんだ付は作業が可能となり、他
の電子部品に熱的な損傷を与えなくなるので基板の品質
向上に有効である。
In addition, soldering can be performed at lower temperatures and will not cause thermal damage to other electronic components, which is effective in improving the quality of the board.

【図面の簡単な説明】[Brief explanation of drawings]

図は、本発明の半導体装置用リードフレームの一実施例
の部分断面図である。 1:銅合金基体、 2:光沢Niめっき層、 3:Nj−Fe−P合金めっき層。 1、@合金基体 2、光1尺Niめ・〕き層 3 : Ni−Pθ−P合金めっき層
The figure is a partial sectional view of an embodiment of a lead frame for a semiconductor device according to the present invention. 1: Copper alloy base, 2: Bright Ni plating layer, 3: Nj-Fe-P alloy plating layer. 1. @Alloy base 2, Ni plating layer 3: Ni-Pθ-P alloy plating layer

Claims (1)

【特許請求の範囲】[Claims] 1、銅または銅合金からなるリードフレーム基体上に、
光沢ニッケルめっき層を設け、これに積層してNi−F
e−P合金めっき層を設けたことを特徴とする半導体装
置用リードフレーム。
1. On a lead frame base made of copper or copper alloy,
A bright nickel plating layer is provided, and Ni-F is laminated on this.
A lead frame for a semiconductor device characterized by being provided with an e-P alloy plating layer.
JP2286484A 1990-10-24 1990-10-24 Lead frame for semiconductor device Expired - Lifetime JP2682226B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2286484A JP2682226B2 (en) 1990-10-24 1990-10-24 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2286484A JP2682226B2 (en) 1990-10-24 1990-10-24 Lead frame for semiconductor device

Publications (2)

Publication Number Publication Date
JPH04162461A true JPH04162461A (en) 1992-06-05
JP2682226B2 JP2682226B2 (en) 1997-11-26

Family

ID=17704999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2286484A Expired - Lifetime JP2682226B2 (en) 1990-10-24 1990-10-24 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JP2682226B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110608A (en) * 1996-12-10 2000-08-29 The Furukawa Electric Co., Ltd. Lead material for electronic part, lead and semiconductor device using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140160A (en) * 1984-12-12 1986-06-27 Hitachi Cable Ltd Lead frame for semiconductor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140160A (en) * 1984-12-12 1986-06-27 Hitachi Cable Ltd Lead frame for semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110608A (en) * 1996-12-10 2000-08-29 The Furukawa Electric Co., Ltd. Lead material for electronic part, lead and semiconductor device using the same
USRE38588E1 (en) * 1996-12-10 2004-09-14 The Furukawa Electric Co., Ltd. Lead material for electronic part, lead and semiconductor device using the same

Also Published As

Publication number Publication date
JP2682226B2 (en) 1997-11-26

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