JPH0529517A - Lead frame for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a lead frame substratum for a semiconductor device wherein soldering on a substrate on which a lustrous Ni plated layer is formed is possible at a lower temperature even without using flux. CONSTITUTION:The title lead frame is constituted as follows; a lustrous Ni plated layer 2 is formed on a substratum of a lead frame, an Ni-P alloy plated layer 3 is laminated on the layer 2, and further an Ni-Co-P alloy plate layer 4 is formed on the layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame plating structure for semiconductor devices, and more particularly to a lead frame having improved Ni plating solder wettability.

[0002]

2. Description of the Related Art Needless to say, the functions required for a plated film of a semiconductor lead frame are excellent in wire bonding and die bonding, but particularly, the plating film of an outer lead pin is mounted on a substrate. From this point, excellent solder wettability is required.

In particular, in a high-power IC, a partially plated lead frame in which a Ni plating layer is provided on the base and silver plating is provided only on the element mounting portion is used in order to withstand thermal shock during assembly and use. , The outer lead pin,
It is covered with Ni plating. Ni easily forms a corrosion-resistant oxide film and has poor solder wettability, so a flux must be used to improve wettability.

As a known example of providing a Ni plating layer containing phosphorus between the Ni plating layer and the solder layer, Japanese Patent Publication No. 60-
No. 33312 and Japanese Patent Publication No. 61-22458 are known examples of providing a cobalt-containing Ni plating layer on a cobalt-containing Ni plating layer.

In any case, after the lead pin is provided with the molten solder, it is necessary to perform post-cleaning with a fluorocarbon solvent or a chlorine organic solvent represented by trichlorethylene in order to remove the residual flux.

[0006]

However, in recent years, due to environmental problems on a global scale, the use of the above-mentioned CFCs and organic solvents tends to be prohibited or restricted. Is getting into a difficult situation.

Therefore, it is necessary to take measures such as using a non-chlorine type flux for soldering, or developing a Ni plating method having good solder wettability without flux.

It has been empirically recognized that in order to improve the solder wettability of the Ni plating, brightening the plating is effective, but at present, in the case of the bright Ni plating, the soldering temperature is high. Therefore, there has been a demand for the development of a Ni plating means that can be joined at a lower soldering temperature even in a state without flux.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a lead frame substrate for a semiconductor device, which can be soldered on a substrate provided with a bright Ni plating layer at a lower temperature without flux. Is to provide.

[0010]

The structure of a lead frame for a semiconductor device according to the present invention for solving the above-mentioned problems is as follows.
Provide a bright Ni plating layer on the lead frame substrate,
It is characterized in that a Ni-P alloy plating layer is provided by laminating on this, and a Ni-Co-P alloy plating layer is provided thereon.

Referring to FIG. 1, the lead frame for a semiconductor device of the present invention is provided with a bright Ni plating layer 2 on a substrate 1 of the lead frame in FIG. 1, and is laminated thereon to form a Ni--P alloy plating layer 3. And Ni-C on top of it
It is provided with an op alloy plating layer 4.

In the present invention, copper, copper alloy or iron alloy is used as the lead frame substrate.

The thickness of the bright Ni plating layer provided on the semiconductor device substrate is required to be 2 μm or more in order to suppress the diffusion of metal from the substrate material and to secure the wire bonding property. The Ni-Co-P alloy plating layer provided on the uppermost layer exhibits extremely excellent solderability by itself. In addition, Ni of the intermediate layer
The -P alloy plating layer also has better solderability than the bright Ni plating layer. However, these plating layers are so hard and dangerous that they cannot be thickly plated on electronic parts that require bending. Therefore, after providing the bright Ni plating layer as a base plating for about 3 μm, the Ni-P alloy plating layer is about 0.1 μm.
5 μm, Ni-Co-P alloy plating is about 0.03 μm on the uppermost layer to provide superior solderability.
Plate as a three-layer structure provided. Solderability by this plating method is such that the bright Ni plating layer alone and Ni-P /
It is remarkably improved as compared with the case of two-layer plating of bright Ni, and the plating crack phenomenon due to bending does not occur. The thickness of the underlying bright Ni plating layer is about 2 to 5 μm and the thickness of the intermediate layer is N.
The total thickness of the i-P alloy plating and the uppermost Ni-Co-P alloy plating is preferably in the range of 0.05 to 0.2 μm.
If the total thickness of the Ni-P layer and the Ni-Co-P alloy plating layer is set to be thicker than 0.2 μm, a plating crack phenomenon may occur when the electronic component is bent. Taking a part of the Ni-Co-P alloy plating layer adopted in the present invention,
As a result of compositional analysis, it was found that the solderability was the best when Co was contained in an amount of about 0.3 to 20% by weight and P was contained in an amount of about 2 to 15% by weight.

The composition of the Ni-P plating layer of the intermediate layer has a P content of about 2 to 15% by weight, and the balance is Ni. The plating solution for depositing a film having a P content of 15% or more has a high phosphorous acid (H ₃ PO ₃ ) concentration in the solution and the deposition efficiency decreases, so the upper limit of the P content may be about 15%.

The underlying Ni layer is preferably bright plated, and a brightening agent and a stress relaxation agent are added to the plating solution.

[0016]

[Examples] (Sample preparation) A lead frame made of a copper alloy was cleaned by degreasing and pickling, and then a plating solution having the composition shown below was used on the entire surface to obtain (bright Ni plating solution composition) NiSO ₄ .6H ₂ O 240 g / l NiCI ₂ .6H ₂ O 40 g / l H ₃ BO ₃ 40 g / l Ebara Eugelite # 61 5 ml / l 〃 # 63 10 ml / l Bright Ni plating current density 4 A / dm ² and provided about 3 μm.

On top of this, a plating solution having the composition shown below (Ni-P plating solution) was used. (Ni-P plating solution composition) NiSO ₄ .6H ₂ O 160 g / l NiCI ₂ .6H ₂ O 40 g / l _{H 3 PO 3 10g / l Ni} -P alloy plating current density 4A / dm ² at about 0.15
μm was provided.

Furthermore using a plating solution having the composition shown in the following (Ni-Co-P plating solution) thereon, (Ni-Co-P plating solution _{composition) NiSO 4 · 6H 2 O 160g} / l NiCI 2 · 6H ₂ O 40 g / l CoSO ₄ .7H ₂ O 0 to 30 g / l H ₃ PO _{3 0 to} 20 g / l Ni—Co—P alloy plating current density 4 A / dm ² and provided about 0.05 μm.

For Ni-Co-P alloy plating, the concentration of phosphorous acid (H ₃ PO ₃ ) in the plating solution is 0 to 20 g.
/ L, the ₍₂ O CoSO ₄ · 7H) Concentration Cobalt sulfate 0
The amount of P and Co in the deposited film was quantified by changing each in the range of up to 30 g / l.

(Soldering Test Method) Lead frame 1
Put the piece in a clip and use an automatic lifting device to use eutectic solder (tin 62%, lead 38%) without using flux.
%) Was immersed in a molten solder bath for 10 seconds and then pulled up. Solder bath temperature from 240 ℃ to 320 ℃ in 320
The temperature was gradually changed to 0 ° C., and the solder wet state of each sample at each solder bath temperature was visually observed. It can be said that the lower the temperature at which the solder wets, the better the solderability.

The lead frame is always subjected to heat history during assembly. Therefore, in order to simulate the solderability after passing through the heat history of the assembly process, the lead frame after each plating was heat treated at 150 ° C. for 30 minutes, and then a solderability test was performed. The test was performed 3 times or more per one condition. The evaluation criteria of the soldering state are as follows.

◯: The entire surface is uniformly wet.

Δ: Almost wet, but the underlying plating surface was slightly exposed and dewetting phenomenon was observed.

X: Solder is repelled and the exposed underside is clearly visible.

The results of the solderability test are shown in Table 1.

[0026]

[Table 1]

As a result, it was shown that the lead frame for a semiconductor device of the present invention is remarkably superior in solderability as compared with the comparative example having only bright Ni plating.

[0028]

Since the lead frame of the present invention does not require the use of flux during soldering, there is no risk of contamination by residual flux, and the reliability of the semiconductor is significantly improved. Further, since cleaning is not required after assembling the semiconductor, it has a great effect on the environment and economically. Even without flux, at lower temperature (260 ℃, 280 ℃)
But soldering is now possible.

The Ni-P alloy plating of the intermediate layer is omitted,
Even with a Ni-Co-P / bright Ni two-layer plating structure in which only Ni-Co-P alloy plating is provided at 0.2 μm or more,
Shows excellent solderability, but Co is expensive, so
The plating film containing Co is preferably as thin as possible. In this respect, the present invention is an extremely thin Ni-Co-P alloy plating film having an excellent solderability and is formed on the uppermost layer to a thickness of 0.05 to 0.2 [mu] m, which enables cost reduction.

[Brief description of drawings]

FIG. 1 is a side sectional view of a lead frame for a semiconductor device of the present invention.

[Explanation of symbols]

 1 Lead frame substrate 2 Bright nickel plating layer 3 Ni-P alloy plating layer 4 Ni-Co-P alloy plating layer

Claims (1)

Claim: What is claimed is: 1. A bright Ni plating layer is provided on a lead frame substrate, and a Ni-P alloy plating layer is provided on the bright Ni plating layer.
A lead frame for a semiconductor device, further comprising Ni-Co-P alloy plating thereon.