JPH0758463B2 - Data processing device - Google Patents

Description

The present invention relates to a data processing device, and more particularly to a data processing device having a pipeline mechanism.

[Prior Art] FIG. 2 is a diagram showing a mechanism for processing an instruction in a data processing device having a conventional pipeline mechanism. In FIG. 2, the data processing device comprises a fetch decode mechanism 1, an instruction execution mechanism 2 and an address generation mechanism 3. The fetch / decode mechanism 1 fetches and decodes an instruction, and the instruction execution mechanism 2 executes an instruction. The address generation mechanism 3 is composed of a program counter (hereinafter referred to as a decoding program counter) 31 indicating the address of an instruction fetched and decoded by the fetch decoding mechanism 1 and an adder 32, and fetches a certain instruction. After decoding, the address of the instruction to be fetched next is generated.

Next, the operation will be described. Fetch decoding mechanism 1
The instruction is fetched and decoded, and at the same time, the address generation mechanism 3 adds the length of the fetched instruction to the program counter 31 for decoding, and calculates the address of the instruction to be fetched next. Next, the instruction is transferred to the instruction execution mechanism 2 and executed, and at the same time, a new next instruction is fetched from the address indicated by the decoding program counter 31 and decoded by the fetch decoding mechanism 1.

[Problems to be Solved by the Invention] Since the conventional data processing device is configured as described above, when the conditional branch instruction is fetched and decoded and transferred to the instruction execution mechanism 2, the fetch decode mechanism 1 , The instruction located next to the conditional branch instruction in the program is fetched and decoded, and the conditional branch instruction is executed. As a result, when a branch occurs, the instruction that has already been fetched and is being decoded must be canceled, and the fetching of the next instruction from the jump destination address of the branch must be redone. If one stage of the pipeline takes one machine cycle, the conditional branch instruction will eventually take two machine cycles, resulting in a problem of lower throughput.

Therefore, a main object of the present invention is to provide a data processor capable of increasing the throughput by minimizing the frequency of disturbance of the pipeline that occurs when a conditional branch instruction is executed.

[Means for Solving Problems] A data processing device according to the present invention includes a first mechanism and a second mechanism.
The second mechanism continues the first period based on the address of the first instruction processed by the first mechanism at the first period. , The address of the second instruction to be processed by the first mechanism is calculated, and when the conditional branch instruction is fetched and decoded, it is predicted in the early stage of the pipeline whether a branch will occur, When it is determined that a branch will occur, the branch condition of the conditional branch instruction is reversed, and the displacement of the conditional branch instruction and the instruction length of the conditional branch instruction are interchanged.

[Operation] The data processing device according to the present invention predicts whether a branch will occur when a branch instruction is fetched at an early stage of the pipeline, and if it is determined that the branch will occur, the branch condition of the conditional branch instruction is set. While inverting, the displacement of the branch is replaced with its instruction length, the instruction length is moved to the next stage, the displacement of the branch is added, and the next instruction is fetched from the jump destination address of the branch.

Embodiment of the Invention FIG. 1 is a schematic block diagram of an embodiment of the present invention.
In the embodiment shown in FIG. 1, the fetch decode mechanism 1, the instruction execution mechanism 2 and the address generation mechanism 3 are the same as those in the second embodiment.
The configuration is similar to that of the figure, and a prediction table 4 and an instruction length replacement mechanism 5 are further provided. The prediction table 4 is a table for predicting whether or not a branch will actually occur by a conditional branch instruction given from the fetch decoding mechanism 1 based on the past behavior of the instruction. The prediction table 4 stores a conditional branch instruction and a flag for predicting whether or not it actually occurs. And if Bragg stands, it means that a branch will happen. The instruction length substitution mechanism 5 inverts the bit indicating the branch condition in the decoding result of the conditional branch instruction. For example, change from branching if the zero flag is set to branching if the zero flag is not set. Then, the displacement of the branch in the decoding result is replaced with the instruction length of the instruction. That is, when it is predicted that a branch will occur in the prediction table 4, the instruction replacement mechanism 5 replaces the displacement of the conditional branch instruction from the fetch decode mechanism 1 with the instruction length of that instruction, and the program counter 31 included in the address generation mechanism 3 Is added to the branch displacement instead of the instruction length during the fetch decoding period, and is added to the program counter included in the instruction execution mechanism 2 (in the instruction execution mechanism 2 separately from the program counter included in the address generation mechanism 3). Is added with the instruction length instead of the branch displacement during the instruction execution period.

Next, a specific operation of the embodiment of the present invention will be described. If an instruction comes to the fetch decode mechanism 1 and it is a normal instruction, the fetch decode mechanism 1 decodes the instruction, and the instruction length is transferred to the program counter of the address generation mechanism 3 via the instruction length replacement mechanism 5. Add to 31. However, when it is found that the instruction given to the fetch decoding mechanism 1 is a conditional branch instruction, the prediction table 4
Based on, it is predicted whether a branch will occur. When it is predicted that a branch will occur, the instruction length replacement mechanism 5 exchanges the displacement of the conditional branch instruction and its instruction length, and reverses the condition of the branch. For example, if the Z flag is set, branch is performed, whereas if the Z flag is not set, branch is performed. Then, an instruction length is given to the instruction execution mechanism 2 instead of the displacement, and a displacement is added to the program counter 31 instead of the instruction length.

Then, the fetch decoding mechanism 1 fetches the next instruction from the jump destination address of the branch. Even if the prediction in the fetch decode mechanism 1 is wrong, the branch condition of the conditional branch instruction is inverted, and the displacement of the branch is replaced by the instruction length, so that the instruction execution mechanism 2 has a program condition. A branch to the instruction located next to the branch instruction occurs, this instruction is fetched and decoded by the fetch decoding mechanism 1, and the same operation as that when the conditional branch before the branch condition is inverted does not occur is obtained.

Instead of reversing the branch condition when it is predicted that a branch will occur, the execution sequence of the instruction execution mechanism 2 is set so that the branch is taken if the branch condition is not satisfied (normally, the branch condition is satisfied). if,
There is also a way to make a branch.

[Effects of the Invention] As described above, according to the present invention, by predicting the execution result of a conditional branch instruction in advance with a high probability, the only instruction fetched into the pipeline next to the conditional branch instruction is fetch and decode. Therefore, the probability of having to be fetched and decoded again by the time it goes to the execution stage and to be executed again is reduced, so that the pipeline is less disturbed and throughput can be improved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.
FIG. 2 is a schematic block diagram of a conventional data processing device. In the figure, 1 is a fetch decode mechanism, 2 is an instruction execution mechanism, 3 is an address generation mechanism, 4 is a prediction table, 5 is an instruction length replacement mechanism, 31 is a program counter, and 32 is an adder.

Claims (1)

[Claims] 1. An instruction processing unit including a first mechanism and a second mechanism, wherein the first mechanism and the second mechanism process an instruction on the principle of pipeline processing, and the first mechanism. Based on the address of the first instruction processed by the mechanism at the first time, the second instruction to be processed by the first mechanism at the second time subsequent to the first time is processed. Instruction address calculation means for calculating an address, branch prediction means for predicting whether or not the first instruction causes a branch, displacement to a branch destination instruction indicated by the first instruction, and the first instruction A data processing apparatus comprising: a displacement replacement unit that replaces the instruction length of 1. and a branch condition inversion unit that inverts a branch condition when the branch prediction unit determines that a branch will occur.