JP3419276B2 - Instruction prefetch apparatus and instruction prefetch method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetch device and an instruction prefetch method, and more particularly to an instruction prefetch device and an instruction prefetch method capable of efficiently executing pipeline processing in a processor.

[0002]

2. Description of the Related Art Currently, most computers store programs as well as data in storage devices.
The Neumann architecture for reading and executing this is adopted. Generally, a Neumann computer mainly comprises a computer having a processor such as a CPU for controlling execution of programs and a main memory for temporarily storing programs and data, and I / O for inputting / outputting data to / from a user or the outside. It is realized as a computer system having an (input / output device) and an auxiliary storage device (secondary storage device) for storing programs and data for a long time.

In executing a program under the control of a processor, an instruction process for reading a command of a program stored in a main memory and sending a control signal to each part of a computer is executed based on the content thereof. Inside the processor, there are provided a program counter for designating a storage location in the main memory of an instruction to be executed, and an instruction register for storing an instruction.

FIG. 6 (a) is a diagram for explaining the control operation in the instruction processing under the control of the processor. First, in the instruction fetch process, the instruction to be executed next is read by referring to the program counter.
In the next instruction decoding process, the type of the read instruction is determined and the instruction is interpreted. In the subsequent instruction execution processing, processing such as data reading and arithmetic processing is executed according to the instruction. Then, in the result storing process, the result obtained by executing the instruction is stored. As shown,
Each process is performed from timing CLn to timing CLn + 3 at each timing corresponding to a machine cycle.

Generally, a program is executed by sequentially executing a plurality of instructions, but FIG. 1B shows a case where the instruction A and the instruction B are sequentially executed. In the case shown in FIG. 6B, in the instruction fetch processing, the instruction A is read by referring to the program counter,
The instruction decoding process interprets the content instructed by the instruction A, the process according to the instructed content is performed in the instruction execution process, and the result obtained by the instruction execution is appropriately stored in the result storage process. At the next timing, the instruction fetch process for the instruction B is executed to read the instruction B, and the instructions are sequentially processed in this manner. If the processing of the instruction A is performed from the timing CLn to the timing CLn + 3 as in the case of FIG. 9A, the execution of the instruction B is performed from the timing CLn + 4.

FIG. 1C is a diagram for explaining pipeline processing for improving efficiency and speed of processing. Here, it is possible to perform the four processes of “instruction fetch”, “instruction decode”, “instruction execution”, and “result storage” as pipeline processing in an overlapping manner, that is, four control operations are performed in parallel. It should be possible to carry out. At the timing CL1,
The instruction fetch process of the instruction A is performed. Next timing C
In L2, the decoding process for the instruction A and the fetch process for the instruction B are performed. At the next timing CL3, execution processing for the instruction A, decoding processing for the instruction B, and fetch processing for the instruction C are performed. By executing the pipeline processing in this way, it becomes possible to concurrently process a number of instructions equivalent to the number of pipeline processings, and to speed up the processing.

Here, if the instructions A to D are simply instructions to be sequentially executed, the ideal pipeline processing can be performed by processing in the program description order. But in the program,
Iterative processing and branch / selection processing are frequently used, and a plurality of instructions are not always processed in the order described. In addition, the result of the execution process of the preceding instruction may be used to process the subsequent instruction, or branch / selection may be performed. It will be necessary for commercialization.

A method of instruction prefetch with prediction processing in the prior art will be described below. Conventionally, in the instruction fetch processing in pipeline processing, the instruction fetch processing is performed by predicting the next instruction before the address of the next instruction to be executed is finally determined. The instruction fetch processing by such prefetching is called instruction prefetch processing. An instruction prefetch device according to the related art that executes an instruction prefetch process accompanied by a prediction process in a processor will be described below.

FIG. 7 is a diagram showing a configuration of a prefetch device according to a conventional technique, FIG. 8 is a diagram showing a part of a program including an instruction to be subjected to prefetch processing, and FIG.
FIG. 6 is a timing chart diagram showing a schematic operation when processing is performed by a conventional prefetch device. As shown in FIG. 7, the conventional instruction prefetch device includes a prefetch address generation unit 300, a first decoding unit 303,
The configuration includes a branch prediction unit 304, an instruction buffer 305, a second decoding unit 306, an operation execution unit 307, and a condition code holding unit 308.

The prefetch address generator 300 generates an address to be prefetched next based on the prediction of the branch predictor 304 and the condition code, and outputs a prefetch address signal S301. First decoding unit 30
3 performs a decoding process on the prefetched instruction S302 to acquire the instruction, and an instruction buffer 3 to be described later.
This is output to 05. Also, the first decoding unit 3
03 determines the type of the prefetched instruction S302 based on the result of the decoding process, and when the instruction S302 is a conditional branch instruction, a signal indicating that is issued to the branch prediction unit 304 and the prefetch unit described later. It is output to the address generator 300. The branch prediction unit 304 predicts how the branch of the processing procedure will be performed in order to prefetch the instruction following the conditional branch instruction, and outputs the prediction result to the prefetch address generation unit 300.
As a prediction method, a method of determining a branching direction in advance based on the probability of branching, or a method of storing a branching direction in the same conditional branch in the past and setting it according to the history of the stored branching direction Etc. can be used. The instruction buffer 305 temporarily stores the instruction acquired by the decoding processing of the first decoding unit 303 for the subsequent processing. The second decoding unit 306 takes out the temporarily stored instructions from the instruction buffer 305, sequentially decodes the instructions, and controls the arithmetic processing in the later-described arithmetic execution unit according to the obtained result. Calculation execution unit 3
07 executes an operation under the control of the second decoding unit 306, and if the condition code held by the condition code holding unit 308 described later changes according to the result of the operation, the condition code holding unit 308 A signal indicating the result is output. The condition code holding unit 308 is a calculation execution unit 307.
The condition code obtained based on the arithmetic processing result input from is stored.

The outline of the operation of the conventional instruction prefetch device having the above-described structure is as follows. At a certain timing, the prefetch address generator 3
At 00, the address of the instruction to be fetched next is generated and output as the prefetch address signal S301. A processor using the instruction prefetch device fetches an instruction using the prefetch address signal S301 and inputs the instruction to the instruction prefetch device. At the next timing, the prefetched instruction is input to the first decoding unit 303 and decoded.

The first decoding unit 303 determines whether the processed instruction is a conditional branch instruction. If it is a conditional branch instruction, the prefetch address generation unit 300
Then, a signal indicating that is output to the branch prediction unit 304. In addition, the processed instruction is processed in the instruction buffer 305 regardless of whether it is a conditional branch instruction or not.
Output to.

The instruction temporarily stored in the instruction buffer 305 is taken out by the second decoding unit 306 and subjected to a decoding process to interpret the content of the instruction. The second decoding unit 306 outputs a signal indicating the content of the acquired instruction to the arithmetic execution unit 307, and the arithmetic execution unit 307 executes arithmetic processing according to the content of the instruction based on the input signal. . The result of the arithmetic processing is processed in the processor including the instruction prefetch device, and when the result of the arithmetic processing affects the condition code, it is output to and held in the condition code holding unit 308. .

On the other hand, when the signal indicating that it is a conditional branch instruction is input from the first decoding unit, the branch prediction unit 304 performs prediction processing according to the set method and prefetches a signal indicating the result of prediction. It is output to the address generator 300. The prefetch address generation unit 300 generates an address of an instruction to be prefetched next, but here, the prefetch address generation unit 300
If the signal indicating that the instruction is a conditional branch instruction is not input from the decoding unit 303, the condition code held in the condition code holding unit 308 is referred to, and the address of the instruction to be prefetched next is determined. It is generated and output as the prefetch address signal S301. On the other hand, if a signal indicating that the instruction is a conditional branch instruction is input from the first decoding unit 303, the next prefetch is performed based on the signal indicating the prediction input from the branch prediction unit 304. An address of a power instruction is generated and this is output as a prefetch address signal S301.

Here, the case where the program shown in FIG. 8 is processed will be described according to the timing chart of FIG. 9, but the program shows the following processing procedure. In the figure, an instruction 400 is an addition instruction, which performs addition processing on the data stored in the registers D0 and D1 and outputs the result to the register D2.
Is meant to be stored in. In this program, according to the operation result of executing the instruction 400,
The branch in instruction 401 is to be determined. In other words, the condition code used by the instruction 401, which is a conditional branch instruction, to determine a branch changes depending on the execution result of the instruction 400. Here, if the result is 0, the zero flag of the condition code is set. The instruction 401 is a conditional branch instruction, and a processing procedure is branched by selecting an instruction to be executed next according to the zero flag of the condition code. Here, if the zero flag is not set, the instruction to be executed next is the instruction 403, and if it is set, the instruction to be executed next is the instruction 402.

Next, in the instruction prefetch device according to the conventional technique, the operation when the processor using the prefetch device executes the program shown in FIG. 8 will be described below with reference to the timing chart of FIG. At timing t1 shown in the chart of FIG. 9, the address of the instruction 400 is generated in the prefetch address generation unit 300, and the prefetch address signal S301 is generated.
Is output as. In the processor using the instruction prefetch device, the instruction 400 is fetched using this prefetch address signal S301 and input to the instruction prefetch device. At the next timing t2,
The prefetched instruction 400 is stored in the first decoding unit 30.
3 and is decoded.

Since instruction 400 is not a conditional branch instruction,
The instruction 400 is output to the instruction buffer 305 without outputting a signal indicating that it is a conditional branch instruction. The second decoding unit 306 transfers the instruction 40 from the instruction buffer 305.
By fetching 0 and decoding it, the instruction 40
It interprets that 0 is an addition instruction, and the result of decoding processing is transmitted to the operation execution unit 307 by signal output. The arithmetic execution unit 307 executes the addition process indicated by the instruction 400,
As described above, since the result of the addition process of the instruction 400 may affect the condition code, the result of the addition process is output to the condition code holding unit 308, and the condition code holding unit 308 is changed. Holds the condition code. As described above, if the addition result is 0, the zero flag of the condition code is set, but here it is assumed that the operation result is not 0 and the zero flag is not set. At timing t3 in FIG. 9, the condition flag for determining the conditional branch in the instruction 401 is settled.

Thereafter, at timing t3, the instruction 4
The address 01 is generated, the instruction 401, which is a conditional branch instruction, is fetched, input to the prefetch device at timing t4, and decoded by the first decoding unit 303. Since the instruction 401 is a conditional branch instruction, the signal indicating that is output from the first decoding unit 303 to the prefetch address generation unit 300 and the branch prediction unit 304.

The branch predictor 304 to which the signal is input performs prediction and outputs a signal indicating the result to the prefetch address generator 300. Here, the branch prediction unit 304
The prediction by is assumed to have been set to predict the "instruction described next in the program". Therefore, a signal indicating the "next instruction" is output from the branch prediction unit 304 to the prefetch address generation unit 300, and at the timing t5 in FIG.
00 generates the address of the instruction 402 which is the “next instruction” of the conditional branch instruction 401, and outputs the prefetch address signal S301 indicating the “instruction 402”. In the processor, the instruction 402 is prefetched, and the instruction 402 is input to the first decoding unit 303 at timing t4 in FIG.

On the other hand, the conditional flag determined at the timing t3 is used to judge the conditional branch of the instruction 401. Since the zero flag is not set by the above setting, the next instruction to be executed is the instruction 403.
This corresponds to the determination of the branch destination address at the timing t6 in FIG. At this stage, the address of the instruction to be fetched next is originally determined, but in this example, the original address (address of the instruction 403) and the address generated by the prefetch address generation unit 300 at the timing t5. (Address of instruction 402) does not match, that is, a branch prediction error has occurred, so at the next timing t7, prefetching of the next instruction is started again.

[0021]

In the above-described conventional instruction prefetch device, when there is a conditional branch instruction, the instruction following it is prefetched exclusively based on the prediction of the branch prediction unit 304. I will. Then, as shown in FIG. 9, even when the execution of the instruction 400 is completed at the time when the conditional branch instruction 401 is prefetched and the condition code is fixed (timing t3), this result is used. The next prefetch instruction cannot be determined. Therefore, if the prediction is correct, smooth pipeline processing will be performed, and the processing efficiency will be good, but if the prediction is incorrect, the already fetched instruction will be canceled and the correct instruction There is a problem that a delay occurs due to fetching. Also, the instruction 40 in this example
The prefetch of No. 2 is a useless operation, and the device resources are not utilized as a whole processor including the prefetch device.

The present invention has been made in view of the above problems. If the condition is fixed at the time of prefetching the conditional branch instruction, the instruction prefetch is executed according to the fixed condition. An object of the present invention is to provide an instruction prefetch device capable of reducing delay due to branch misprediction and performing efficient processing utilizing device resources.

[0023]

In order to achieve the above object, an instruction prefetch device according to claim 1 is an instruction prefetch device for prefetching from a storage device storing the instruction in a computer that executes the instruction, The prefetched instruction determines whether or not it is a branch instruction for instructing branching, and if it is a branch instruction, branch determination means for outputting a branch signal, and when the branch signal is output, It is determined whether or not the condition for determining the branch in the branch instruction is fixed, and if the condition is fixed, the fixed condition information corresponding to the condition is output to the prefetch address generating means described later. The condition information generating means, a branch predicting means for generating information designating a branch destination instruction according to a predetermined branch predicting method, and the definite condition information generating means, When the information is input, an address to be prefetched is generated based on the definite condition information, and when the definite condition information is not input, the address to be prefetched is generated based on the information generated by the branch prediction unit. And a prefetch address generating means for generating the branch instruction.
Whether the conditions that determine the branch in the decree have been established
Judges and outputs the condition confirmation signal when it is confirmed
The condition confirmation signal generating means outputs the condition confirmation signal.
If so, obtain the confirmed conditions and obtain the above
Condition confirmation judgment that generates the above-mentioned confirmation condition information based on the condition
And a condition determining signal generating device.
Holds the address output from the branch determination means
First instruction address holding means and the actual
A second instruction add that holds the address of the instruction being executed
Address holding means, the first instruction address holding means,
Address held by the second instruction address holding means
The comparison process is performed and it is determined that they match in the above comparison.
The condition determination signal, the condition determination signal
In the prefetch of the instruction following the branch instruction, if the condition is fixed, the address of the instruction corresponding to the fixed condition is generated and fixed. If not, the address of the instruction is generated according to a predetermined prediction method. Also,
Communicates whether or not the condition is confirmed by the condition confirmation signal
However, if the condition is confirmed, the condition is used.
In addition, determine whether the condition has been finalized by confirming the condition.
The address of the instruction that is executing with the address of the instruction that is executing
This is executed, and it is determined whether or not the condition is fixed.

An instruction prefetch device according to a second aspect is the device according to the first aspect, wherein the branch determining means is
Is whether the prefetched instruction is a condition generation instruction or not.
If it is a condition generation instruction, the condition generation instruction
The address of the command to the first instruction address holding means
And output to the condition confirmation determination means,
The condition undetermined signal is output.
As a branch signal, information indicating the branch condition in the branch instruction
Report is output to the condition confirmation determining means.
Information indicating the branch destination address in the above branch instruction
Is output to the prefetch address generating means.
It executes the judgment process for the condition generation instruction.
By holding the address, the address comparison
Make a judgment about the condition confirmation.

Further, the instruction prefetching device according to claim 3, The apparatus of claim 2, said condition determination judging hand
When the above condition confirmation signal is input, the stage
Use the address next to the decree or the branch destination address above.
Condition confirmation information indicating that the prefetch address is
It is output to the compensator, and the
Generates the address of the corresponding instruction.

According to a fourth aspect of the present invention, there is provided an instruction prefetch device, which comprises an instruction determining means for determining whether the prefetched first instruction is a conditional branch instruction, and a condition generating instruction immediately before the first instruction. means for storing the addresses, the stored address, and comparing means for comparing the address of the instruction being executed, in a case where the first instruction is determined to conditional branch instruction, a Te to the comparison means When a match of the address is detected, the prefetch address generating means for outputting the prefetch address from the determined condition is provided, and the condition generation is performed to determine whether or not the branch condition is determined. When the instruction is executed, it is determined in advance, and if the condition is confirmed, the prefetch address of the instruction based on the condition is generated.

According to a fifth aspect of the present invention, there is provided an instruction prefetch method, which comprises an instruction determining step of determining whether the prefetched first instruction is a conditional branch instruction and a condition generating instruction immediately before the first instruction. a step of storing the addresses, the stored address, a comparison step of comparing the address of the instruction being executed, in a case where the first instruction is determined to conditional branch instruction, a Te on the comparison step When a match of the address is detected, a prefetch address generation step of outputting a prefetch address based on the determined condition is included, and whether or not the branch condition is determined is determined by a condition generation instruction. It is determined in advance at the time of execution, and if the condition is fixed, the prefetch address of the instruction based on the condition is generated.

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. The instruction prefetch device according to the first embodiment of the present invention uses a condition decision signal indicating whether or not a branch condition is decided, and when the condition is decided, prefetches an instruction corresponding to the condition. is there. FIG. 1 is a block diagram showing the configuration of the instruction prefetch device according to the first embodiment. As shown, the first embodiment
The instruction prefetch device by means of the prefetch address generation unit 100, the first decoding unit 101, the condition generation instruction address holding unit 102, the condition determination determination unit 103, the instruction buffer 104, the second decoding unit 105, the condition code holding unit 106, the operation execution Unit 107, program counter 10
8 and a comparator 109.

The prefetch address generation unit 100 uses the prefetch address information S114 output from the condition determination determination unit 103 to generate an address to be prefetched next, and outputs the prefetch address signal S110 output from the device of the instruction prefetch device. Output. The first decoding unit 101 performs a decoding process on the prefetched instruction S112 to obtain information S indicating the content of the instruction.
116 is acquired and is output to the instruction buffer 104 described later.

Further, the first decoding section 101 functions as a branch judging means for judging whether or not the instruction is a branch instruction and, if it is a branch instruction, outputting a branch signal, and the instruction S112. Is a branch instruction, the signal S1 indicating the branch destination address in the conditional branch instruction.
11 and a signal S1 indicating a branch condition in the branch instruction.
And 15 are output. The signals S111 and S115 are
It is also treated as a branch signal indicating that the instruction is a branch instruction. Furthermore, the first decoding unit 101 determines whether or not the instruction is an instruction for changing a condition code (for example, a zero flag), that is, a condition generation instruction. Condition generation instruction S1
The 12 instruction addresses S113 are output to the condition generation instruction address holding unit 102, which will be described later, and the undetermined signal S115 is output to the condition determination determining unit 103.

The condition decision determining unit 103 receives the signal S115 indicating the branch condition input from the first decoding unit 101,
Condition code S11 acquired from the condition code holding unit 106
9 is used to generate prefetch address information to be output to the prefetch address generation unit 100.

The instruction buffer 104 includes the first decoding unit 1
The signal S116 indicating the content of the instruction acquired by the decoding processing of 01 is temporarily stored for the subsequent processing.
The second decoding unit 105 uses the temporarily stored signal S116.
Is fetched from the instruction buffer 104, is sequentially decoded, and a signal for controlling the arithmetic processing in the arithmetic execution unit described later is output according to the obtained result. The condition code holding unit 106 holds a condition code such as a branch condition used for the determination in a process involving the determination such as the conditional branch process. The operation executing unit 107 includes the second decoding unit 10
An operation is executed in accordance with a control signal input from No. 5, and a condition code holding unit 106 described later is executed according to the result of the operation.
When there is a change in the condition code held by, the condition code holding unit 106 outputs a signal indicating the result.

The condition generation instruction address holding unit 102 functions as a first instruction address holding unit which holds the address of the condition generation instruction, and the instruction address S11.
Holds 3. The program counter 108 is a register that holds the address of the instruction that is being executed in the processor that uses the instruction prefetch device, and functions as a second instruction address holding unit that holds the instruction address that is being executed by the operation execution unit 107. . Comparator 10
9 compares the instruction address S117 acquired from the condition generation instruction address holding unit 102 with the address held in the program counter 108, and if they match, outputs a signal indicating the match. The condition generation instruction address holding unit 102, the program counter 108, and the comparator 109 determine whether or not the condition for determining the branch in the branch instruction has been decided, and if so, output the condition decision signal S118. Condition determination signal generating means 12
Functions as 0.

Further, although not shown in FIG. 1, the instruction prefetch device according to the first embodiment is provided with a branch predictor similar to the device according to the prior art, and the condition decision signal S118 is used to determine the condition decision. When the address is not input to the unit 103, the branch prediction is performed by using the branch prediction unit, and the address is prefetched by the prefetch address generation unit 10.
It is input to 0.

The outline of the operation of the instruction prefetch device according to the first embodiment having the above-described structure will be described below. At a certain timing, the prefetch address generation unit 100 generates the address of the instruction to be fetched next, and the prefetch address signal S11 is generated.
It is output as 0. In the processor using the instruction prefetch device, an instruction is fetched by using the prefetch address signal S110, and the instruction S1 is fetched.
12 is input to the instruction prefetch device. At the next timing, the prefetched instruction S112 is
It is input to the decoding unit 101 and decoded.

In the first decoding section 101, the instruction S112
Is a conditional branch instruction and whether it is a condition generation instruction. When the instruction S112 is a conditional branch instruction, the first decoding unit 101 outputs a signal S111 indicating a branch destination address in the conditional branch instruction to the prefetch address unit 100, and at the same time, indicates a branch condition in the branch instruction. The signal S115 is output to the condition confirmation determination unit 103. As the signal indicating the branch destination address, here, a signal S11 indicating the address difference between the branch destination address and the address of the instruction prefetched previously.
1 is to be output. If the instruction S112 is a condition generation instruction, a signal S113 indicating the instruction address of the instruction S112 is output to the condition generation instruction address holding unit 102, and an unconfirmed signal S115 is output to the condition determination determination means 103. . As for the determination as to whether or not a condition generation command, for example, an instruction for adding, subtraction, multiplication and division is used as a condition generation command, and whether or not it is a condition generation command is determined in advance according to the type of the command.
Can be judged when is input. Also, the command S
Whether signal 112 is a conditional branch instruction, a conditional generation instruction, or neither a conditional branch instruction nor a conditional generation instruction, a signal S116 indicating the content of the instruction S112 is output to the instruction buffer 104. .

The signal S116 indicating the content of the instruction temporarily stored in the instruction buffer 104 is taken out by the second decoding unit 105 and subjected to a decoding process to interpret the content of the instruction. The second decoding unit 105 outputs an instruction according to the content of the interpreted instruction to the arithmetic execution unit 107, and the arithmetic execution unit 107 executes arithmetic processing based on the input instruction. The result of the arithmetic processing is processed in the processor including the instruction prefetch device, and when the result of the arithmetic processing affects the condition code, it is output to the condition code holding unit 106 and held therein. .

On the other hand, in the condition determination signal generating means 120, the condition generating instruction address holding unit 102 is instructed by the instruction S11.
When the second address S113 is input, the address and the address obtained from the program counter 108 are input to the comparator 109 and compared. As described above, the program counter 108 stores the address of the instruction being executed in the processing of the processor including the instruction prefetch device. Therefore, the target condition generating instruction is executed by the comparison processing. You can know whether it is a thing or not. If it has been executed, the condition determined by the execution result of this command S112 is determined to have been determined, so the condition determination signal S118 indicating that the condition has been determined is output to the condition determination determination unit 103.

The condition confirmation determination unit 103 inputs whether or not the condition determination signal S118 is input from the condition determination signal generation means 120, and an undetermined signal or a signal S115 as a signal indicating a branch condition from the first decoding unit. The operation differs depending on whether or not it is performed. First, the undetermined signal S115
When is input, a reset process is executed in the condition confirmation determination unit 103, and the set state is reset by using the condition confirmation signal S118 based on the condition generation instruction processed immediately before.

A signal S115 indicating a branching condition is input to the condition decision determining unit 103, and the condition decision signal S
When 118 is input, the condition code is acquired from the condition code holding unit 106 and is output to the prefetch address unit 100 as the prefetch address information S114. On the other hand, when the signal S115 indicating the branch condition is input but the condition determination signal S118 is not input, the condition determination determination unit 103 does not operate and the branch prediction unit (not shown) operates as described above. The prediction is input to the prefetch address generation unit 100 and used.

In the prefetch address generator 100,
A prefetch address signal S110 is generated and output using the input prefetch address information. FIG. 2 is a diagram for explaining the operation of the prefetch address generation unit 100 and shows a main part of the internal configuration. As shown, the prefetch address generator 10
0 is provided with a selector 151, an address counter 152, and an adder 153.

The selector 151 has a condition decision determining section 103.
Either the signal S111 or the fixed length (in this case, the value “4”) is selected in accordance with the prefetch address information S114 input from the adder 153.
Output to. The signal S111 is input as a signal indicating a branch destination address in the conditional branch instruction prefetched as described above, and is used as a relative value of the address difference. On the other hand, the fixed length fixedly determines the difference between the addresses, and if the fixed length is determined to be, for example, 4 bytes, the value “4” is used as shown in the figure.

The address counter 152 holds the address generated in the immediately preceding prefetch address generating process. When the selected signal is output from the selector 151 to the adder 153, the adder 153 performs addition processing on the selected signal and the value held in the address counter 152, and the result of this addition is It is output as a prefetch address signal S110 which is a device output of the instruction prefetch device. At the same time, the prefetch address signal S110 is also output to the address counter 152 and held for use in the next address generation process.

As a result of the above operation, the prefetch address generator 100 compares the address of the previously prefetched instruction held in the address counter 152 with
In the adder 153, the address difference (relative value) transmitted by the signal S111 is added, and the obtained branch destination address becomes the prefetch address signal S110, or a fixed length "4" is added and the next 4-byte destination is added. Either the address of the instruction becomes the prefetch address signal S110.

Then, as in the case of the prior art device,
The operation when executing the program shown in FIG.
A description will be given according to the timing chart of FIG. At the timing t1 shown in the chart of FIG. 3, the address of the instruction 400 is generated in the prefetch address generation unit 100 and output as the prefetch address signal S110. In the processor using the instruction prefetch device, the instruction 400 is fetched using this prefetch address signal S110 and input to the instruction prefetch device. At the next timing t2, the prefetched instruction 400 is input to the first decoding unit 101,
It is decoded.

Since the instruction 400 is not a conditional branch instruction,
The signal S111 indicating the branch address and the signal S115 indicating the branch condition are not output. On the other hand, since the instruction 400 is an instruction for changing the condition code (zero flag) and is determined to be a condition generation instruction, the address of the instruction 400 is output to and stored in the condition generation instruction address holding unit 102, and The code unconfirmed signal S115 is input to the condition confirmation judgment unit 103.

Also, a signal S11 indicating the content of the instruction 400
6 is output to the instruction buffer 104. The second decoding unit 105 interprets that the instruction 400 is an addition instruction by fetching the instruction 400 from the instruction buffer 104 and performing a decoding process, and transmits the result of the decoding process to the operation executing unit 107 by outputting a signal. The calculation execution unit 107
The addition process executed by the instruction 400 is executed, and the result of the addition process may affect the condition code.
The result of the addition processing is output to the condition code holding unit 106, and the condition code holding unit 106 holds the changed condition code. At timing t3 in FIG. 3, the condition flag is settled.

By executing the instruction 400, which is a condition generation instruction, in the processing of the condition confirmation signal generation means 120,
Since the condition confirmation signal S118 will be output, the condition confirmation determination unit 103 to which the condition confirmation signal S118 is input.
Acquires the condition code S119 from the condition code holding unit 106.

At timing t4, the instruction 401, which is a conditional branch instruction, is decoded in the first decoding unit 101. Since the instruction 401 is a branch instruction, the signal S115 indicating the branch condition is sent to the condition determination determination unit 10
3 is output. In the condition confirmation determination unit 103, the signal S1
According to the input of 15, the correct address (the address of the instruction 403) as the instruction address to be executed next to the conditional branch instruction 401 based on the acquired condition code S119.
To the prefetch address generation unit 100. As a result, the instruction 403 is prefetched based on the prefetch address generated at the timing t5.

Comparing FIG. 3 which is a timing chart diagram with FIG. 9 which is a timing chart diagram when a device according to the prior art is used, the address of the instruction 403 which is the instruction to be fetched correctly at the timing t7 in FIG. 3 is output, the chart of FIG. 3 according to the first embodiment shows that the address of the instruction 403 is output at the timing t5. It can be seen that the processing can be performed quickly by using the definite condition for.

FIG. 4 is a diagram for explaining the prefetch process according to the first embodiment in the pipeline process. FIG. 7A shows the case of the conventional technique, and the instruction A
If There is a condition generate instruction, until after the execution of the instruction A in the timing CLn + 2, based on the determined condition indicates that process is not performed to the prefetch of the next instruction. On the other hand, in the case of the first embodiment shown in FIG. 7B, the instruction A at the timing CL + 1
At the time of the decoding process of 1, the instruction A is judged to be a condition generation instruction, and preparation is made to acquire the confirmed condition. The instruction B can be prefetched based on the determined condition.

As described above, according to the instruction prefetch device of the first embodiment of the present invention, the condition determination signal generating means 12
0 and the condition confirmation determination unit 103, and the first decoding unit 1
When 01 decodes the prefetched instruction, it determines not only whether it is a branch instruction but also whether it is a condition generation instruction, and outputs a signal to that effect. When the condition is confirmed, the signal S118 indicating that is input to the condition determination determination unit 103. Therefore, if the condition is already confirmed when the conditional branch instruction is prefetched, branch prediction is not performed. A correct prefetch address is generated, a delay time due to a misprediction in executing a branch instruction is eliminated, and efficient processing can be executed.

Embodiment 2. The instruction prefetch device according to the second embodiment of the present invention is
In the instruction execution process, it is determined whether or not the branch condition is fixed. If the condition is fixed, the instruction corresponding to the condition is prefetched. FIG. 5 is a block diagram showing the configuration of the instruction prefetch device according to the second embodiment. As shown, the instruction prefetch device according to the second embodiment includes a prefetch address generation unit 20.
0, first decoding unit 201, condition determination judging unit 202, instruction buffer 20 3, the second decode section 204 has a configuration which includes a condition code holding unit 206 and the execution unit 205. In comparison with FIG. 1, the instruction prefetch device according to the second embodiment does not include the condition determination signal generating means 120 included in the device according to the first embodiment.

The first decoding unit 201 performs a decoding process on the prefetched instruction S209, obtains information indicating the content of the instruction, and outputs it to the instruction buffer 203. Also, the first decoding unit 201
It judges whether or not the instruction is a branch instruction, and when it is a branch instruction, it functions as a branch determination means for outputting a branch signal. When the instruction S209 is a branch instruction, the conditional branch is executed. The signal S208 indicating the branch destination address in the instruction and the signal S211 indicating the branch condition in the branch instruction are output. Signals S208 and S22
1 is also treated as a branch signal indicating that it is a branch instruction.

The calculation executing section 205 determines the condition confirmation signal S21.
Is intended to function as a condition determination signal generating means for generating 2, upon execution of the instruction, the instruction to which the instruction to change the condition code, i.e., a condition generation instruction, and the condition code is the change , Which affects the conditional branch instruction following the condition generation instruction, when the execution of the instruction is completed, the condition determination signal S2
12 is output to the condition determination determination unit 202.

Therefore, in the program to be processed by the instruction prefetch device according to the second embodiment,
For an instruction satisfying the above conditions, the information indicating that is included in the instruction itself. Such a setting is, for example, in the process of creating an executable program such as compilation, analyzing an instruction and adding information indicating that to a conditional generation instruction that affects a subsequent conditional branch instruction. It can be realized by doing. Therefore, in the second embodiment,
By including that fact in the instruction, the condition determination signal 212 is sent to the condition determination determination unit 202 when the execution of the condition generation instruction is completed.

The prefetch address generating unit 200, the instruction buffer 203, the second decoding unit 204, and the condition code holding unit 206 are the same as those in the device of the first embodiment.
Is the same as 0, 104, 105, and 106, so
The description is omitted.

An outline of the operation of the instruction prefetch device according to the second embodiment having the above-described structure will be described below. At a certain timing, the prefetch address generation unit 200 generates the address of the instruction to be fetched next, and the prefetch address signal S20
It is output as 7. In the processor using the instruction prefetch device, the instruction is fetched by using the prefetch address signal S207, and the instruction S2 is fetched.
09 is input to the instruction prefetch device. At the next timing, the prefetched instruction S209 is
It is input to the decoding unit 201 and subjected to decoding processing.

In the first decoding section 201, the instruction S209
Is a conditional branch instruction. Command S20
If 9 is a conditional branch instruction, the first decoding unit 201
Outputs a signal S208 indicating the branch destination address in the conditional branch instruction to the prefetch address unit 200,
At the same time, the signal S211 indicating the branch condition in the branch instruction is output to the condition determination determination unit 202. Also,
Whether the instruction S209 is a conditional branch instruction or not, a signal indicating the content of the instruction S209 is output to the instruction buffer 104.

The signal indicating the content of the instruction temporarily stored in the instruction buffer 203 is then sent to the second decoding section 20.
The contents of the instruction are interpreted by being fetched by 4 and decoded. Second decoding unit 204
Is the operation execution unit 20 that gives an instruction according to the content of the interpreted instruction.
5, and the arithmetic execution unit 205 executes arithmetic processing based on the input instruction. The result of the arithmetic processing is processed in the processor including the instruction prefetch device, and when the result of the arithmetic processing affects the condition code, it is output to the condition code holding unit 206 and held therein. .

In the instruction prefetch device according to the second embodiment, the operation executing unit 205 outputs the condition confirmation signal S212 to the condition confirmation determining unit 202 with the output of the condition code in the following cases. That is, when the instruction S209 is the condition generation instruction and the condition code obtained as the execution result thereof is used in the subsequent conditional branch instruction, the condition determination signal S212 is output as described above. As a result, in the device according to the second embodiment, the fact that the condition code held in the condition code holding unit 206 can be used when the prefetch address is generated is transmitted to the condition confirmation determination unit 202.

A signal S211 indicating a branching condition is input to the condition determination determination unit 202, and the condition determination signal S
When 212 is input, the condition code is acquired from the condition code holding unit 206 and is output to the prefetch address unit 200 as the prefetch address information S210. On the other hand, when the signal S211 indicating the branch condition is input but the condition confirmation signal S212 is not input, the condition determination determination unit 202 does not operate and the first embodiment
Similarly, the prediction by the branch prediction unit (not shown) is input to the prefetch address generation unit 200 and used. After this, the prefetch address generation unit 200
Is the same as that of the first embodiment, and the prefetch address signal S207 is output as the device output of the instruction prefetch device according to the second embodiment.

Next, the operation when the program shown in FIG. 8 is executed will be described as in the case of the apparatus according to the prior art and the apparatus according to the first embodiment, but the timing is also used in the apparatus according to the second embodiment. Since the relationship between the operation and the operation is the same as that in the first embodiment, the first embodiment
The timing chart in FIG. 3 will be used and will be described below with reference to the timing chart in FIG. At timing t1 shown in the chart of FIG. 3, the address of the instruction 400 is generated in the prefetch address generation unit 200 and output as the prefetch address signal S207. In the processor using the instruction prefetch device, the instruction 400 is fetched by using the prefetch address signal S207 and input to the instruction prefetch device. At the next timing t2, the prefetched instruction 400 is input to the first decoding unit 201 and decoded.

Since the instruction 400 is not a conditional branch instruction,
The signal S208 indicating the branch address and the signal S211 indicating the branch condition are not output.

A signal indicating the content of the instruction 400 is output to the instruction buffer 203. The second decoding unit 204 takes out the instruction 400 from the instruction buffer 203 and decodes it to interpret that the instruction 400 is an addition instruction, and transmits the result of the decoding processing to the operation execution unit 205 by outputting a signal. The instruction 400 is a condition generation instruction, and its execution result is the conditional branch instruction 401 immediately after.
That will affect. This fact is obtained from the information given to the instruction 400 at the time of compilation, and is interpreted by the second decoding unit 204 and then transmitted to the operation executing unit 205.

The arithmetic execution unit 205 executes the addition process indicated by the instruction 400, and the result of the addition process may affect the condition code. Therefore, the result of the addition process is stored in the condition code holding unit 206. Then, the condition code holding unit 206 holds the changed condition code. At timing t3 in FIG. 3, the condition flag is settled. And
The operation executing unit 205 in the second embodiment sends the condition confirmation signal S212 to the condition confirmation determining unit 2 based on the information about the instruction 400 transmitted from the second decoding unit 204.
Output to 02. The condition confirmation determination unit 202, to which the condition confirmation signal S212 is input, acquires the condition code S213 from the condition code holding unit 206.

At timing t4, the instruction 401, which is a conditional branch instruction, is decoded in the first decoding unit 201. Since the instruction 401 is a branch instruction, the signal S211 indicating the branch condition is the condition determination determination unit 20.
2 is output. In the condition confirmation determination unit 202, the signal S2
According to the input of 11, the correct address (address of the instruction 403) as the instruction address to be executed next to the conditional branch instruction 401 based on the acquired condition code S213.
To the prefetch address generation unit 200. As a result, the instruction 403 is prefetched based on the prefetch address generated at the timing t5.

As described above, according to the instruction prefetch device of the second embodiment, regarding the condition generation instruction which affects the subsequent conditional branch instruction, the instruction itself has the fact as information, and the instruction concerned. At the time of execution, since the operation execution unit 205 is supposed to generate the condition confirmation signal,
Similar to the first embodiment, if the condition is already established when the conditional branch instruction is prefetched, the correct prefetch address is generated without performing the branch prediction, and the delay time at the time of executing the branch instruction due to the misprediction is predicted. It becomes possible to execute efficient processing.

In the second embodiment, it is necessary to perform the above-mentioned processing at the time of compiling the program, and a program corresponding to the device of the second embodiment, which has been subjected to such processing, must be used. With the execution of the arithmetic processing, it is possible to confirm the condition confirmation and generate the condition confirmation signal, and in the instruction prefetch device, it is possible to simplify the configuration of the device and the processing.

[0076]

According to the instruction prefetch device of the first aspect, in a computer that executes an instruction, the instruction prefetch device prefetches from a storage device that stores the instruction, and the prefetched instruction commands a branch. If the branch instruction is a branch instruction, a branch determination unit that outputs a branch signal and a condition that determines a branch in the branch instruction when the branch signal is output are determined. Whether or not it has been decided, and when it has been decided, the definite condition information corresponding to the condition is outputted to a prefetch address generating means which will be described later, and a predetermined branch prediction. According to the method, when the definite condition information is input from the branch predicting unit that generates information designating a branch destination instruction and the definite condition information generating unit, the definite condition Based on the distribution, and generates an address to be prefetched, when not inputting the confirmation condition information, and a prefetch address generating means for generating an address to be prefetched based on information the branch prediction unit is generated, the The confirmation condition information generating means is
The conditions that determine the branch in the above branch instruction have been determined.
Condition confirmation signal if it is confirmed.
Condition determination signal generating means for outputting
When is output, obtain the confirmed conditions and
Generate the fixed condition information based on the acquired conditions
The above-mentioned condition confirmation message shall be provided.
The signal generating means outputs the address output from the branch determining means.
The first instruction address holding means for holding the
A second holding the address of the instruction being executed in
Of the first instruction address holding means
Held by the holding means and the second instruction address holding means.
Address comparison processing is performed.
If it is determined that the above condition determination signal is
It has a comparison means for outputting to the determination confirmation means.
Therefore, in prefetching an instruction following a branch instruction, if the condition is fixed, the address of the instruction corresponding to the fixed condition is generated, and if not fixed, the address of the instruction is determined according to a predetermined prediction method. Will generate
Not only can the delay due to branch misprediction be reduced, the efficiency of processing that utilizes equipment resources can be improved, but the conditions are also fixed.
By transmitting whether or not it is done in the condition confirmation signal,
Generate a prefetch address corresponding to the confirmed conditions.
To reduce the delay due to branch misprediction,
It is possible to improve the efficiency of processing by utilizing
The address of the instruction that determines the condition is used to determine whether it has been determined.
Execution by comparing the address with the address of the executing instruction
By doing so, it is possible to judge whether or not the condition is fixed, and
Processing that utilizes equipment resources by reducing delays due to measurement errors
The efficiency of can be improved.

According to the instruction prefetch device of claim 2, in the device of claim 1, the branch determining means is
Judge whether the prefetched instruction is a condition generation instruction
However, if it is a condition generation instruction, the condition generation instruction
Output the dress to the first instruction address holding means
In addition, the condition confirmation
Outputs a definite signal and outputs the branch signal
As the information indicating the branch condition in the branch instruction,
While outputting to the condition confirmation determination means,
Information indicating the branch destination address in the branch instruction is
It is output to the refetch address generation means.
To execute the judgment processing for the condition generation instruction and
By holding the reply, the condition can be determined by comparing the addresses.
If the condition is confirmed, it will make a judgment about
For example, it is possible to reduce the delay due to a branch misprediction by using this condition and improve the efficiency of the processing that utilizes the device resources.

According to the instruction prefetch device of claim 3, in the device of claim 2, the condition confirmation determining means.
Is the branch instruction when the condition confirmation signal is input.
Next address or the branch destination address above should be used
Condition confirmation information indicating that the above prefetch address is generated
It is output to the means and corresponds to the fixed condition
Since the address of the executed instruction is generated, the delay due to the branch prediction error can be reduced, and the efficiency of the processing utilizing the device resources can be improved.

According to the instruction prefetch device of the fourth aspect, the instruction judging means for judging whether or not the prefetched first instruction is the conditional branch instruction, and the condition generating instruction immediately before the first instruction. means for storing the addresses, the stored address, and comparing means for comparing the address of the instruction being executed, in a case where the first instruction is determined to conditional branch instruction, a Te to the comparison means Since the prefetch address generating means for outputting the prefetch address from the determined condition is provided when the match of the address is detected , the condition generating instruction is executed depending on whether or not the branch condition is determined. If the condition is confirmed, the prefetch address of the instruction based on the condition can be generated, and the branch instruction execution delay due to the branch misprediction is eliminated. Succoth is possible.

According to the instruction prefetch method of the fifth aspect, the instruction determining step of determining whether the prefetched first instruction is a conditional branch instruction, and the condition generating instruction immediately before the first instruction a step of storing the addresses, the stored address, a comparison step of comparing the address of the instruction being executed, in a case where the first instruction is determined to conditional branch instruction, a Te on the comparison step If a match of the address is detected, the prefetch address generation step of outputting the prefetch address based on the determined condition is included. Therefore, it is determined whether the branch condition is determined by executing the condition generation instruction. When the condition is confirmed, the prefetch address of the instruction based on the condition can be generated and the delay in executing the branch instruction due to the branch misprediction is eliminated. It becomes possible.

[0081]

[0082]

[0083]

[0084]

[0085]

[0086]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an instruction prefetch device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a main configuration for explaining a function of a prefetch address generation unit of the same embodiment.

FIG. 3 is a timing chart diagram showing a schematic operation of a process in the same embodiment.

FIG. 4 is a diagram for explaining the flow of processing in the same embodiment in comparison with the case of a conventional technique.

FIG. 5 is a block diagram showing a configuration of an instruction prefetch device according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining processing by a processor of a computer.

FIG. 7 is a block diagram showing a configuration of an instruction prefetch device according to a conventional technique.

FIG. 8 is a diagram showing an example of a program to be processed.

FIG. 9 is a timing chart showing a schematic operation of processing in a conventional technique.

[Explanation of symbols]

100, 200, 300 prefetch address generation unit 101, 201, 303 first decoding unit 102 condition generation instruction address holding unit 103, 202 condition determination determination unit 104, 203, 305 instruction buffer 105, 204, 306 second decoding unit 106, 206, 308 Condition code holding units 107, 205, 307 Operation execution unit 108 Program counter 109 Comparator 120 Condition determination signal generating means

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-161750 (JP, A) JP-A-1-119829 (JP, A) JP-A-4-60720 (JP, A) JP-A-61- 208130 (JP, A) JP-A-50-128949 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/38

Claims (5)

(57) [Claims] 1. A computer for executing instructions, which is an instruction prefetch device for prefetching from a storage device for storing the instructions, wherein the prefetched instruction is a branch instruction for instructing branching. In the case of a branch instruction, a branch determination unit that outputs a branch signal, and, when the branch signal is output, determines whether or not the condition for determining the branch in the branch instruction is fixed.
If it has been decided, the decision condition information generating means for outputting the decision condition information corresponding to the condition to the prefetch address generating means described later and the instruction of the branch destination according to the predetermined branch prediction method are specified. When the definite condition information is input from the branch predicting unit that generates information and the definite condition information generating unit, an address to be prefetched is generated based on the definite condition information, and the definite condition information is not input. And a prefetch address generating means for generating an address to be prefetched based on the information generated by the branch predicting means, wherein the definite condition information generating means determines the condition for determining the branch in the branch instruction. Whether or not there is a condition-determining signal generating means for outputting a condition-determining signal, and the condition-determining device And a condition confirmation determination means for acquiring the confirmed condition and generating the confirmed condition information based on the acquired condition. First instruction address holding means for holding the address of the instruction output from the judging means, second instruction address holding means for holding the address of the instruction currently being executed, and the first instruction address holding Means for comparing the addresses held by the means and the second instruction address holding means, and when it is determined that they match in the comparison, the comparison means for outputting the condition determination signal to the condition determination determining means. An instruction prefetch device, comprising: 2. The instruction prefetch device according to claim 1, wherein the branch determination means determines whether or not the prefetched instruction is a condition generation instruction, and if it is a condition generation instruction, the condition is fetched. The address of the generated instruction is output to the first instruction address holding means, and at the same time, a condition undetermined signal is output to the condition determination determination means. The branch signal to be output is the branch instruction. information indicating the branch condition of, and outputs to said condition determination judging means, information indicating a branch destination address in the branch instruction, and outputs to said prefetch address generating means, and characterized in that Instruction prefetching device. 3. The instruction prefetch device according to claim 2, wherein the condition decision determining means should use the next address of the branch instruction or the branch destination address when the condition decision signal is input. and outputs to said prefetch address generating means the condition determination information indicating the instruction prefetch and wherein the. 4. An instruction determination means for determining whether or not the prefetched first instruction is a conditional branch instruction, a means for storing an address of a condition generation instruction immediately before the first instruction, and stored. and address comparison means for comparing the address of the instruction being executed, in a case where the first instruction is determined to conditional branch instruction, if a match of addresses is detected Te in the comparison means , and a prefetch address generating means for outputting a prefetch address from established criteria, instruction prefetching apparatus characterized by. 5. An instruction determination step of determining whether the prefetched first instruction is a conditional branch instruction, a step of storing an address of a condition generation instruction immediately before the first instruction, address, a comparison step of comparing the address of the instruction being executed, in a case where the first instruction is determined to conditional branch instruction, if a match of addresses Te in the comparing step is detected , instruction prefetching method and a prefetch address generating step, and wherein the outputs of the prefetch address from established criteria.