JPH0756190A - Thin-film transistor and its production - Google Patents
Thin-film transistor and its productionInfo
- Publication number
- JPH0756190A JPH0756190A JP20086293A JP20086293A JPH0756190A JP H0756190 A JPH0756190 A JP H0756190A JP 20086293 A JP20086293 A JP 20086293A JP 20086293 A JP20086293 A JP 20086293A JP H0756190 A JPH0756190 A JP H0756190A
- Authority
- JP
- Japan
- Prior art keywords
- interlayer insulating
- insulating film
- thin film
- film transistor
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アクティブマトリック
ス液晶表示装置に用いられる薄膜トランジスタおよびそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used in an active matrix liquid crystal display device and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】薄膜トランジスタを用いたアクティブマ
トリックス型液晶表示装置は、近年ますます高精細化が
進行している。高精細で良好な表示品質の液晶表示装置
を得るためには、薄膜トランジスタの微細化と同時に薄
膜トランジスタのソース配線、ゲート配線を埋め込むこ
とが有効である。配線を埋め込むために有機薄膜を用い
た例としては、有機薄膜にポリイミド膜を用いた例とし
て反射型アクティブマトリックス液晶表示装置において
は、特開昭５７ー２０７７９や特公平１ー３５３５１な
どがある。また透過型アクティブマトリックス液晶表示
装置においては、特開平２ー２０７２２２がある。有機
薄膜としてポリイミド膜を用いる理由は、ポリイミド膜
の比誘電率が小さく、また厚く形成することが容易であ
るため、アクティブマトリックス液晶表示装置の層間絶
縁膜として好適であるからである。また反応性イオンエ
ッチング（ＲＩＥ）などを用いてポリイミド膜に微細な
コンタクトホールを形成することが可能であるが、ポリ
イミド膜の膜厚が厚くなるとコンタクトホールのアスペ
クト比が大きくなり、良好なコンタクトを得ることが困
難になる。また高精細な液晶表示装置を達成するには、
配線を埋め込むだけでなく、画素電極の微細化も必要と
なるが、ポリイミド膜上の画素電極の微細加工をＲＩＥ
で行うには、ポリイミド膜へのダメージが問題となる。2. Description of the Related Art In recent years, the definition of active matrix type liquid crystal display devices using thin film transistors has become higher and higher. In order to obtain a liquid crystal display device having high definition and good display quality, it is effective to embed the source wiring and the gate wiring of the thin film transistor at the same time as miniaturizing the thin film transistor. As an example of using an organic thin film for embedding a wiring, there are JP-A-57-20779 and Japanese Patent Publication No. 1-35351 in a reflection type active matrix liquid crystal display device as an example of using a polyimide film as an organic thin film. Further, regarding a transmission type active matrix liquid crystal display device, there is JP-A-2-207222. The reason why the polyimide film is used as the organic thin film is that the polyimide film is suitable as an interlayer insulating film of an active matrix liquid crystal display device because it has a small relative permittivity and can be easily formed to be thick. Further, it is possible to form a fine contact hole in the polyimide film by using reactive ion etching (RIE) or the like. However, as the film thickness of the polyimide film becomes thicker, the aspect ratio of the contact hole becomes larger and a good contact is obtained. Hard to get. To achieve a high-definition liquid crystal display device,
In addition to embedding the wiring, it is necessary to miniaturize the pixel electrode, but the fine processing of the pixel electrode on the polyimide film is performed by RIE.
However, damage to the polyimide film poses a problem.
【０００３】[0003]
【発明が解決しようとする課題】アクティブマトリック
ス液晶表示装置に用いられる薄膜トランジスタにおい
て、層間絶縁膜にポリイミドを用いた場合に問題となる
ポリイミド膜に形成される微細なコンタクトホールの形
状を改善し、良好なコンタクト特性を得ると同時にポリ
イミド膜上の画素電極をＲＩＥなどにより微細加工でき
る構造と製造方法を考案する。In a thin film transistor used for an active matrix liquid crystal display device, it is possible to improve the shape of a fine contact hole formed in a polyimide film, which is a problem when polyimide is used for an interlayer insulating film, and We devise a structure and manufacturing method that can obtain fine contact characteristics and at the same time finely process the pixel electrode on the polyimide film by RIE or the like.
【０００４】[0004]
【課題を解決するための手段】絶縁基板ないしは絶縁膜
上に多結晶シリコン層が形成されパターンニングされる
工程と、次に前記の多結晶シリコン層の上部にゲート絶
縁膜が形成される工程と、次にゲート電極が形成される
工程と、前記のゲート電極上に第一の層間絶縁膜が形成
される工程と、次に薄膜トランジスタのソース・ドレイ
ン部にコンタクトホールを開口する工程と、次にソース
配線を形成する工程と、次に前記のソース配線の上部に
第二および第三の層間絶縁膜が形成される工程と、次に
前記の第三の層間絶縁膜を等方的にエッチングし、第二
の層間絶縁膜を異方的にエッチングして薄膜トランジス
タのドレイン部にコンタクトホールを開口する工程と、
次に薄膜トランジスタのドレイン部に画素電極が形成さ
れることを特徴とする。SOLUTION: A polycrystalline silicon layer is formed on an insulating substrate or an insulating film and patterned, and a gate insulating film is formed on the polycrystalline silicon layer. , A step of forming a gate electrode, a step of forming a first interlayer insulating film on the gate electrode, a step of forming contact holes in the source / drain portions of the thin film transistor, A step of forming a source wiring, a step of forming second and third interlayer insulating films on the source wiring, and a step of isotropically etching the third interlayer insulating film. A step of anisotropically etching the second interlayer insulating film to open a contact hole in the drain portion of the thin film transistor,
Next, a pixel electrode is formed in the drain portion of the thin film transistor.
【０００５】[0005]
【実施例】以下に、本発明の一実施例を図１、図２およ
び図３を用いて説明する。図１は本発明の薄膜トランジ
スタおよびその製造方法の一実施例の平面図である。図
１において、ゲート配線１およびソース配線２、画素電
極３は各々異なる平面に形成されており、画素電極３
は、ゲート配線１およびソース配線２と部分的に重なっ
ている。図２は図１におけるＡ−Ａ´部の断面を示した
図である。薄膜トランジスタのチャネルとなる多結晶シ
リコン膜４、ソース・ドレイン領域５、ゲート絶縁膜
６、ゲート絶縁膜上に形成されたゲート電極７、前記の
ゲート電極７上にシリコン酸化膜やシリコン窒化膜で形
成された第一の層間絶縁膜８、第一の層間絶縁膜８およ
びゲート絶縁膜６にＲＩＥを用いて形成された微細なコ
ンタクトホール９、Ａｌなどの金属を用いて形成された
ソース電極１０、第二の層間絶縁膜であるポリイミド膜
１１、シリコン酸化膜やシリコン窒化膜、酸化タンタル
などを用いて形成された第三の層間絶縁膜１２、ＲＩＥ
を用いて第二の層間絶縁膜１１および第三の層間絶縁膜
１２に開口された微細なコンタクトホール１３、インジ
ウム錫酸化物（ＩＴＯ）１４などで形成された画素電極
を示す。次に本発明の薄膜トランジスタおよびその製造
方法の一実施例を図３（ａ）から（ｄ）の工程図を用い
て説明する。先ず図３（ａ）に示すようにガラスや石英
などの透明な絶縁基板に多結晶シリコン膜４を５００Å
から１０００Å程度の厚さで堆積し、パターンニングす
る。前記の絶縁基板の純度が低く、重金属などが多結晶
シリコン膜に拡散する危険性がある場合には、多結晶シ
リコン膜４を堆積する前にシリコン酸化膜を絶縁基板上
に堆積すればよい。次にシリコン酸化膜を１２００Åの
厚さで堆積しゲート絶縁膜６を形成するか、あるいは前
記の多結晶シリコン膜４を熱酸化させてゲート絶縁膜を
形成する。次にゲート電極７を形成し、イオン注入法を
用いてソース・ドレイン領域５を形成する。前記ゲート
電極としては、燐を含む多結晶シリコンや、Ｃｒ、Ｔ
ａ、Ａｌなどの金属、ＭｏＳｉ2などの珪化物などが用
いられる。また前記ゲート電極の膜厚は特に限定され
ず、薄膜トランジスタのソース・ドレイン領域５に打ち
込まれる不純物イオンを阻止する為に十分な厚さであれ
ばよい。例えば、前記ゲート電極に多結晶シリコンを用
いた場合の膜厚は、３５００Å以上あれば、１００ｋｅ
Ｖで打ち込まれる燐イオンを十分阻止できる。次に図３
（ｂ）に示すように、シリコン酸化膜を５０００Åの厚
さで堆積し第一の層間絶縁膜８を形成する。ソース・ド
レイン領域にＲＩＥを用いて異方性のエッチング条件で
２×２μｍサイズの微細なコンタクトホール９を開口し
た後、Ａｌにてソース電極配線１０を行なう。前記の異
方性のエッチング条件の一例として、エッチングガスに
ＣＨＦ3を用い、ガス流量２０ｓｃｃｍ、反応圧力１０
Ｐａ、ｒｆ出力１ｋＷの条件を用いることができる。次
に図３（ｃ）に示すように第二の層間絶縁膜としてポリ
イミド膜１１を硬化後の膜厚で１μｍとなるようにスピ
ンコーターを用いて塗布し、３００℃で熱硬化させる。
ポリイミド膜は、液晶表示装置用に充分な透光性や耐薬
品性を保証できるものであれば、特に限定されない。次
にシリコン酸化膜を２０００Åの厚さでプラズマＣＶＤ
法やスパッタ等を用いて堆積し第三の層間絶縁膜１２を
形成する。前記のシリコン酸化膜はポリイミドの耐熱性
を考慮して、３００℃以下で形成することが好ましい。
また、前記のシリコン酸化膜以外には、シリコン窒化膜
や酸化タンタルを用いることが可能である。次にレジス
トをマスクとして、第三の層間絶縁膜１２にコンタクト
を開ける。前記の第三の層間絶縁膜１２のコンタクトエ
ッチングは、ＲＩＥなどを用いた場合にコンタクトにテ
ーパーがつく等方性のエッチング条件を用いるか、ＨＦ
を用いてのウェットエッチングを行う。次に図３（ｄ）
に示すように、第三の層間絶縁膜１２をマスクとして、
前記のポリイミド膜１１をＲＩＥを用いて異方性エッチ
ング条件でエッチングを行い、コンタクト１３を開口す
る。前記のポリイミド膜１１のエッチング条件の一例と
しては、エッチングガスにＯ2を用い、ガス流量２０ｓ
ｃｃｍ、反応圧力１３Ｐａ、ｒｆ出力１ｋＷの条件をも
ちいることができる。前記のポリイミド膜１１のエッチ
ングにおいて、第一の層間絶縁膜のコンタクトホール９
のエッジ部がイオン衝撃効果により面取りされるため、
コンタクト形状は更に改善される。最後にインジウム錫
酸化物（ＩＴＯ）１４を１６００Åの厚さとなるように
スパッタ法で堆積し、ＲＩＥを用いてパターンニングす
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3. FIG. 1 is a plan view of an embodiment of a thin film transistor and a method of manufacturing the same according to the present invention. In FIG. 1, the gate wiring 1, the source wiring 2, and the pixel electrode 3 are formed on different planes.
Partially overlap with the gate wiring 1 and the source wiring 2. FIG. 2 is a view showing a cross section taken along the line AA ′ in FIG. A polycrystalline silicon film 4 serving as a channel of a thin film transistor, a source / drain region 5, a gate insulating film 6, a gate electrode 7 formed on the gate insulating film, and a silicon oxide film or a silicon nitride film formed on the gate electrode 7. The formed first interlayer insulating film 8, the first interlayer insulating film 8 and the gate insulating film 6 with the fine contact holes 9 formed by RIE, the source electrode 10 formed by using a metal such as Al, A polyimide film 11 which is a second interlayer insulating film, a third interlayer insulating film 12 formed using a silicon oxide film, a silicon nitride film, tantalum oxide, or the like, RIE
A pixel electrode formed of a fine contact hole 13 opened in the second interlayer insulating film 11 and the third interlayer insulating film 12, an indium tin oxide (ITO) 14, etc. is shown. Next, one embodiment of the thin film transistor and the manufacturing method thereof according to the present invention will be described with reference to the process diagrams of FIGS. First, as shown in FIG. 3 (a), a polycrystalline silicon film 4 is applied to a transparent insulating substrate such as glass or quartz with a thickness of 500 Å.
To a thickness of about 1000Å and patterning. If the purity of the insulating substrate is low and there is a risk that heavy metals or the like will diffuse into the polycrystalline silicon film, a silicon oxide film may be deposited on the insulating substrate before depositing the polycrystalline silicon film 4. Next, a silicon oxide film is deposited to a thickness of 1200 Å to form the gate insulating film 6, or the polycrystalline silicon film 4 is thermally oxidized to form the gate insulating film. Next, the gate electrode 7 is formed, and the source / drain regions 5 are formed by using the ion implantation method. As the gate electrode, polycrystalline silicon containing phosphorus, Cr, T
Metals such as a and Al, silicides such as MoSi 2 and the like are used. The thickness of the gate electrode is not particularly limited as long as it is sufficient to prevent impurity ions implanted in the source / drain regions 5 of the thin film transistor. For example, when polycrystalline silicon is used for the gate electrode, the film thickness is 100 ke if it is 3500 Å or more.
Phosphorus ions driven by V can be sufficiently blocked. Next in FIG.
As shown in (b), a silicon oxide film is deposited to a thickness of 5000Å to form a first interlayer insulating film 8. After the fine contact holes 9 of 2 × 2 μm size are formed in the source / drain regions under anisotropic etching conditions by using RIE, the source electrode wiring 10 is made of Al. As an example of the anisotropic etching conditions, CHF 3 is used as the etching gas, the gas flow rate is 20 sccm, and the reaction pressure is 10
The conditions of Pa and rf output of 1 kW can be used. Next, as shown in FIG. 3C, a polyimide film 11 is applied as a second interlayer insulating film by using a spin coater so that the film thickness after curing becomes 1 μm, and is thermally cured at 300 ° C.
The polyimide film is not particularly limited as long as it can ensure sufficient translucency and chemical resistance for a liquid crystal display device. Next, plasma-enhance the silicon oxide film to a thickness of 2000Å
A third interlayer insulating film 12 is formed by depositing using a method or sputtering. The silicon oxide film is preferably formed at 300 ° C. or lower in consideration of heat resistance of polyimide.
Besides the silicon oxide film, a silicon nitride film or tantalum oxide can be used. Next, using the resist as a mask, a contact is opened in the third interlayer insulating film 12. For the contact etching of the third interlayer insulating film 12, the isotropic etching condition in which the contact is tapered when RIE or the like is used, or HF is used.
Wet etching is performed. Next, FIG. 3 (d)
As shown in, the third interlayer insulating film 12 is used as a mask,
The polyimide film 11 is etched using RIE under anisotropic etching conditions to open the contact 13. As an example of the etching conditions for the polyimide film 11, O 2 is used as an etching gas and a gas flow rate is 20 s.
Ccm, reaction pressure 13 Pa, rf output 1 kW can be used. In the etching of the polyimide film 11, the contact hole 9 of the first interlayer insulating film
Since the edge part of is chamfered by the ion impact effect,
The contact shape is further improved. Finally, indium tin oxide (ITO) 14 is deposited by a sputtering method so as to have a thickness of 1600Å, and patterned by using RIE.
【０００６】[0006]
【発明の効果】本発明により、以下の効果がある。The present invention has the following effects.
【０００７】（１）．ポリイミド膜に形成された微細な
コンタクトホールの形状が改善され、良好なコンタクト
特性を得ることが可能になった。(1). The shape of the fine contact hole formed in the polyimide film was improved, and it became possible to obtain good contact characteristics.
【０００８】（２）．ポリイミド膜上に形成された画素
電極をＲＩＥを用いて微細加工することが容易になり、
高精細な液晶表示装置が実現可能となった。(2). It becomes easy to finely process the pixel electrode formed on the polyimide film by using RIE,
A high-definition liquid crystal display device has become possible.
【図１】 本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図２】 図１におけるＡ−Ａ´部の断面を示す断面
図である。FIG. 2 is a cross-sectional view showing a cross section taken along the line AA ′ in FIG.
【図３】 本発明の一実施例を示す工程図である。FIG. 3 is a process drawing showing an example of the present invention.
１．ゲート配線 ２．ソース配線 ３．画素電極 ４．多結晶シリコン膜 ５．ソース・ドレイン領域 ６．ゲート絶縁膜 ７．ゲート電極 ８．第一の層間絶縁膜 ９．コンタクトホール １０．ソース電極配線 １１．ポリイミド膜 １２．第三の層間絶縁膜 １３．コンタクトホール １４．インジウム錫酸化物 1. Gate wiring 2. Source wiring 3. Pixel electrode 4. Polycrystalline silicon film 5. Source / drain region 6. Gate insulating film 7. Gate electrode 8. First interlayer insulating film 9. Contact hole 10. Source electrode wiring 11. Polyimide film 12. Third interlayer insulating film 13. Contact hole 14. Indium tin oxide
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/336 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/336
Claims (4)
用いられる薄膜トランジスタにおいて、前記の薄膜トラ
ンジスタのゲート配線の上部に第一の層間絶縁膜を介し
てソース配線が形成され、前記のソース配線の上部に第
二の層間絶縁膜が形成され、前記の第二の層間絶縁膜の
上部に第三の層間絶縁膜が形成され、前記の第三の層間
絶縁膜の上部に画素電極が形成されており、前記の第三
の層間絶縁膜が等方的にエッチングされ、第二の層間絶
縁膜が異方的にエッチングされたコンタクトホールを用
いて前記の画素電極と薄膜トランジスタのドレイン部の
コンタクトが為されていることを特徴とする薄膜トラン
ジスタおよびその製造方法。1. In a thin film transistor used in an active matrix liquid crystal display device, a source wiring is formed on a gate wiring of the thin film transistor via a first interlayer insulating film, and a second wiring is formed on the source wiring. An interlayer insulating film is formed, a third interlayer insulating film is formed on the second interlayer insulating film, and a pixel electrode is formed on the third interlayer insulating film. The third interlayer insulating film is isotropically etched, and the second interlayer insulating film is anisotropically etched using the contact hole to make contact between the pixel electrode and the drain portion of the thin film transistor. Characteristic thin film transistor and manufacturing method thereof.
り、前記の第三の層間絶縁膜が無機薄膜であることを特
徴とする請求項１に記載の薄膜トランジスタおよびその
製造方法。2. The thin film transistor according to claim 1, wherein the second interlayer insulating film is an organic thin film, and the third interlayer insulating film is an inorganic thin film.
用いられる薄膜トランジスタにおいて、絶縁基板ないし
は絶縁膜上に多結晶シリコン層が形成されパターンニン
グされる工程と、次に前記の多結晶シリコン層の上部に
ゲート絶縁膜が形成される工程と、次にゲート電極が形
成される工程と、前記のゲート電極上に第一の層間絶縁
膜が形成される工程と、次に薄膜トランジスタのソース
・ドレイン部に反応性イオンエッチングを用いて微細な
コンタクトホールを開口する工程と、次にソース配線を
形成する工程と、次に前記のソース配線の上部に第二お
よび第三の層間絶縁膜が形成される工程と、次に前記の
第三の層間絶縁膜を等方的にエッチングし、第二の層間
絶縁膜を異方的にエッチングして薄膜トランジスタのド
レイン部にコンタクトホールを開口する工程と、次に薄
膜トランジスタのドレイン部に画素電極が堆積され、反
応性イオンエッチングを用いてパターンニングすること
を特徴とする薄膜トランジスタおよびその製造方法。3. In a thin film transistor used in an active matrix liquid crystal display device, a step of forming and patterning a polycrystalline silicon layer on an insulating substrate or an insulating film, and then gate insulating on the polycrystalline silicon layer. A step of forming a film, a step of forming a gate electrode next, a step of forming a first interlayer insulating film on the gate electrode, and then a reactive ion in the source / drain portion of the thin film transistor. A step of forming a fine contact hole by etching, a step of forming a source wiring next, a step of forming second and third interlayer insulating films on the source wiring, Isotropically etched on the third interlayer insulating film, and anisotropically etched on the second interlayer insulating film to contact the drain portion of the thin film transistor. A thin film transistor and a method of manufacturing the thin film transistor, characterized in that a step of opening a through hole is performed, and then a pixel electrode is deposited on a drain portion of the thin film transistor and patterned by using reactive ion etching.
り、前記の第三の層間絶縁膜が無機薄膜であることを特
徴とする請求項３に記載の薄膜トランジスタおよびその
製造方法。4. The thin film transistor according to claim 3, wherein the second interlayer insulating film is an organic thin film, and the third interlayer insulating film is an inorganic thin film.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20086293A JP3309509B2 (en) | 1993-08-12 | 1993-08-12 | Active matrix display device using thin film transistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20086293A JP3309509B2 (en) | 1993-08-12 | 1993-08-12 | Active matrix display device using thin film transistor and method of manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| JPH0756190A true JPH0756190A (en) | 1995-03-03 |
| JP3309509B2 JP3309509B2 (en) | 2002-07-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP20086293A Expired - Lifetime JP3309509B2 (en) | 1993-08-12 | 1993-08-12 | Active matrix display device using thin film transistor and method of manufacturing the same |
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