JP2004056099A - Silicon nitride film, semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for forming a dense insulating film of high quality suitably applicable as a gate insulating film or a protective film, at a temperature below the deformation point on a glass substrate and to apply a semiconductor device for realizing high reliability with high performance using the technique. <P>SOLUTION: In this semiconductor device, a silicon nitride film having characteristics of an etching rate of 10 nm/min or less to a mixed aqueous solution containing hydrogen of 1×10<SP>21</SP>/cm<SP>3</SP>or lower for the concentration, oxygen of 5×10<SP>18</SP>-5×10<SP>21</SP>/cm<SP>3</SP>for the concentration, ammonium hydrogen fluoride (NH<SB>4</SB>HF<SB>2</SB>) of 7.13% and ammonium fluoride (NH<SB>4</SB>F) of 15.4% is formed in a gate insulating film of a field effect transistor, having a channel length of 0.32-2.5 μm on a crystalline semiconductor film via a silicon oxide film. <P>COPYRIGHT: (C)2004,JPO

Description

【００４０】
また、比較例として、従来のプラズマＣＶＤ法により形成される窒化珪素膜の膜形成条件を表２に示す。
【００４１】
【表２】

【００４２】
次に、表１の成膜条件で形成された窒化珪素膜と、表２の条件で形成された窒化珪素膜の代表的な特性値について比較した結果を表３に示す。尚、試料において「ＲＦＳＰ−ＳｉＮ（Ｎｏ．１）」と「ＲＦＳＰ−ＳｉＮ（Ｎｏ．２）」との違いはスパッタリング装置による違いであり、本発明における窒化珪素膜としての機能を損なうものでははい。また、内部応力は、圧縮応力と引っ張り応力とで数値の正負が変わるが、ここではその絶対値のみを取り扱う。
【００４３】
【表３】

【００４４】
表３に示すように、上述の高周波マグネトロンスパッタリング法で作製された「ＲＦＳＰ−ＳｉＮ（Ｎｏ．１）」と「ＲＦＳＰ−ＳｉＮ（Ｎｏ．２）」の試料のプラズマＣＶＤ法で作製された比較例の試料に対する特徴的な違いは、フッ化水素アンモニウム（ＮＨ_４ＨＦ_２）を７．１３％とフッ化アンモニウム（ＮＨ_４Ｆ）を１５．４％含む混合水溶液の２０℃（ＬＡＬ５００　ＳＡバッファードフッ酸；橋本化成株式会社製）におけるエッチング速度が非常に遅く、水素の含有量が極めて少ない点にある。また、内部応力は、プラズマＣＶＤ法で形成された窒化珪素膜よりも絶対値で比較して小さい値となっている。
【００４５】
当該窒化珪素膜における水素、酸素、炭素の不純物濃度は二次イオン質量分析（ＳＩＭＳ）により調べたものであり、その深さ方向分析の結果を図３に示す。試料は単結晶珪素基板上に表１に従う条件で形成された窒化珪素膜であり、水素濃度が１×１０^２１／ｃｍ^３以下であることが判明している。窒化珪素膜における水素結合の有無はフーリエ変換赤外分光分析（ＦＴ−ＩＲ）によっても調べ、その結果をプラズマＣＶＤ法で作製された窒化珪素膜の特性との比較で図５に示す。ＦＴ−ＩＲの分析によってもＳｉ−Ｈ結合、Ｎ−Ｈ結合による吸収ピークは観測されていない。
【００４６】
また、分光光度計で測定した透過率を図４に示し、比較参照のため同図には表２で示す条件によりプラズマＣＶＤ法で作製した窒化珪素膜の特性についても示している。両者には顕著な違いは見られず、どちらも透明度の良い膜であることが分かる。
【００４７】
上記、特性値は代表的な結果を示すものであり、種々の実験結果から本発明に係る高周波マグネトロンスパッタリング法で作製された窒化珪素膜の主要な特性値は以下の通りである。
【００４８】
本発明に係る窒化珪素膜は種々検討した結果、次に示す特性の少なくとも一つを満たすものである。即ち、フッ化水素アンモニウム（ＮＨ_４ＨＦ_２）を７．１３％とフッ化アンモニウム（ＮＨ_４Ｆ）を１５．４％含む混合水溶液（２０℃）におけるエッチング速度が１０ｎｍ／ｍｉｎ以下（好ましくは３．５ｎｍ／ｍｉｎ以下）、水素濃度が１×１０^２１／ｃｍ^３以下（好ましくは５×１０^２０／ｃｍ^３以下）、酸素濃度が５×１０^１８〜５×１０^２１／ｃｍ^３（好ましくは１×１０^１９〜１×１０^２１／ｃｍ^３）であることのいずれか一つ、好ましくは複数の要件を同時に満たすものである。また、内部応力の絶対値は２×１０^１０ｄｙｎ／ｃｍ^２以下、好ましくは５×１０^９ｄｙｎ／ｃｍ^２以下、さらに好ましくは５×１０^８ｄｙｎ／ｃｍ^２以下とする。内部応力を小さくすれば他の被膜と積層させた場合において、界面における欠陥準位の発生を抑えることができ、また剥離などの問題が生じることはない。
【００４９】
さらに、上記特性を有する本発明の窒化珪素膜は、ＮａやＬｉに代表される周期律表１族及び２族の元素に対するブロッキング効果が極めて高く、これらの可動イオンの拡散を抑制することができる。この事実を端的に示すデータを図１、図２、図６に示す。図６は表２の条件でプラズマＣＶＤ法により膜形成した窒化珪素膜を誘電体としたＭＯＳ構造のバイアス−熱ストレス（Ｂ−Ｔストレス）試験の結果前後におけるＣ−Ｖ特性の変化を示すグラフである。試料の構造は単結晶珪素基板（ｎ型、１〜１０Ωｃｍ）に１００ｎｍの窒化珪素膜を表２の条件で形成し、その上にＡｌにＬｉを添加（０．２〜１．５重量％）した金属を電極（直径１ｍｍ）としたものである。この試料の構造においてＡｌ電極にＬｉを添加することにより、Ｌｉ拡散の有無を調べることができる。Ｂ−Ｔストレス試験の条件は、１．７ＭＶの電圧を印加して１５０℃にて１時間保持する条件下にて行った。図６によれば、ＢＴストレス試験によりＣ−Ｖ特性が大きくシフトし、窒化珪素膜上に形成したＡｌにＬｉを添加した電極からＬｉが拡散している影響が顕著に確認することができる。
【００５０】
図１と図２は、表１の条件で作製した窒化珪素膜を誘電体膜としたＭＯＳ構造の試料におけるＢ−Ｔストレス試験前後におけるＣ−Ｖ特性を示している。図１の試料は窒化珪素膜上の電極をＡｌ−Ｓｉ（珪素を添加したＡｌ）で形成したものであり、図２はＡｌ−Ｌｉで電極を形成した試料である。但し、試料は単結晶珪素基板（ｐ型、１〜１０Ωｃｍ）の表面に５０ｎｍの酸化膜を形成してあり、これは窒化珪素膜と珪素基板との界面準位の影響を低減する目的で形成したものである。従って、窒化珪素膜のＬｉに対するブロッキング性に何ら影響を与えるものではない。
【００５１】
図１と図２の特性を比較すると、両グラフともにＢ−Ｔストレス試験前後におけるＣ−Ｖ特性の変化に殆ど差がなく、Ｌｉの拡散による影響が表れていないこと、即ち、表１の膜形成条件で作製した窒化珪素膜が効果的にブロッキング膜として機能することが確認できる。このように、本発明に係る窒化珪素膜は３００℃以下の温度で形成されているにもかかわらず、非常に緻密でありＮａやＬｉといった可動イオンに対するブロッキング効果が高いことを確認することができる。
【００５２】
以上におけるＢ−Ｔストレス試験などで確認される、非常に緻密な窒化珪素膜は従来のスパッタリング現象による物理的な膜形成機構とは異なり、ターゲット表面及び被膜堆積表面において窒素又は窒素と希ガスイオンと珪素とが相互に反応して膜形成に関与していると考えられる。
【００５３】
その膜形成機構の一考察例を図９の模式図により説明する。ターゲット９０１に高周波電力の印加によりグロー放電プラズマ９００が形成されると、窒素又は窒素と希ガスとは様々なイオン種、励起種、発光種が形成される。その中で化学的に極めて活性な性質を持つ活性窒素が生成される。活性窒素はきわめて反応性が強く比較的低温でも容易に窒化物を形成することが知られている。つまり、ターゲット表面に拡散した活性窒素は、珪素と反応して窒化物を形成する。窒化珪素は安定であるが、ターゲット表面に希ガスイオン又は窒素イオンがシース電界で加速されて入射すると、スパッタリングされ気相中に放出される。グロー放電プラズマ９００中を拡散する珪素の窒化物は、その過程で活性窒素や他の窒素の励起種と反応し、一部は基板表面に達する。そこで珪素の窒化物は表面反応して窒化珪素が形成される。表面反応においてもプラズマ電位と接地電位との電位差により加速されて入射するイオン種の援助が作用していると考えられる。このような膜形成機構により、窒化珪素膜中に珪素のクラスターが含まれず、それが膜の緻密さを向上させていることが推測される。
【００５４】
このような膜形成機構は、供給する窒素よりも希ガスの割合を高めてしまうと、希ガスイオンによるスパッタリングが支配的となり実現することはできない。理想的には、窒素ガスのみとすれば良いが、膜形成速度が著しく低下するので、窒素と希ガスとの混合比が最大で１対１となる範囲内で選択することが好ましい。
【００５５】
上記窒化珪素膜及び製造装置を用いた半導体装置の態様について、以下に図面を用いて詳細に説明する。
【００５６】
（実施の形態１）
本実施の形態において適用することのできる基板には、バリウムホウケイ酸ガラス、アルミノホウケイ酸ガラス、アルミノシリケートガラスなどを素材とするガラス基板が適している。代表的には、コーニング社製の１７３７ガラス基板（歪み点６６７℃）、旭硝子社製のＡＮ１００（歪み点６７０℃）などが適用可能であるが、勿論他の同様な基板であれば特段の限定はない。いずれにしても、本発明においては歪み点７００℃以下のガラス基板が適用可能である。本実施例では、歪み点７００℃以下のガラス基板上に高周波マグネトロンスパッタリング法により作製された窒化珪素膜を用いてマイクロプロセッサ（Ｍｉｃｒｏ　Ｐｒｏｃｅｓｓｏｒ　Ｕｎｉｔ：ＭＰＵ）を形成する一形態について説明する。
【００５７】
尚、本発明において、歪み点が７００℃以上である基板を除外するものではない。勿論、耐熱温度が１０００℃以上である合成石英基板を適用しても良い。本発明に係る窒化珪素膜は７００℃以下の温度で緻密でブロキング性の高い膜が形成でき、その特徴において特段合成石英基板を選択する必要はない。
【００５８】
上記基板を選択して図１０（Ａ）に示すように、ガラス基板２００上に酸化珪素膜、窒化珪素膜または酸化窒化珪素膜（ＳｉＯ_ｘＮ_ｙ）等の絶縁膜から成る第１無機絶縁体層２０１を形成する。代表的な一例は２層構造を有し、ＳｉＨ_４、ＮＨ_３、及びＮ_２Ｏを反応ガスとしてプラズマＣＶＤにより膜形成される第１酸化窒化珪素膜２０２を５０ｎｍ、ＳｉＨ_４、及びＮ_２Ｏを反応ガスとしてプラズマＣＶＤにより膜形成される第２酸化窒化珪素膜２０３を１００ｎｍの厚さに積層形成する構造である。ここで、第１酸化窒化珪素膜２０２を高周波マグネトロンスパッタリング法で形成する窒化珪素膜と置き換えても良い。当該窒化珪素膜はＮａなどガラス基板に微量に含まれるアルカリ金属元素が拡散するのを防ぐことができる。
【００５９】
ＴＦＴの活性層とする結晶性半導体膜は、第１無機絶縁体層２０１上に形成した非晶質珪素膜２０４を結晶化して得る。また、非晶質珪素膜に換えて、非晶質シリコンゲルマニウム（Ｓｉ_１−ｘＧｅ_ｘ；ｘ＝０．００１〜０．０５）膜を適用しても良い。最初に形成する非晶質珪素膜の厚さは出来上がりの結晶性珪素膜の厚さが２０ｎｍ乃至６０ｎｍとなる範囲で選択される。この膜厚さの上限はＴＦＴのチャネル形成領域において完全空乏型として動作させるための上限値であり、この膜厚の下限値はプロセス上の制約であり、結晶性珪素膜のエッチング工程において選択加工する場合に必要な最小値として決めている。
【００６０】
結晶化の工程において、その方法は特に限定はない。例えば結晶化法の一例として、ニッケルなどの半導体の結晶化に対し触媒作用のある金属元素を添加して結晶化させても良い。この場合、ニッケルを含有する層２０５を非晶質珪素膜２０４上に保持させた後、脱水素化（５００℃、１時間）、続けて５５０℃、４時間の加熱処理により結晶化させる。
【００６１】
図１０（Ｂ）は結晶性珪素膜２０６が形成された状態を示している。この状態で５０〜９５％の割合で結晶化した結晶性珪素膜が得られるが、図１０（Ｃ）で示すように、更に結晶性を向上させるためパルス発振のエキシマレーザー又は、ＹＡＧレーザー、ＹＶＯ_４レーザー、ＹＬＦレーザーなど固体レーザーの第２高調波を照射するレーザーアニール処理を加える。レーザーアニール処理では当該レーザー光を光学系にて短手方向の幅４００μｍの線状レーザー光として、９０〜９８％のオーバーラップ率を持って照射する。このパルスレーザー光の照射により、図１０（Ｃ）に示すように表面に最大値として、膜厚と同程度の高さの凸部が多数形成される。
【００６２】
この結晶性珪素膜の上にゲート絶縁膜を形成してトップゲート型のＴＦＴを形成すると、ゲートリーク電流が増加する。また、ゲート電極にバイアス電圧を印加するストレス試験によっても特性が劣化する。これは、凸部に電界が集中するためであると考えられる。よって、結晶性珪素膜の表面の凹凸形状の最大値を１０ｎｍ以下好ましくは５ｎｍ以下にすることが望ましい。
【００６３】
表面の凹凸を低減するには、オゾン水含有水溶液による酸化処理と、フッ酸含有水溶液による酸化膜除去処理を１回、好ましくは複数回繰り返すことで実現することができる。本実施の形態では、チャネル長０．３５〜２．５μｍのＴＦＴを作製するために、ゲート絶縁膜の実質的な厚さを３０〜８０ｎｍとするために、結晶性珪素膜の表面の平滑性に関し、凹凸形状の最大値を１０ｎｍ以下好ましくは５ｎｍ以下にする（図１０（Ｄ））。
【００６４】
その後、得られた結晶性珪素膜をフォトマスクを用いて写真蝕刻法により所望の形状にエッチング処理し、ＴＦＴにおいてチャネル形成領域、ソース及びドレイン領域、低濃度不純物領域などを含む活性層を形成する半導体膜２１６〜２１８を形成する（図１２（Ａ））。
【００６５】
図１０（Ｄ）の状態で形成された結晶性珪素膜をエッチングするには、ドライエッチング法を用いてＣＦ_４とＯ_２の混合ガスをエッチングガスとして用い、ゲート絶縁膜の被覆性を良くするために、半導体膜２１６〜２１８の端部に３０〜６０度のテーパー角が付くように加工する。その詳細は図１７に示されている。下地との選択比との関係で、酸化窒化珪素膜も僅かにエッチングされるが、そのザグリの深さは半導体膜の厚さｄの１／３以下となるようにする。ザグリが深い場合、ゲート絶縁膜が被覆せず、その上層に形成するゲート配線が断線する不良が発生する。また、半導体膜２１６〜２１８に対し、しきい値（Ｖｔｈ）を制御するためにｐ型を付与する不純物元素を添加してもよい。半導体に対してｐ型を付与する不純物元素には、ボロン（Ｂ）、アルミニウム（Ａｌ）、ガリウム（Ｇａ）など周期律第１３族元素が対象となる。
【００６６】
次いで、図１２（Ｂ）で示すように、半導体膜２１６〜２１８上にゲート絶縁膜を形成する酸化珪素膜２１９、窒化珪素膜２２０を高周波マグネトロンスパッタリング法で形成し、ゲート電極を形成する第１導電膜２２１、第２導電膜２２２の４層を大気に触れさせることなく減圧下にて連続的に形成する。
【００６７】
図７で説明したマルチタスク型マグネトロンスパッタリング装置はこの工程に適した構成となっている。このゲート絶縁膜〜ゲート電極を形成するまでの工程は概略以下の通りである。
【００６８】
まず、ロード／アンロード室１１１から搬送される基板は図１２（Ａ）の状態となっている。前述の表面の平滑化処理は、スピナーを備えた前処理室１１２で行うことが可能でありオゾン水含有水溶液による酸化処理と、フッ酸含有水溶液による酸化膜除去処理を行い、半導体膜の表面を凸部を中心にエッチングする。また、この処理により半導体膜の最表面がエッチングされて水素で終端された清浄で不活性な表面が形成されるという特徴もある。
【００６９】
その後、基板は中間室１０８を経て真空排気された第１共通室１０１に搬送される。加熱処理室１０３には加熱手段１２０が備えられ、基板に吸着している水分を離脱させ清浄化させる。膜形成室１０４では高周波マグネトロンスパッタリング法により合成石英をターゲットとして酸化珪素膜を１０〜６０ｎｍの厚さで形成する。主な膜形成条件は、スパッタガスＯ_２、スパッタリング時の圧力０．４Ｐａ、放電電力１１．０ｍＷ／ｃｍ^２、１３．５６ＭＨｚ、基板加熱温度２００℃とする。この条件により半導体膜と界面準位密度が低く、緻密な酸化珪素膜２１９を形成することができる。次いで、基板を膜形成室１０５に移して高周波マグネトロンスパッタリング法にて窒化珪素膜を１０〜３０ｎｍの厚さで形成する。この膜形成条件は表１と同じである。酸化珪素の比誘電率３．８に対し窒化珪素の比誘電率は約７．５であるので、酸化珪素膜で形成するゲート絶縁膜に窒化珪素膜を含ませることで、実質的にはゲート絶縁膜の薄膜化を図るのと同等の効果を得ることができる。
【００７０】
即ち、結晶性珪素膜の表面の平滑性に関し、凹凸形状の最大値を１０ｎｍ以下好ましくは５ｎｍ以下とし、ゲート絶縁膜において酸化珪素膜と窒化珪素膜の２層構造とすることで、当該ゲート絶縁膜の全厚さを３０〜８０ｎｍとしてもゲートリーク電流を低減させ、２．５〜１０Ｖ、代表的には３．０〜５．５ＶでＴＦＴを駆動させることができる。
【００７１】
また、ゲート絶縁膜とゲート電極界面の汚染物もＴＦＴの特性ばらつきの原因となるので、ゲート絶縁膜を形成した後、続けて膜厚１０〜５０ｎｍの窒化タンタル（ＴａＮ）から成る第１導電膜２２１と、膜厚１００〜４００ｎｍのタングステン（Ｗ）から成る第２導電膜２２２とを積層形成する。ゲート電極を形成するための導電性材料としてはＴａ、Ｗ、Ｔｉ、Ｍｏ、Ａｌ、Ｃｕから選ばれた元素、または当該元素を主成分とする合金材料もしくは化合物材料で形成する。また、リン等の不純物元素をドーピングした多結晶珪素膜に代表される半導体膜を用いてもよい。また、第１導電膜をタンタル（Ｔａ）膜で形成し、第２導電膜をＷ膜とする組み合わせ、第１導電膜を窒化タンタル（ＴａＮ）膜で形成し、第２導電膜をＡｌ膜とする組み合わせ、第１導電膜を窒化タンタル（ＴａＮ）膜で形成し、第２導電膜をＣｕ膜とする組み合わせとしてもよい。
【００７２】
次に、図１２（Ｃ）に示すように、写真蝕刻法によりゲート電極パターンが形成されるレジストマスク２２３を形成する。その後、ドライエッチング法により第１エッチング処理を行う。エッチングには例えばＩＣＰ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ：誘導結合型プラズマ）エッチング法が適用される。エッチング用ガスに限定はないが、ＷやＴａＮのエッチングにはＣＦ_４とＣｌ_２とＯ_２とを用いると良い。第１エッチング処理では、基板側には所定のバイアス電圧を印加して、形成される第１形状のゲート電極パターン２２４の側面に１５〜５０度の傾斜角を持たせる。エッチング条件にもよるが、第１エッチング処理によりゲート絶縁膜として形成された窒化珪素膜２２０は、第１形状のゲート電極パターン２２４の下部において残存し、酸化珪素膜２１９が露出する。この後、第２エッチング条件に変え、エッチング用ガスにＳＦ_６とＣｌ_２とＯ_２とを用い、基板側に印加するバイアス電圧を所定の値として、Ｗ膜の異方性エッチングを行う。こうして、ゲート電極２２４、２２５を形成する。その後、レジストマスク２２３は除去する。
【００７３】
ゲート電極は第１導電膜２２１と第２導電膜２２２との積層構造体であり、第１導電膜が庇のように突出した構造を有している。その後、図１２（Ａ）で示すようにドーピング処理を行い、各半導体膜に不純物領域を形成する。ドーピング条件は適宜設定すれば良い。半導体膜２１６に形成される第１ｎ型不純物領域２２７は低濃度ドレインを形成し、第２ｎ型不純物領域２２８はソース又はドレイン領域を形成する。半導体膜２１７に形成される第１ｐ型不純物領域２３０は低濃度ドレインを形成し、第２ｐ型不純物領域２３１はソース又はドレイン領域を形成する。それぞれの半導体膜におけるチャネル形成領域２２６、２２９は低濃度ドレイン領域の間に位置する。半導体膜２１８は容量部を形成するための部材であり第２ｎ型不純物領域と同じ濃度で不純物が添加される。
【００７４】
そして、図１６（Ａ）に示すように水素を含有する酸化窒化珪素膜２７４をプラズマＣＶＤ法により５０ｎｍの厚さで形成し、３５０〜５５０℃の加熱処理により半導体膜の水素化を行う。この加熱処理には図２０及び図２１で示すＲＴＡ熱処理装置を用いる。また、水素化と共に上述の不純物領域の活性化処理を同時に行うこともできる。
【００７５】
層間絶縁膜２７５はアクリル又はポリイミドなどを主成分とする感光性の有機樹脂材料で所定のパターンに形成する。その後、保護膜２７６を高周波マグネトロンスパッタリング法により窒化珪素膜で形成する。膜厚は２０〜５００ｎｍとすれば、酸素や空気中の水分をはじめ各種イオン性の不純物の侵入を阻止するブロッキング作用を得ることができる。そして、ドライエッチングによりコンタクトホール２７７を形成する（図１６（Ｂ））。
【００７６】
その後、図１６（Ｃ）で示すように、Ａｌ、Ｔｉ、Ｍｏ、Ｗなどを用いて配線２７８ａ〜２７８ｄ、２７９を形成する。配線構造の一例は、膜厚５０〜２５０ｎｍのＴｉ膜と、膜厚３００〜５００ｎｍの合金膜（ＡｌとＴｉとの合金膜）との積層膜を用いる。
【００７７】
こうして、ｎチャネル型ＴＦＴ３０３、ｐチャネル型ＴＦＴ３０４、容量部３０５を形成することができる。各ＴＦＴにおいてはゲート絶縁膜に少なくとも１層の窒化珪素膜が含まれている。また、容量部３０５において、誘電体膜として少なくとも一層の窒化珪素膜（２７６）が含まれている。当該窒化珪素膜は、フッ化水素アンモニウム（ＮＨ_４ＨＦ_２）を７．１３％とフッ化アンモニウム（ＮＨ_４Ｆ）を１５．４％含む混合水溶液に対するエッチング速度が１０ｎｍ／ｍｉｎ以下であるなどの本発明の特徴を有している。
【００７８】
（実施の形態２）
実施の形態１において、図１０（Ｂ）で示す結晶性珪素膜が得られた後に、図１１で示すように、連続発振型の固体レーザーとして、ＹＡＧレーザー、ＹＶＯ_４レーザー、ＹＬＦレーザーを用いることができる。ＹＡＧレーザー、ＹＶＯ_４レーザー、ＹＬＦレーザーの第２高調波を照射する。例えば、ＹＶＯ_４レーザーの第２高調波（５３２ｎｍ）を線状に集光して、１〜１００ｃｍ／ｓｅｃの速度で走査させ結晶性の向上を図る。この工程で連続発振レーザーを用いることで、表面が平滑な結晶性珪素膜を得ることができ、表面の凹凸形状の最大値を１０ｎｍ以下好ましくは５ｎｍ以下にすることができる。
【００７９】
（実施の形態３）
本実施の形態は、ゲート電極の構造が異なり、より微細化に適した半導体装置の構成について図面を参照して説明する。勿論、この半導体装置の各部位においても本発明に係る窒化珪素膜が適用される。
【００８０】
図１３（Ａ）において、半導体膜２１６〜２１８は実施の形態１と同様にして形成する。ゲート絶縁膜２４０は、１０〜８０ｎｍの厚さで高周波マグネトロンスパッタリング法で作製される窒化珪素膜が適用されるが、半導体膜との界面にはスパッタリング又は酸素プラズマ処理により形成される１〜５ｎｍの厚さの酸化珪素膜を介在させておく。このことにより、窒化珪素と半導体膜とが直接接触して界面準位密度が増加するのを防ぎ、また、膜形成時のダメージを低減することができる。
【００８１】
ゲート電極２４３、２４４及び容量電極２４５は、実施の形態１と同様に膜厚１０〜５０ｎｍの窒化タンタル（ＴａＮ）から成る第１導電膜２４１と、膜厚１００〜４００ｎｍのタングステン（Ｗ）から成る第２導電膜２４２とで形成する。
【００８２】
その後、図１３（Ｂ）に示すように、ドーピング処理により第１ｎ型不純物領域２４６、２４８、第１ｐ型不純物領域２４７を形成する。これらの不純物領域は、第２導電膜２４２をマスクとして第１導電膜２４１と重畳するように形成している。
【００８３】
図１３（Ｃ）では、ゲート電極の側壁スペーサ２４９〜２５１を酸化珪素膜で形成している。全面にプラズマＣＶＤ法で酸化珪素膜を形成し、異方性ドライエッチングでこの膜を全面にわたって均一にエッチングして側壁スペーサを形成する。ゲート電極をマスクとして第２ｎ型不純物領域２５２、２５４、第２ｐ型不純物領域２５３を形成する。
【００８４】
そして、図１４（Ａ）に示すように水素を含有する酸化窒化珪素膜２５６をプラズマＣＶＤ法により５０ｎｍの厚さで形成する。さらに、高周波マグネトロンスパッタリング法により作製される窒化珪素膜２５７を形成する。その後、４１０℃の加熱処理により水素化を行うが、窒化珪素膜２５７により当該水素が気相中に放散されるのを防ぎ水素化の効果を高めることができる。また、窒化珪素膜２５７に置き換えて酸化窒化アルミニウム（ＡｌＮｘＯｙ：Ｘ＝２．５〜４７．５原子％）を適用しても良い。酸化窒化アルミニウムは窒化珪素膜と同様な効果に加え、熱伝導性が高いことから、ＴＦＴの発熱を放散させる効果が得られる。即ち、素子を微細化して集積度を向上させることによる発熱の影響を低減することができる。
【００８５】
層間絶縁膜２５８はプラズマＣＶＤ法で作製される酸化珪素膜、常圧ＣＶＤ法で作製されるリンガラス（ＰＳＧ）、あるいはボロンガラス（ＢＳＧ）、もしくはリンボロンガラス（ＰＢＳＧ）で形成可能であるが、最も好ましくはポリイミド、アクリルなど感光性有機樹脂材料により被膜の形成と同時にコンタクト部の開口を形成する。
【００８６】
そして、配線２５９をＡｌ、Ｔｉ、Ｍｏ、Ｗなどを用いて形成する。この配線２５９と層間絶縁膜２５８を被覆する形で高周波マグネトロンスパッタリング法により窒化珪素膜２６０を２０〜１００ｎｍの厚さに形成する。これは、この上層にＣｕ配線を形成するに際し、Ｃｕの拡散を防ぐバリア膜とするものである。
【００８７】
そして、酸化珪素膜又は有機樹脂材料を用いて０．５〜５μｍの厚さで第２層間絶縁膜２６１を形成する。第２層間絶縁膜２６１に配線を形成するための開溝を形成し、その後全面にスパッタ法で窒化タンタル膜から成るバリア層２６２を１００〜２００ｎｍの厚さで形成する。窒化タンタル膜はＣｕの拡散を防ぐバリア層として用いる。さらにスパッタ法でＣｕ膜を成膜してシード層を形成し、硫酸銅を用いたメッキ法によりＣｕ層２６３を１〜１０μｍの厚さで形成する。メッキ法以外でも、Ｃｕ層をスパッタ法で形成し、４５０℃の熱処理でリフローさせて平坦化を実現することもできる（図１４（Ｃ））。
【００８８】
Ｃｕ層２６３をエッチング加工してＣｕ配線２６４を形成する。Ｃｕ配線は酸化しやすく熱的に不安定であるので、このＣｕ配線２６４を被覆する保護膜を高周波マグネトロンスパッタリング法による窒化珪素膜２６５で２０〜２００ｎｍの厚さで形成する。当該窒化珪素膜は緻密であり、Ｃｕの酸化や周辺部位への拡散を防ぐことができる。また、窒化珪素膜２６０と窒化珪素膜２６５とでＣｕ配線２６４を挟み込むことによりＣｕによりＴＦＴが汚染されるのを防ぐことができる。さらに必要があれば第３層間絶縁膜２６６を形成し、図１４（Ｃ）と同様な作業をすれば多層配線を形成し、マイクロプロセッサやメモリーなどの半導体装置を形成することができる。
【００８９】
（実施の形態４）
本実施の形態では、ダマシンによりＣｕ配線を形成する一形態について図１５を用いて説明する。勿論、この半導体装置の各部位においても本発明に係る窒化珪素膜が適用される。
【００９０】
まず、実施の形態３と同様にして図１４（Ｂ）の状態を形成する。即ち、配線２５９の上層に窒化珪素膜２６０を形成する。その後、酸化シリコン膜、又は有機樹脂膜を用いて１〜５μｍの厚さで第２層間絶縁膜２６７を形成する。第２層間絶縁膜２６７上に窒化珪素膜２６８を形成した後、配線を形成するための開溝２６９を形成する（図１５（Ａ））。
【００９１】
さらに第３層間絶縁膜２７０を形成し、概略開口２６９の位置に合わせ、それより開口幅の広い開口２７２を形成する。その後全面にスパッタ法で窒化タンタル膜２７１を１００〜２００ｎｍの厚さで形成する。窒化タンタル膜はＣｕの拡散を防ぐ層となる（図１５（Ｂ））。
【００９２】
さらにスパッタ法でＣｕ膜を成膜し、シード層を形成した後、硫酸銅を用いたメッキ法によりＣｕ層を１〜１０μｍの厚さで形成する。メッキ法以外でもＣｕ層をスパッタ法で形成し、４５０℃の熱処理でリフローさせて平坦化を実現することもできる。
【００９３】
次に、ＣＭＰ（Ｃｈｅｍｉｃａｌ−Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ：化学的・機械的ポリッシング）法を用いてＣｕメッキ層の表面から研磨を始め、第３層間絶縁膜２７０が露出するまで研磨を行い、図１５（Ｃ）に示すように表面を平坦化する。こうしてＣｕ配線２７３が形成される。ＣＭＰのスラリーは砥粒と酸化剤と添加剤から成り、砥粒にはアルミナかシリカを用いる。酸化剤には硝酸鉄、過酸化水素、過ヨウ素酸カリウム等を用いる。こうしてバリア層２７１、Ｃｕ層２７３から成る配線が形成される。この上層に窒化珪素膜２７４を形成して保護膜としても良い。窒化珪素膜２６０、窒化珪素膜２６８、窒化珪素膜２７４とでＣｕ配線２６３を挟み込むことによりＣｕによりＴＦＴが汚染されるのを防ぐことができる。
【００９４】
（実施の形態５）
本実施の形態は、ガラス基板と比較してより平坦性の高い合成石英基板を用いて、より微細化に適した半導体装置の構成について図２２と図２３を参照して説明する。勿論、この半導体装置の各部位においても本発明に係る窒化珪素膜が適用される。
【００９５】
石英基板２００上に結晶性珪素膜を形成する。結晶性珪素膜は６００〜９００℃の加熱処理により非晶質珪素膜を結晶化して形成されたもの、又は非晶質珪素膜にＮｉなど珪素の結晶化の触媒となる元素を添加して５００〜７００℃で結晶化させたものを適用することができる。後者の場合には、結晶性珪素膜が得られた後に、ハロゲンを含む酸化性雰囲気中で８５０〜１０５０℃、好ましくは９５０℃にて１〜１２時間の加熱処理を行って、触媒となる元素をゲッタリングにより除去しておくと良い。
【００９６】
その後、図２２（Ａ）において示すように、当該結晶性珪素膜より、島状に分割した半導体膜２１６〜２１８を形成する。さらに、図７及び図２０で説明したＰＰＴＡ法を用いて、半導体膜２１６〜２１８の表面に熱酸化処理により１〜５ｎｍの酸化珪素膜２８０を形成する。また、酸素に、ＮＦ_３、ＨＦ、ＣｌＦ_３から選ばれた一種又は複数種を０．０１〜０．１％添加して酸化処理を行い、Ｆを酸化珪素膜中に含ませても良い。
【００９７】
図２２（Ｂ）で示すように、ゲート絶縁膜２４０は、１０〜８０ｎｍの厚さで高周波マグネトロンスパッタリング法で作製される窒化珪素膜が適用されるが、半導体膜との界面には熱酸化処理により形成される１〜５ｎｍの厚さの酸化珪素膜２８０を介在させておく。酸化珪素膜により、窒化珪素と半導体膜とが直接接触して界面準位密度が増加するのを防ぎ、また、膜形成時のダメージを低減することが可能であり、界面準位密度を低減することができる。
【００９８】
また、同様な効果を得る手段として、酸化性の水溶液、代表的にはオゾン水で形成される酸化珪素膜（ケミカルオキサイド）を残存させておいても良い。
【００９９】
ゲート電極２４３、２４４及び容量電極２４５は、実施の形態１と同様に膜厚１０〜５０ｎｍの窒化タンタル（ＴａＮ）から成る第１導電膜２４１と、膜厚１００〜４００ｎｍのタングステン（Ｗ）から成る第２導電膜２４２とで形成する。
【０１００】
その後、図２２（Ｃ）に示すように、ドーピング処理により第１ｎ型不純物領域２４６、２４８、第１ｐ型不純物領域２４７を形成する。これらの不純物領域は、第２導電膜２４２をマスクとして第１導電膜２４１と重畳するように形成している。
【０１０１】
図２２（Ｄ）では、ゲート電極の側壁スペーサ２４９〜２５１を酸化珪素膜で形成している。全面にプラズマＣＶＤ法で酸化珪素膜を形成し、異方性ドライエッチングでこの膜を全面にわたって均一にエッチングして側壁スペーサを形成する。ゲート電極をマスクとして第２ｎ型不純物領域２５２、２５４、第２ｐ型不純物領域２５３を形成する。
【０１０２】
そして、図２３（Ａ）に示すように水素を含有する酸化窒化珪素膜２５６をプラズマＣＶＤ法により５０ｎｍの厚さで形成する。さらに、高周波マグネトロンスパッタリング法により作製される窒化珪素膜２５７を形成する。その後、４１０℃の加熱処理により水素化を行うが、窒化珪素膜２５７により当該水素が気相中に放散されるのを防ぎ水素化の効果を高めることができる。また、窒化珪素膜２５７に置き換えて酸化窒化アルミニウム（ＡｌＮｘＯｙ：Ｘ＝２．５〜４７．５原子％）を適用しても良い。酸化窒化アルミニウムは窒化珪素膜と同様な効果に加え、熱伝導性が高いことから、ＴＦＴの発熱を放散させる効果が得られる。即ち、素子を微細化して集積度を向上させることによる発熱の影響を低減することができる。
【０１０３】
層間絶縁膜２５８はプラズマＣＶＤ法で作製される酸化珪素膜、常圧ＣＶＤ法で作製されるリンガラス（ＰＳＧ）、あるいはボロンガラス（ＢＳＧ）、もしくはリンボロンガラス（ＰＢＳＧ）で形成可能であるが、最も好ましくはポリイミド、アクリルなど感光性有機樹脂材料により被膜の形成と同時にコンタクト部の開口を形成する。
【０１０４】
そして、配線２５９をＡｌ、Ｔｉ、Ｍｏ、Ｗなどを用いて形成する。この配線２５９と層間絶縁膜２５８を被覆する形で高周波マグネトロンスパッタリング法により窒化珪素膜２６０を２０〜１００ｎｍの厚さに形成する。これは、この上層にＣｕ配線を形成するに際し、Ｃｕの拡散を防ぐバリア膜とするものである（図２３（Ｂ））。
【０１０５】
そして、酸化珪素膜又は有機樹脂材料を用いて０．５〜５μｍの厚さで第２層間絶縁膜２６１を形成する。第２層間絶縁膜２６１に配線を形成するための開溝を形成し、その後全面にスパッタ法で窒化タンタル膜から成るバリア層２６２を１００〜２００ｎｍの厚さで形成する。窒化タンタル膜はＣｕの拡散を防ぐバリア層として用いる。さらにスパッタ法でＣｕ膜を成膜してシード層を形成し、硫酸銅を用いたメッキ法によりＣｕ層２６３を１〜１０μｍの厚さで形成する。メッキ法以外でも、Ｃｕ層をスパッタ法で形成し、４５０℃の熱処理でリフローさせて平坦化を実現することもできる（図２３（Ｃ））。
【０１０６】
Ｃｕ層２６３をエッチング加工してＣｕ配線２６４を形成する。Ｃｕ配線は酸化しやすく熱的に不安定であるので、このＣｕ配線２６４を被覆する保護膜を高周波マグネトロンスパッタリング法による窒化珪素膜２６５で２０〜２００ｎｍの厚さで形成する。当該窒化珪素膜は緻密であり、Ｃｕの酸化や周辺部位への拡散を防ぐことができる。また、窒化珪素膜２６０と窒化珪素膜２６５とでＣｕ配線２６４を挟み込むことによりＣｕによりＴＦＴが汚染されるのを防ぐことができる。さらに必要があれば第３層間絶縁膜２６６を形成し、図２３（Ｃ）と同様な作業をすれば多層配線を形成し、マイクロプロセッサやメモリーなどの半導体装置を形成することができる（図２３（Ｄ））。配線層は必要に応じて多層化するることができる。
【０１０７】
（実施の形態６）
実施の形態５に、実施の形態４で示す配線形成工程を組み合わせて半導体装置を完成させても良い。即ち、ダマシン技術によりＣｕ配線を形成することができる。この場合においても、本発明に係る窒化珪素膜が適用される。
【０１０８】
（実施の形態７）
実施の形態１〜６により作製される代表的な半導体装置としてマイクロコンピュータの一実施形態を図１８と図１９を用いて説明する。図１８に示すように、０．３〜１．１ｍｍの厚さのガラス又は石英などの基板上に各種の機能回路部を集積してマイクロコンピュータを実現することができる。各種の機能回路部は実施の形態１〜６により作製されるＴＦＴや容量部を主体として形成することが可能である。
【０１０９】
図１８で示すマイクロコンピュータ２１００の要素としては、ＣＰＵ２１０１、ＲＯＭ２１０２、割り込みコントローラ２１０３、キャッシュメモリー２１０４、ＲＡＭ２１０５、ＤＭＡＣ２１０６、クロック発生回路２１０７、シリアルインターフェース２１０８、電源発生回路２１０９、ＡＤＣ／ＤＡＣ２１１０、タイマカウンタ２１１１、ＷＤＴ２１１２、Ｉ／Ｏポート２１０２などである。
【０１１０】
ガラス基板上に形成されたマイクロコンピュータ２１００は、セラミックやＦＲＰ（繊維強化プラスチック）のベース２２０１にフェースダウンボンディングで固着される。マイクロコンピュータ２１００のガラス基板の裏面には、熱伝導性の良い酸化窒化アルミニウム２２０３が被覆されて熱放散効果を高めている。さらにこれに接してアルミニウムで形成される放熱フィン２２０４が設けられ、マイクロコンピュータ２１００の動作に伴う発熱対策としている。全体は封止樹脂２２０５で覆われ、外部回路との接続はピン２２０２により行う。
【０１１１】
本実施の形態ではマイクロコンピュータの形態を一例として示したが、各種機能回路の構成や組み合わせを換えれば、メディアプロセッサ、グラフィクス用ＬＳＩ、暗号ＬＳＩ、メモリー、グラフィクス用ＬＳＩ、携帯電話用ＬＳＩなど様々な機能の半導体装置を完成させることができる。
【０１１２】
【発明の効果】
本発明により、歪み点７００℃以下のガラス基板上であっても、水素を１×１０^２１／ｃｍ^３以下の濃度で含み、酸素を５×１０^１８〜５×１０^２１／ｃｍ^３の濃度で含み、フッ化水素アンモニウム（ＮＨ_４ＨＦ_２）を７．１３％とフッ化アンモニウム（ＮＨ_４Ｆ）を１５．４％含む混合水溶液に対するエッチング速度が１０ｎｍ／ｍｉｎ以下の特性を有し、Ｌｉの如き可動イオンに対してブロッキング性の高い緻密な窒化珪素膜を得ることができる。
【０１１３】
この窒化珪素膜はゲート絶縁膜や、保護膜、特にＣｕ配線のバリア膜として、半導体装置の各部位に用いることで、高性能で高信頼性を実現する半導体装置を提供することができる。
【０１１４】
このような水素及び酸素含有量、エッチング特性を有することにより、ゲート絶縁膜への適用においては、ゲートリーク電流が低減し、電界効果移動度、サブスレショルド係数、コンダクタンス（ｇｍ）などが良好となり、連続動作におけるトランジスタ特性の経時変化が低減し、製造歩留まりや特性ばらつきを向上させることができる。また、このような効果は、結晶性半導体膜と窒化珪素膜との間に、酸化珪素膜を介在させることによりより有効に発現させることができる。
【図面の簡単な説明】
【図１】本発明に係る窒化珪素膜を用い、ＭＯＳ構造でＬｉの拡散がない場合のＣ−Ｖ特性を示すグラフ。
【図２】本発明に係る窒化珪素膜を用い、ＭＯＳ構造でＬｉの拡散がある場合のＣ−Ｖ特性を示すグラフ。
【図３】本発明の窒化珪素膜に含まれるＨ、Ｃ、Ｏ濃度をＳＩＭＳにより測定した結果を示すグラフ。
【図４】本発明の窒化珪素膜と比較例の窒化珪素膜の透過率を示すグラフ。
【図５】本発明の窒化珪素膜と比較例の窒化珪素膜の赤外吸収スペクトルを示すグラフ。
【図６】プラズマＣＶＤ法により形成された窒化珪素膜を用い、ＭＯＳ構造でＬｉの拡散がある場合のＣ−Ｖ特性を示すグラフ。
【図７】本発明に適用するマグネトロンスパッタリング装置の構成を説明する上面図。
【図８】本発明に適用するマグネトロンスパッタリング装置の膜形成室の詳細を説明する断面図。
【図９】本発明の係る高周波マグネトロンスパッタリングにおける窒化珪素膜の膜形成機構を模式的に説明する図。
【図１０】本発明の半導体装置の作製工程を説明する縦断面図。
【図１１】本発明の半導体装置の作製工程を説明する縦断面図。
【図１２】本発明の半導体装置の作製工程を説明する縦断面図。
【図１３】本発明の半導体装置の作製工程を説明する縦断面図。
【図１４】本発明の半導体装置の作製工程を説明する縦断面図。
【図１５】本発明の半導体装置の作製工程を説明する縦断面図。
【図１６】本発明の半導体装置の作製工程を説明する縦断面図。
【図１７】半導体膜のエッチング形状の詳細を説明する図。
【図１８】本発明によるマイクロコンピュータの構成を説明する図。
【図１９】本発明によるマイクロコンピュータのパッケージ構造を説明する図。
【図２０】加熱処理室の構成を説明する図。
【図２１】光源の点滅と半導体基板の温度変化および冷媒の供給方法を説明する図。
【図２２】本発明の半導体装置の作製工程を説明する縦断面図。
【図２３】本発明の半導体装置の作製工程を説明する縦断面図。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a silicon nitride film formed on a substrate having a strain point of 700 ° C. or lower, a semiconductor element typified by a field-effect transistor using the silicon nitride film, and a semiconductor integrated circuit.
[0002]
[Prior art]
In a display device using liquid crystal or electroluminescence (abbreviated as EL), a technique has been developed in which a driving circuit is integrally formed using a field-effect thin film transistor (abbreviated as TFT) on the same glass substrate. In order to realize a practical operating frequency, the TFT uses a polycrystalline silicon film for an active layer (semiconductor region forming a channel portion) which is a main component thereof. In addition, a concept of a system-on-panel has been proposed in which integrated circuits having various functions such as a microprocessor, an image processing processor, and a memory are realized by using TFTs to realize a further high-speed operation.
[0003]
Of course, the TFT uses not only a polycrystalline silicon film but also an insulating film in each part such as a gate insulating film and an insulating film for insulating and separating between wirings, and these form an integrated circuit integrally. . The properties required for the materials used for each part are different, and the gate insulating film is required to have few defects, low leakage current, low interface defect state density, etc. On the other hand, there is a variety of applications, such as a need for a property of preventing the entry of alkali ions and the like.
[0004]
With respect to wiring, with the progress of high integration, a technique has been developed in which copper can flow a current at a higher density than aluminum and has high resistance to electromigration as a wiring material.
[0005]
It is required that the insulating film be dense, have a low defect density without pinholes, contain no fixed charge, and have good adhesion to the base. In addition, in order to improve the performance of a transistor with miniaturization of an element, it is necessary to improve the gate driving capability by thinning the gate insulating film, and accordingly, a dense insulating film which does not increase the gate leakage current is required. ing.
[0006]
As a method for forming an insulating film, a CVD method, which is a chemical film forming method, and a sputtering method, which is a physical film forming method, are known. In the CVD method, parameters for classifying the pressure include pressure at the time of film formation, flow rate of supplied gas, energy for accelerating a chemical reaction, and the like. Thermal CVD under normal pressure or reduced pressure, plasma CVD using plasma There are laws and the like, each of which has characteristics and is used according to the purpose.
[0007]
[Problems to be solved by the invention]
When a polycrystalline silicon film is formed on an insulating substrate such as glass or quartz and an integrated circuit is realized using the film, it has been impossible to divert the manufacturing technology cultivated in large-scale integrated circuits as it is. This is not only due to the problem of the crystallinity of the polycrystalline silicon film, but also at present, the insulating film and the semiconductor element using the same by various methods cannot sufficiently exhibit the desired characteristics and reliability. Was.
[0008]
Although a dense silicon nitride film that does not pass alkali ions or the like can be formed by a low-pressure CVD method, the film formation temperature needs to be 750 ° C. or higher. Although the plasma CVD method can form a film at a low temperature, there is a problem that the film is damaged by charged particles in the plasma and defects and pinholes are easily formed. At a film formation temperature of 500 ° C. or less, hydrogen was contained in the film, which reduced the stability of the film. On the other hand, the high frequency sputtering method can use an insulator target such as silicon nitride, and can form a silicon nitride film in which hydrogen is not mixed in the film. However, it is generally known that the film has a large compressive stress, and peeling of the film is often not a problem.
[0009]
Further, in a gate insulating film of a TFT formed by depositing an insulating film, an interface state density is inevitably increased, and a favorable interface cannot be formed. Also, from the viewpoint of interface cleanliness, there is a problem that the polycrystalline silicon film formed on the insulating substrate is easily contaminated. In particular, it is difficult to clearly identify the cause and route of chemical contamination, and boron contamination, which is thought to be caused by filter materials in clean rooms, and phosphorus and organic contamination from wall materials and sealing materials, It is difficult to prevent it only by daily substrate management alone, and the difficulty increases as the size of the glass substrate increases.
[0010]
Although the Cu wiring as described above is formed in a damascene structure in which the wiring is embedded in an insulating film, there is a problem that if an appropriate barrier film is not used, the Cu wiring is easily diffused into a surrounding insulating film or a lamination interface. are doing. In order to prevent this, it is necessary to form a barrier film that does not diffuse Cu and has good adhesion to the base.
[0011]
The present invention has been made in view of the above problems, a technique for forming a dense and high-quality insulating film suitably applicable as a gate insulating film or a protective film on a glass substrate at a temperature equal to or lower than a strain point, and An object of the present invention is to apply the present invention to a semiconductor device realizing high performance and high reliability.
[0012]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is to form a silicon nitride film at a substrate heating temperature of 300 ° C. or lower by using a target of silicon and a high-frequency magnetron sputtering method, using nitrogen or nitrogen and a rare gas as a sputtering gas. It is. The silicon nitride film can be used as a gate insulating film of a TFT. In addition, the present invention is to apply the silicon nitride film and an oxide film formed on the surface of the crystalline semiconductor film by a chemical treatment, a heat treatment, and light irradiation to be applied as a gate insulating film.
[0013]
In the present invention, a silicon nitride film formed by high frequency magnetron sputtering using silicon as a target satisfies at least one of the following characteristics. That is, ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ F) at an etching rate of 10 nm / min or less (preferably 3.5 nm / min or less) in a mixed aqueous solution (20 ° C.) containing 15.4%, and a hydrogen concentration of 1 × 10 ²¹ / Cm ³ Below (preferably 5 × 10 ²⁰ / Cm ³ Below), oxygen concentration is 5 × 10 ¹⁸ ~ 5 × 10 ²¹ / Cm ³ (Preferably 1 × 10 ¹⁹ ~ 1 × 10 ²¹ / Cm ³ ), And preferably simultaneously satisfies a plurality of requirements. The absolute value of the internal stress is 2 × 10 ¹⁰ dyn / cm ² Below, preferably 5 × 10 ⁹ dyn / cm ² Hereinafter, more preferably, 5 × 10 ⁸ dyn / cm ² The following is assumed.
[0014]
The present invention uses 1 × 10 ²¹ / Cm ³ Contains oxygen at the following concentration and contains 5 × 10 ¹⁸ ~ 5 × 10 ²¹ / Cm ³ Ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ Provided is a silicon nitride film having a characteristic that an etching rate with respect to a mixed aqueous solution containing 15.4% of F) is 10 nm / min or less. Such a silicon nitride film having a hydrogen and oxygen content and an etching characteristic is used in a semiconductor device, not only in a region where electrical insulation is required such as a gate insulating film or a dielectric protective film of a capacitor portion, but also in a gas or gas. It can be applied as a protective film for preventing diffusion of ionic impurities.
[0015]
In the semiconductor device of the present invention, 1 × 10 ²¹ / Cm ³ Contains oxygen at the following concentration and contains 5 × 10 ¹⁸ ~ 5 × 10 ²¹ / Cm ³ Ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ A gate insulating film including at least one silicon nitride film having a characteristic of an etching rate of 10 nm / min or less for a mixed aqueous solution containing 15.4% of F) is formed. Further, at least one silicon nitride film is formed as a gate insulating film of a field-effect transistor having a channel length of 0.35 to 2.5 μm.
[0016]
The above-described gate insulating film or the gate insulating film of the field-effect transistor is formed over a crystalline semiconductor film in which a radius of curvature of a projection on a surface is 1 μm or less. The gate insulating film or the gate insulating film of the field-effect transistor is formed over a crystalline semiconductor film having a radius of curvature of a projection of 1 μm or less on the surface.
[0017]
The present invention provides a structure in which a silicon nitride film having the above composition and etching characteristics is formed as a gate insulating film, a dielectric film of a capacitor, a protective film of a semiconductor element, or on an interlayer insulating film made of an organic resin. Any one or a plurality of combinations are included.
[0018]
By having such hydrogen and oxygen contents and etching characteristics, in application to a gate insulating film, a gate leak current is reduced, and a field effect mobility, a subthreshold coefficient, a conductance (gm), and the like are improved. The change with time of the transistor characteristics in continuous operation is reduced, and the manufacturing yield and the variation in characteristics can be improved. Further, such an effect can be more effectively exerted by interposing a silicon oxide film between the crystalline semiconductor film and the silicon nitride film.
[0019]
According to the method for manufacturing a semiconductor device of the present invention, a crystalline semiconductor film formed on an insulating substrate is oxidized, a first step of performing an oxide film removing process is performed, and Ar and N are applied by applying high-frequency power. ₂ Or N ₂ Under a glow discharge only, a second step of forming a silicon nitride film by sputtering a silicon target, and a third step of forming a conductive film by applying DC power; The third step is characterized in that the step is continuously performed under an inert atmosphere or under reduced pressure without exposure to the air. N in the second stage ₂ Is preferably 0.01 to 0.5.
[0020]
According to a method for manufacturing a semiconductor device of the present invention, a crystalline semiconductor film formed on an insulating substrate is subjected to an oxidizing process, a first stage of performing an oxide film removing process, ₂ A second step of forming a silicon oxide film by a heat treatment in an oxidizing atmosphere under glow discharge, and applying Ar and N by applying high frequency power. ₂ Or N ₂ The first to fourth steps include a third step of forming a silicon nitride film by sputtering a silicon target under only glow discharge, and a fourth step of forming a conductive film by applying DC power. The fourth step is characterized in that the step is continuously performed under an inert atmosphere or under reduced pressure without exposure to the air. The oxidizing atmosphere in the second stage is O ₂ And NF ₃ , HF, ClF ₃ It is preferable to add one or more kinds selected from 0.01 to 0.1%. N in the third stage ₂ Is preferably 0.01 to 0.5.
[0021]
The above method for manufacturing a semiconductor device of the present invention can also be applied to a glass substrate having a strain point of 700 ° C. or lower.
[0022]
According to the method for manufacturing a semiconductor device of the present invention, hydrogen is added at a temperature of room temperature to 300 ° C. or lower, preferably ²¹ / Cm ³ Contains oxygen at the following concentration and contains 5 × 10 ¹⁸ ~ 5 × 10 ²¹ / Cm ³ Of ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ A silicon nitride film having an etching rate of 10 nm / min or less for a mixed aqueous solution containing 15.4% of F) can be obtained.
[0023]
In the above method for manufacturing a semiconductor device of the present invention, the power frequency applied in the high-frequency magnetron sputtering method can be 1 MHz to 120 MHz, preferably 10 MHz to 60 MHz.
[0024]
Note that the semiconductor device in the present invention indicates all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention uses a liquid crystal or EL for a gate insulating film and a protective film of a field effect transistor, which is a main component of a semiconductor device, typically a field effect thin film transistor (hereinafter abbreviated as TFT). An oxygen concentration of 1 × 10 is applied to an interlayer insulating film and a protective film in a display device, an interlayer insulating film and a protective film in an integrated circuit formed on an insulating substrate such as glass, and a gate insulating film of a TFT included in the integrated circuit. ¹⁹ / Cm ³ Silicon nitride produced by a high-frequency magnetron sputtering method using the following single crystal or polycrystalline silicon as a target, using nitrogen or nitrogen and a rare gas as a sputtering gas, and setting a substrate heating temperature within a range of room temperature to 300 ° C. or less. Used as
[0026]
FIG. 7 is a view for explaining an embodiment of a preferred multi-task type magnetron sputtering / oxide film forming apparatus in carrying out the present invention. The configuration of the apparatus shown in FIG. 7 includes a plurality of film forming chambers capable of forming a film by sputtering via a gate valve 119 with respect to a first common chamber 101 provided with a substrate transfer means 102. In forming a silicon nitride film, a single reaction chamber is sufficient. However, in order to continuously form a plurality of films having different properties without contacting the atmosphere and without contaminating the interface, the apparatus shown in FIG. The configuration is suitable.
[0027]
A substrate on which a film such as a silicon nitride film is to be formed is loaded into the load / unload chamber 111 and transported by the transport unit 110 provided in the second common chamber 109. The pretreatment chamber 112 is provided with a spinner for rotating the substrate, and is capable of performing processes such as cleaning, oxidation, and removal of an oxide film on the surface of the substrate to be deposited by applying various chemicals from the chemical solution supply unit 118. The load / unload chamber 111, the second common chamber 109, and the pretreatment chamber 112 are filled with an inert gas by a gas supply means 130 and used at normal pressure, and the intermediate chamber 108 has a first pressure reducing interior. It is provided as a room for transferring substrates between the common room 101 and a plurality of film formation rooms connected thereto. Although not shown in detail in FIG. 7, the intermediate chamber 108 may be provided with a cassette holder or the like that temporarily holds the total number of substrates loaded in the load / unload chamber 111.
[0028]
The heat treatment chamber 103 is provided with a heating means 120, which removes and cleans various impurities including atmospheric components adsorbed on the substrate, or heats and densifies or crystallizes a film formed by sputtering. And so on.
[0029]
As a configuration of the heat treatment chamber 103, a heating unit 120 for performing instantaneous thermal annealing (RTA) may be provided. FIG. 20 is a diagram illustrating details of the heat treatment chamber 103. The heat treatment chamber 103 includes a reaction chamber 1129 formed of quartz, and a light source 1110 is provided outside the reaction chamber 1129. In the reaction chamber 1129, there is a substrate holder 1112 made of quartz, and the substrate to be processed is set on the substrate holder 1112. At this time, the substrate to be processed is placed on the pins in order to make the temperature distribution uniform. As a means for monitoring the temperature heated by the light source 1110, a temperature detection system 1128 using a thermocouple is employed here.
[0030]
The light source 1110 is turned on and off by a power supply 1111. The computer 1118 controls the operation of the power supply and the flow control unit 1115. The refrigerant introduced into the reaction chamber 1129 may be circulated and operated by the circulator 1116. It is also important to provide a purifier 1117 in the circulation path to maintain the purity of He as a refrigerant.
[0031]
In addition, a turbo molecular pump 1119 and a dry pump 1120 are provided as exhaust means to enable heat treatment under reduced pressure. In the heat treatment under reduced pressure, the semiconductor film can be heated by using a wavelength band in which lamp light is absorbed by the semiconductor film. By the heat treatment under reduced pressure, the oxidation of the surface of the semiconductor film is suppressed by reducing the oxygen concentration, and as a result, it is possible to promote crystallization and improve gettering efficiency. The target substrate is processed from a transfer chamber connected via a gate, and the target substrate is set on the substrate stage 1112 by the transfer means.
[0032]
FIG. 21 is a diagram illustrating a substrate to be processed heated by a light source and a method of controlling a flow rate of a gas flowing into a processing chamber. First, a substrate to be processed placed at room temperature is rapidly heated by a light source. During the heating period, the heating is performed to a set temperature (for example, 1100 ° C.) at a heating rate of 100 to 200 ° C./sec. For example, if heating is performed at a heating rate of 150 ° C./sec, heating can be performed to 1100 ° C. in less than 7 seconds. Thereafter, the temperature is maintained at the set temperature for a certain period of time, and the light source is turned off. The holding time is 0.5 to 5 seconds. Therefore, the continuous lighting time of the light source is 0.1 second or more, and does not exceed 20 seconds. By continuing to flow the gas into the processing atmosphere, the temperature reduction rate can be set to 50 to 150 ° C./sec. For example, when cooling at a rate of 100 ° C./sec, it is possible to cool from 1100 ° C. to 300 ° C. in 8 seconds.
[0033]
As described above, the cycle of heating by the light source and the cycle of cooling by circulation of the gas are repeatedly performed a plurality of times. This is called a PPTA (Plural Pulse Thermal Annealing) method. By shortening the actual heating time by the PPTA method and irradiating light selectively absorbed by the semiconductor film from a light source, the substrate itself is not heated so much and only the semiconductor film is selectively heated. It becomes possible. The pulse light as shown in FIG. 21 heats the semiconductor film, stops the heating before the heat propagates to the substrate side, and cools the surroundings with a coolant, so that the temperature of the substrate does not increase so much. Therefore, the deformation of the substrate, which has been a problem in the conventional RTA apparatus, can be prevented.
[0034]
The light emission time per light source is 0.1 to 60 seconds, preferably 0.1 to 20 seconds, and light from the light source is irradiated a plurality of times. Alternatively, light from a light source is irradiated in a pulse shape so that the maximum temperature of the semiconductor film is maintained for 0.5 to 5 seconds. Further, by increasing or decreasing the supply amount of the coolant in accordance with the blinking of the light source, the heat treatment effect of the semiconductor film is enhanced, and the substrate is prevented from being damaged by heat. Further, an exhaust means for reducing the pressure in the treatment chamber is provided to reduce the oxygen concentration in the heat treatment atmosphere. This can prevent the surface of the semiconductor film from being oxidized or contaminated by the heat treatment.
[0035]
In FIG. 7, targets of different materials are mounted in the film forming chambers 104 to 107, whereby a plurality of films can be continuously formed under reduced pressure. Each film forming chamber is provided with a gas supply unit 115 for supplying a sputtering gas, an exhaust unit 114, and a pressure control unit 113. Each of the film forming chambers 104 and 105 has a target made of an insulating material, and is connected to a high-frequency power supply 116 for sputtering. The frequency of the power supplied by the high-frequency power supply is 1 MHz to 120 MHz, preferably 10 MHz to 60 MHz. As for the application range of such a frequency, the sheath potential decreases as the frequency increases, and even in the sputtering method using a physical film forming mechanism, the film formation by a chemical reaction is superior and a dense film is formed. Can be expected. Further, the film formation chambers 106 and 107 have a metal target and are connected to a DC power supply 117.
[0036]
FIG. 8 is a diagram illustrating details of the film formation chamber 105 as an example. The film formation chamber 105 is a place where the silicon nitride film according to the present invention is formed. The target 120 is made of silicon, and is cooled by a cooling medium via a backing plate. The permanent magnet 124 makes a circular or linear motion in a direction parallel to the target surface so that a film having uniform thickness can be formed on the opposing substrate surface. The shutter 123 opens and closes before and after the start of film formation to prevent a film from being formed in an unstable plasma state at the beginning of discharge. The substrate holding means 122 holds the substrate up and down and fixes the substrate to the back plate 121. In the back plate 121, a sheath heater is embedded as a heating means 128, and a heated rare gas is introduced from the back side of the substrate to increase the uniformity of heat. A nitrogen gas is introduced from the gas introduction unit 115 in addition to the rare gas, and the pressure in the film formation chamber 105 is controlled by a conductance valve 126. The rectifying plate 125 is provided for the purpose of rectifying the flow of the sputtering gas in the film forming chamber 105. The target is connected to a high-frequency power supply, and sputtering is performed by applying high-frequency power.
[0037]
A high-density silicon nitride film can be formed using silicon as a target by the high-frequency magnetron sputtering with the configuration in FIG. The main film forming conditions are as follows. ₂ Only or N ₂ A mixed gas of Ar and Ar is used as a sputtering gas. The frequency of the applied high frequency power is typically 13.56 MHz, but a higher frequency of 27 to 120 MHz may be applied. As the frequency increases, the chemical reaction becomes more preferential in the film formation mechanism, and it is expected that the film formation is dense and less damages to the underlayer. Ar used as a sputtering gas is introduced as a gas for heating the substrate from the back side of the substrate as shown in FIG. ₂ And contributes to sputtering.
[0038]
Table 1 below shows typical examples of film forming conditions. Of course, the film formation conditions shown here are merely examples, and can be set as appropriate within a range that satisfies the above main film formation conditions.
[0039]
[Table 1]

[0040]
As a comparative example, Table 2 shows film forming conditions of a silicon nitride film formed by a conventional plasma CVD method.
[0041]
[Table 2]

[0042]
Next, Table 3 shows results of comparison of typical characteristic values of the silicon nitride film formed under the film forming conditions of Table 1 and the silicon nitride film formed under the conditions of Table 2. In the sample, the difference between “RFSP-SiN (No. 1)” and “RFSP-SiN (No. 2)” is a difference depending on the sputtering apparatus, and does not impair the function as a silicon nitride film in the present invention. . The sign of the internal stress changes depending on the compressive stress and the tensile stress. Here, only the absolute value is handled.
[0043]
[Table 3]

[0044]
As shown in Table 3, comparative examples of samples of “RFSP-SiN (No. 1)” and “RFSP-SiN (No. 2)” manufactured by the above-described high-frequency magnetron sputtering method manufactured by the plasma CVD method. The characteristic difference between the samples is that ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ The etching rate of a mixed aqueous solution containing 15.4% of F) at 20 ° C. (LAL500 SA buffered hydrofluoric acid; manufactured by Hashimoto Kasei Co., Ltd.) is very low, and the content of hydrogen is extremely low. Further, the internal stress is smaller in absolute value than that of the silicon nitride film formed by the plasma CVD method.
[0045]
The impurity concentrations of hydrogen, oxygen, and carbon in the silicon nitride film were measured by secondary ion mass spectrometry (SIMS), and the results of the depth direction analysis are shown in FIG. The sample is a silicon nitride film formed on a single crystal silicon substrate under the conditions according to Table 1, and has a hydrogen concentration of 1 × 10 ²¹ / Cm ³ It has been found that: The presence or absence of hydrogen bonding in the silicon nitride film is also examined by Fourier transform infrared spectroscopy (FT-IR), and the result is shown in FIG. 5 in comparison with the characteristics of a silicon nitride film manufactured by a plasma CVD method. Even by FT-IR analysis, no absorption peak due to Si—H bond or N—H bond was observed.
[0046]
FIG. 4 shows the transmittance measured by a spectrophotometer. For comparison, FIG. 4 also shows the characteristics of a silicon nitride film formed by a plasma CVD method under the conditions shown in Table 2. There is no remarkable difference between the two, and it can be seen that both are films with good transparency.
[0047]
The above characteristic values show typical results, and from various experimental results, the main characteristic values of the silicon nitride film produced by the high-frequency magnetron sputtering method according to the present invention are as follows.
[0048]
As a result of various studies, the silicon nitride film according to the present invention satisfies at least one of the following characteristics. That is, ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ F) at an etching rate of 10 nm / min or less (preferably 3.5 nm / min or less) in a mixed aqueous solution (20 ° C.) containing 15.4%, and a hydrogen concentration of 1 × 10 ²¹ / Cm ³ Below (preferably 5 × 10 ²⁰ / Cm ³ Below), oxygen concentration is 5 × 10 ¹⁸ ~ 5 × 10 ²¹ / Cm ³ (Preferably 1 × 10 ¹⁹ ~ 1 × 10 ²¹ / Cm ³ ), And preferably simultaneously satisfies a plurality of requirements. The absolute value of the internal stress is 2 × 10 ¹⁰ dyn / cm ² Below, preferably 5 × 10 ⁹ dyn / cm ² Hereinafter, more preferably, 5 × 10 ⁸ dyn / cm ² The following is assumed. If the internal stress is reduced, the occurrence of defect levels at the interface can be suppressed when laminated with another film, and problems such as peeling do not occur.
[0049]
Furthermore, the silicon nitride film of the present invention having the above characteristics has an extremely high blocking effect on elements of the first and second groups of the periodic table represented by Na and Li, and can suppress the diffusion of these mobile ions. . Data showing this fact are shown in FIGS. FIG. 6 is a graph showing the change in CV characteristics before and after the results of a bias-thermal stress (BT stress) test of a MOS structure using a silicon nitride film formed by a plasma CVD method as a dielectric under the conditions shown in Table 2. It is. The structure of the sample is such that a 100 nm silicon nitride film is formed on a single crystal silicon substrate (n-type, 1 to 10 Ωcm) under the conditions shown in Table 2, and Li is added to Al (0.2 to 1.5% by weight). The obtained metal was used as an electrode (diameter 1 mm). By adding Li to the Al electrode in the structure of this sample, the presence or absence of Li diffusion can be checked. The conditions for the BT stress test were such that a voltage of 1.7 MV was applied and the temperature was maintained at 150 ° C. for 1 hour. According to FIG. 6, the CV characteristics are significantly shifted by the BT stress test, and the effect of diffusion of Li from the electrode formed by adding Li to Al formed on the silicon nitride film can be remarkably confirmed.
[0050]
1 and 2 show CV characteristics before and after a BT stress test in a sample having a MOS structure using a silicon nitride film formed as a dielectric film under the conditions shown in Table 1. FIG. 1 shows a sample in which an electrode on a silicon nitride film is formed of Al—Si (Al added with silicon), and FIG. 2 shows a sample in which an electrode is formed of Al—Li. However, the sample has a 50 nm oxide film formed on the surface of a single crystal silicon substrate (p type, 1 to 10 Ωcm), which is formed for the purpose of reducing the influence of the interface state between the silicon nitride film and the silicon substrate. It was done. Therefore, it does not affect the blocking property of the silicon nitride film against Li at all.
[0051]
Comparing the characteristics of FIG. 1 and FIG. 2, there is almost no difference in the change of the CV characteristics before and after the BT stress test in both graphs, and there is no influence due to the diffusion of Li. It can be confirmed that the silicon nitride film formed under the formation conditions effectively functions as a blocking film. As described above, it can be confirmed that the silicon nitride film according to the present invention is very dense and has a high blocking effect against mobile ions such as Na and Li, even though the silicon nitride film is formed at a temperature of 300 ° C. or less. .
[0052]
The very dense silicon nitride film confirmed by the BT stress test and the like described above is different from the physical film formation mechanism by the conventional sputtering phenomenon, in that nitrogen or nitrogen and rare gas ions are formed on the target surface and the film deposition surface. And silicon react with each other to participate in film formation.
[0053]
One consideration example of the film formation mechanism will be described with reference to the schematic diagram of FIG. When glow discharge plasma 900 is formed by applying high-frequency power to target 901, various ion species, excited species, and luminescent species are formed from nitrogen or nitrogen and a rare gas. In this, active nitrogen having extremely chemically active properties is produced. It is known that active nitrogen is extremely reactive and easily forms nitride even at relatively low temperatures. That is, the active nitrogen diffused to the target surface reacts with silicon to form a nitride. Silicon nitride is stable, but when rare gas ions or nitrogen ions are accelerated and incident on the target surface by a sheath electric field, they are sputtered and released into the gas phase. The silicon nitride that diffuses in the glow discharge plasma 900 reacts with active nitrogen or other excited species of nitrogen in the process, and reaches a part of the substrate surface. Then, the surface of the silicon nitride reacts to form silicon nitride. It is considered that also in the surface reaction, the assist of the ion species that is accelerated by the potential difference between the plasma potential and the ground potential acts. By such a film formation mechanism, it is supposed that silicon clusters are not included in the silicon nitride film, and this improves the denseness of the film.
[0054]
If the ratio of the rare gas is higher than the supplied nitrogen, such a film formation mechanism cannot be realized because sputtering by rare gas ions becomes dominant. Ideally, it is sufficient to use only nitrogen gas. However, since the film formation rate is remarkably reduced, it is preferable to select the nitrogen gas within a range in which the mixing ratio of nitrogen and rare gas is 1: 1 at the maximum.
[0055]
Embodiments of a semiconductor device using the silicon nitride film and the manufacturing apparatus will be described below in detail with reference to the drawings.
[0056]
(Embodiment 1)
As a substrate that can be used in this embodiment, a glass substrate formed using barium borosilicate glass, aluminoborosilicate glass, aluminosilicate glass, or the like is suitable. Representatively, a 1737 glass substrate (strain point 667 ° C.) manufactured by Corning, AN100 (strain point 670 ° C.) manufactured by Asahi Glass Co., Ltd. can be applied. Of course, there is no particular limitation if other similar substrates are used. There is no. In any case, a glass substrate having a strain point of 700 ° C. or less is applicable in the present invention. In this embodiment, one mode in which a microprocessor (Micro Processor Unit: MPU) is formed using a silicon nitride film manufactured by a high-frequency magnetron sputtering method on a glass substrate having a strain point of 700 ° C. or lower is described.
[0057]
In the present invention, a substrate having a strain point of 700 ° C. or more is not excluded. Of course, a synthetic quartz substrate having a heat resistant temperature of 1000 ° C. or higher may be used. The silicon nitride film according to the present invention can form a dense and highly blocking film at a temperature of 700 ° C. or less, and does not require a special synthetic quartz substrate in its characteristics.
[0058]
By selecting the above substrate, as shown in FIG. 10A, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y The first inorganic insulator layer 201 made of an insulating film such as (1) is formed. A typical example has a two-layer structure, ₄ , NH ₃ , And N ₂ The first silicon oxynitride film 202 formed by plasma CVD using O as a reaction gas is ₄ , And N ₂ This is a structure in which a second silicon oxynitride film 203 formed by plasma CVD using O as a reaction gas is stacked to a thickness of 100 nm. Here, the first silicon oxynitride film 202 may be replaced with a silicon nitride film formed by a high-frequency magnetron sputtering method. The silicon nitride film can prevent diffusion of a small amount of an alkali metal element such as Na contained in a glass substrate.
[0059]
The crystalline semiconductor film used as the active layer of the TFT is obtained by crystallizing the amorphous silicon film 204 formed on the first inorganic insulator layer 201. Further, instead of the amorphous silicon film, an amorphous silicon germanium (Si _1-x Ge _x X = 0.001 to 0.05) A film may be applied. The thickness of the amorphous silicon film to be formed first is selected so that the thickness of the resulting crystalline silicon film is 20 nm to 60 nm. The upper limit of this film thickness is an upper limit for operation as a fully depleted type in the channel forming region of the TFT, and the lower limit of this film thickness is a process restriction, and is selectively processed in the etching step of the crystalline silicon film. If so, it is determined as the minimum required.
[0060]
In the crystallization step, the method is not particularly limited. For example, as an example of the crystallization method, a metal element having a catalytic action on crystallization of a semiconductor such as nickel may be added for crystallization. In this case, after the layer 205 containing nickel is held on the amorphous silicon film 204, it is crystallized by dehydrogenation (500 ° C., 1 hour) and subsequently by heat treatment at 550 ° C. for 4 hours.
[0061]
FIG. 10B shows a state where the crystalline silicon film 206 is formed. In this state, a crystalline silicon film crystallized at a rate of 50 to 95% is obtained. As shown in FIG. 10C, in order to further improve the crystallinity, a pulse oscillation excimer laser, a YAG laser, or a YVO laser is used. ₄ A laser annealing process for irradiating a second harmonic of a solid laser such as a laser or a YLF laser is performed. In the laser annealing treatment, the laser light is irradiated by an optical system as a linear laser light having a width of 400 μm in the lateral direction with an overlap ratio of 90 to 98%. By the irradiation of the pulse laser beam, as shown in FIG. 10C, a large number of convex portions having the same height as the film thickness are formed on the surface as the maximum value.
[0062]
When a gate insulating film is formed on this crystalline silicon film to form a top gate type TFT, a gate leak current increases. Further, the characteristics are degraded by a stress test in which a bias voltage is applied to the gate electrode. It is considered that this is because the electric field is concentrated on the convex portion. Therefore, it is desirable that the maximum value of the irregularities on the surface of the crystalline silicon film be 10 nm or less, preferably 5 nm or less.
[0063]
Reduction of surface irregularities can be realized by repeating the oxidation treatment with an aqueous solution containing ozone water and the oxide film removal treatment with an aqueous solution containing hydrofluoric acid once, preferably a plurality of times. In this embodiment mode, in order to manufacture a TFT having a channel length of 0.35 to 2.5 μm, to set the substantial thickness of the gate insulating film to 30 to 80 nm, The maximum value of the uneven shape is set to 10 nm or less, preferably 5 nm or less (FIG. 10D).
[0064]
Thereafter, the obtained crystalline silicon film is etched into a desired shape by photolithography using a photomask to form an active layer including a channel formation region, a source and drain region, a low concentration impurity region, and the like in the TFT. Semiconductor films 216 to 218 are formed (FIG. 12A).
[0065]
In order to etch the crystalline silicon film formed in the state shown in FIG. ₄ And O ₂ In order to improve the coverage of the gate insulating film, the end portions of the semiconductor films 216 to 218 are processed so as to have a taper angle of 30 to 60 degrees. The details are shown in FIG. The silicon oxynitride film is also slightly etched depending on the selectivity to the base, but the counterbore depth is set to be 1/3 or less of the thickness d of the semiconductor film. When the counterbore is deep, the gate insulating film is not covered, and a failure occurs in which a gate wiring formed thereover is disconnected. Further, an impurity element imparting p-type may be added to the semiconductor films 216 to 218 in order to control a threshold value (Vth). The impurity element that imparts p-type to the semiconductor includes a Group 13 element of the periodic rule, such as boron (B), aluminum (Al), and gallium (Ga).
[0066]
Next, as shown in FIG. 12B, a silicon oxide film 219 for forming a gate insulating film and a silicon nitride film 220 are formed over the semiconductor films 216 to 218 by a high-frequency magnetron sputtering method to form a first gate electrode. The four layers of the conductive film 221 and the second conductive film 222 are formed continuously under reduced pressure without exposure to the air.
[0067]
The multitasking magnetron sputtering apparatus described in FIG. 7 has a configuration suitable for this step. The steps from formation of the gate insulating film to formation of the gate electrode are roughly as follows.
[0068]
First, the substrate transferred from the load / unload chamber 111 is in the state shown in FIG. The above-described surface smoothing treatment can be performed in the pretreatment chamber 112 provided with a spinner. The oxidation treatment with an aqueous solution containing ozone water and the oxide film removal treatment with an aqueous solution containing hydrofluoric acid are performed to remove the surface of the semiconductor film. Etching is performed mainly on the protrusions. Another characteristic is that the outermost surface of the semiconductor film is etched by this treatment, and a clean and inert surface terminated with hydrogen is formed.
[0069]
Thereafter, the substrate is transferred to the first common chamber 101 evacuated through the intermediate chamber 108. The heat treatment chamber 103 is provided with a heating means 120 for removing moisture adsorbed on the substrate and cleaning the substrate. In the film formation chamber 104, a silicon oxide film is formed with a thickness of 10 to 60 nm by using a synthetic quartz as a target by a high-frequency magnetron sputtering method. The main film formation conditions are sputtering gas O ₂ , Sputtering pressure 0.4 Pa, discharge power 11.0 mW / cm ² , 13.56 MHz, and a substrate heating temperature of 200 ° C. Under these conditions, a dense silicon oxide film 219 having a low interface state density with the semiconductor film can be formed. Next, the substrate is transferred to the film formation chamber 105, and a silicon nitride film is formed with a thickness of 10 to 30 nm by a high-frequency magnetron sputtering method. The film forming conditions are the same as in Table 1. Since the relative dielectric constant of silicon nitride is about 7.5 with respect to the relative dielectric constant of silicon oxide of 3.8, by including a silicon nitride film in a gate insulating film formed of a silicon oxide film, It is possible to obtain the same effect as reducing the thickness of the insulating film.
[0070]
That is, with respect to the smoothness of the surface of the crystalline silicon film, the maximum value of the unevenness is set to 10 nm or less, preferably 5 nm or less, and the gate insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film. Even if the total thickness of the film is 30 to 80 nm, the gate leakage current can be reduced, and the TFT can be driven at 2.5 to 10 V, typically 3.0 to 5.5 V.
[0071]
In addition, since contaminants at the interface between the gate insulating film and the gate electrode also cause variations in TFT characteristics, after forming the gate insulating film, the first conductive film made of tantalum nitride (TaN) having a thickness of 10 to 50 nm is continuously formed. 221 and a second conductive film 222 made of tungsten (W) having a thickness of 100 to 400 nm are stacked. As a conductive material for forming the gate electrode, an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component is used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of an Al film. Alternatively, the first conductive film may be formed of a tantalum nitride (TaN) film, and the second conductive film may be formed of a Cu film.
[0072]
Next, as shown in FIG. 12C, a resist mask 223 on which a gate electrode pattern is formed is formed by photolithography. After that, a first etching process is performed by a dry etching method. For example, an ICP (Inductively Coupled Plasma) etching method is applied to the etching. There is no limitation on the etching gas, but CF for etching W or TaN is used. ₄ And Cl ₂ And O ₂ It is better to use In the first etching process, a predetermined bias voltage is applied to the substrate side so that the side surface of the first shape gate electrode pattern 224 to be formed has a tilt angle of 15 to 50 degrees. Although depending on the etching conditions, the silicon nitride film 220 formed as a gate insulating film by the first etching process remains below the first shape gate electrode pattern 224, exposing the silicon oxide film 219. Thereafter, the etching conditions are changed to the second etching condition, and SF is used as the etching gas. ₆ And Cl ₂ And O ₂ The W film is subjected to anisotropic etching with the bias voltage applied to the substrate side set to a predetermined value. Thus, gate electrodes 224 and 225 are formed. After that, the resist mask 223 is removed.
[0073]
The gate electrode is a stacked structure of the first conductive film 221 and the second conductive film 222, and has a structure in which the first conductive film protrudes like an eave. After that, as shown in FIG. 12A, a doping process is performed to form an impurity region in each semiconductor film. Doping conditions may be set as appropriate. The first n-type impurity region 227 formed in the semiconductor film 216 forms a low concentration drain, and the second n-type impurity region 228 forms a source or drain region. The first p-type impurity region 230 formed in the semiconductor film 217 forms a low concentration drain, and the second p-type impurity region 231 forms a source or drain region. The channel formation regions 226 and 229 in each semiconductor film are located between the low concentration drain regions. The semiconductor film 218 is a member for forming a capacitor, and is doped with an impurity at the same concentration as the second n-type impurity region.
[0074]
Then, as shown in FIG. 16A, a silicon oxynitride film 274 containing hydrogen is formed with a thickness of 50 nm by a plasma CVD method, and the semiconductor film is hydrogenated by heat treatment at 350 to 550 ° C. The RTA heat treatment apparatus shown in FIGS. 20 and 21 is used for this heat treatment. In addition, the above-described activation treatment of the impurity region can be performed simultaneously with the hydrogenation.
[0075]
The interlayer insulating film 275 is formed in a predetermined pattern using a photosensitive organic resin material containing acrylic or polyimide as a main component. After that, a protective film 276 is formed of a silicon nitride film by a high-frequency magnetron sputtering method. When the thickness is 20 to 500 nm, a blocking effect of preventing invasion of various ionic impurities such as oxygen and moisture in the air can be obtained. Then, a contact hole 277 is formed by dry etching (FIG. 16B).
[0076]
After that, as shown in FIG. 16C, wirings 278a to 278d and 279 are formed using Al, Ti, Mo, W, or the like. As an example of the wiring structure, a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy film (an alloy film of Al and Ti) having a thickness of 300 to 500 nm is used.
[0077]
Thus, an n-channel TFT 303, a p-channel TFT 304, and a capacitor portion 305 can be formed. In each TFT, the gate insulating film includes at least one silicon nitride film. Further, in the capacitor portion 305, at least one layer of the silicon nitride film (276) is included as a dielectric film. The silicon nitride film is formed of ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ The present invention is characterized in that the etching rate for a mixed aqueous solution containing 15.4% of F) is 10 nm / min or less.
[0078]
(Embodiment 2)
In Embodiment 1, after the crystalline silicon film shown in FIG. 10B is obtained, as shown in FIG. 11, a YAG laser, a YVO laser, or a YVO laser is used as a continuous oscillation type solid laser. ₄ Laser and YLF laser can be used. YAG laser, YVO ₄ Irradiates the laser and the second harmonic of the YLF laser. For example, YVO ₄ The second harmonic (532 nm) of the laser is condensed linearly and scanned at a speed of 1 to 100 cm / sec to improve the crystallinity. By using a continuous wave laser in this step, a crystalline silicon film with a smooth surface can be obtained, and the maximum value of the unevenness on the surface can be 10 nm or less, preferably 5 nm or less.
[0079]
(Embodiment 3)
In this embodiment mode, a structure of a semiconductor device which has a different gate electrode structure and is more suitable for miniaturization will be described with reference to drawings. Of course, the silicon nitride film according to the present invention is applied to each part of the semiconductor device.
[0080]
In FIG. 13A, semiconductor films 216 to 218 are formed in a manner similar to that in Embodiment 1. As the gate insulating film 240, a silicon nitride film formed by a high-frequency magnetron sputtering method with a thickness of 10 to 80 nm is applied, and a 1 to 5 nm thickness formed by sputtering or oxygen plasma treatment at an interface with the semiconductor film. A silicon oxide film having a thickness is interposed. Thus, it is possible to prevent the interface state density from increasing due to the direct contact between the silicon nitride and the semiconductor film, and to reduce damage during film formation.
[0081]
The gate electrodes 243 and 244 and the capacitor electrode 245 are made of a first conductive film 241 made of tantalum nitride (TaN) with a thickness of 10 to 50 nm and tungsten (W) with a thickness of 100 to 400 nm as in the first embodiment. The second conductive film 242 is formed.
[0082]
After that, as shown in FIG. 13B, first n-type impurity regions 246 and 248 and a first p-type impurity region 247 are formed by doping. These impurity regions are formed so as to overlap with the first conductive film 241 using the second conductive film 242 as a mask.
[0083]
In FIG. 13C, the sidewall spacers 249 to 251 of the gate electrode are formed of a silicon oxide film. A silicon oxide film is formed on the entire surface by a plasma CVD method, and this film is uniformly etched over the entire surface by anisotropic dry etching to form a sidewall spacer. The second n-type impurity regions 252 and 254 and the second p-type impurity region 253 are formed using the gate electrode as a mask.
[0084]
Then, as shown in FIG. 14A, a silicon oxynitride film 256 containing hydrogen is formed with a thickness of 50 nm by a plasma CVD method. Further, a silicon nitride film 257 formed by a high-frequency magnetron sputtering method is formed. After that, hydrogenation is performed by heat treatment at 410 ° C .; however, the silicon nitride film 257 prevents the hydrogen from being diffused into a gaseous phase, thereby increasing the effect of hydrogenation. Further, instead of the silicon nitride film 257, aluminum oxynitride (AlNxOy: X = 2.5 to 47.5 atomic%) may be used. Aluminum oxynitride has the same effect as the silicon nitride film, and also has an effect of dissipating heat generated by the TFT because of its high thermal conductivity. That is, it is possible to reduce the influence of heat generated by miniaturizing the element and improving the degree of integration.
[0085]
The interlayer insulating film 258 can be formed of a silicon oxide film formed by a plasma CVD method, phosphorus glass (PSG) formed by a normal pressure CVD method, boron glass (BSG), or phosphorus boron glass (PBSG). The opening of the contact portion is formed at the same time as the formation of the coating with a photosensitive organic resin material such as polyimide or acrylic.
[0086]
Then, the wiring 259 is formed using Al, Ti, Mo, W, or the like. A silicon nitride film 260 having a thickness of 20 to 100 nm is formed by high frequency magnetron sputtering so as to cover the wiring 259 and the interlayer insulating film 258. This serves as a barrier film for preventing diffusion of Cu when forming a Cu wiring on this upper layer.
[0087]
Then, a second interlayer insulating film 261 is formed with a thickness of 0.5 to 5 μm using a silicon oxide film or an organic resin material. An opening for forming a wiring is formed in the second interlayer insulating film 261, and thereafter a barrier layer 262 made of a tantalum nitride film is formed with a thickness of 100 to 200 nm on the entire surface by a sputtering method. The tantalum nitride film is used as a barrier layer for preventing diffusion of Cu. Further, a seed layer is formed by forming a Cu film by a sputtering method, and a Cu layer 263 is formed to a thickness of 1 to 10 μm by a plating method using copper sulfate. In addition to the plating method, a Cu layer can be formed by a sputtering method and reflowed by a heat treatment at 450 ° C. to realize flattening (FIG. 14C).
[0088]
The Cu wiring 264 is formed by etching the Cu layer 263. Since the Cu wiring is easily oxidized and is thermally unstable, a protective film covering the Cu wiring 264 is formed of a silicon nitride film 265 by high frequency magnetron sputtering with a thickness of 20 to 200 nm. The silicon nitride film is dense and can prevent oxidation of Cu and diffusion to a peripheral portion. Further, by sandwiching the Cu wiring 264 between the silicon nitride film 260 and the silicon nitride film 265, it is possible to prevent the TFT from being contaminated by Cu. If necessary, a third interlayer insulating film 266 is formed, and by performing the same operation as in FIG. 14C, a multilayer wiring can be formed, and a semiconductor device such as a microprocessor or a memory can be formed.
[0089]
(Embodiment 4)
In this embodiment, one mode of forming a Cu wiring by damascene will be described with reference to FIGS. Of course, the silicon nitride film according to the present invention is applied to each part of the semiconductor device.
[0090]
First, the state of FIG. 14B is formed in the same manner as in the third embodiment. That is, the silicon nitride film 260 is formed over the wiring 259. After that, a second interlayer insulating film 267 is formed with a thickness of 1 to 5 μm using a silicon oxide film or an organic resin film. After a silicon nitride film 268 is formed over the second interlayer insulating film 267, an opening 269 for forming a wiring is formed (FIG. 15A).
[0091]
Further, a third interlayer insulating film 270 is formed, approximately aligned with the position of the opening 269, and an opening 272 having a larger opening width is formed. Thereafter, a tantalum nitride film 271 is formed on the entire surface by a sputtering method to a thickness of 100 to 200 nm. The tantalum nitride film serves as a layer for preventing diffusion of Cu (FIG. 15B).
[0092]
Further, after a Cu film is formed by a sputtering method and a seed layer is formed, a Cu layer is formed to a thickness of 1 to 10 μm by a plating method using copper sulfate. In addition to the plating method, a Cu layer may be formed by a sputtering method and may be reflowed by a heat treatment at 450 ° C. to realize flattening.
[0093]
Next, polishing is started from the surface of the Cu plating layer by using a CMP (Chemical-Mechanical Polishing) method, and the polishing is performed until the third interlayer insulating film 270 is exposed. The surface is flattened as shown in FIG. Thus, a Cu wiring 273 is formed. The CMP slurry is composed of abrasive grains, an oxidizing agent, and an additive, and alumina or silica is used for the abrasive grains. As the oxidizing agent, iron nitrate, hydrogen peroxide, potassium periodate or the like is used. In this way, a wiring composed of the barrier layer 271 and the Cu layer 273 is formed. A silicon nitride film 274 may be formed thereover as a protective film. By sandwiching the Cu wiring 263 between the silicon nitride film 260, the silicon nitride film 268, and the silicon nitride film 274, contamination of the TFT with Cu can be prevented.
[0094]
(Embodiment 5)
In this embodiment mode, a structure of a semiconductor device which is more suitable for miniaturization using a synthetic quartz substrate having higher flatness than a glass substrate will be described with reference to FIGS. Of course, the silicon nitride film according to the present invention is applied to each part of the semiconductor device.
[0095]
A crystalline silicon film is formed on a quartz substrate 200. The crystalline silicon film is formed by crystallizing an amorphous silicon film by a heat treatment at 600 to 900 ° C., or by adding an element such as Ni to the crystallization catalyst of silicon to the amorphous silicon film. What crystallized at -700 ° C can be applied. In the latter case, after the crystalline silicon film is obtained, a heat treatment is performed at 850 to 1050 ° C., preferably 950 ° C. for 1 to 12 hours in an oxidizing atmosphere containing halogen, and the catalyst element Is preferably removed by gettering.
[0096]
After that, as illustrated in FIG. 22A, semiconductor films 216 to 218 divided into islands are formed from the crystalline silicon film. Further, a silicon oxide film 280 of 1 to 5 nm is formed on the surfaces of the semiconductor films 216 to 218 by thermal oxidation using the PPTA method described with reference to FIGS. In addition, NF ₃ , HF, ClF ₃ F may be included in the silicon oxide film by performing an oxidation treatment by adding one or more kinds selected from the group consisting of 0.01 to 0.1%.
[0097]
As shown in FIG. 22B, as the gate insulating film 240, a silicon nitride film formed by a high-frequency magnetron sputtering method with a thickness of 10 to 80 nm is applied, and a thermal oxidation treatment is performed on an interface with the semiconductor film. A silicon oxide film 280 having a thickness of 1 to 5 nm formed by the above is interposed. The silicon oxide film can prevent the interface state density from increasing due to direct contact between the silicon nitride and the semiconductor film, can reduce damage during film formation, and can reduce the interface state density. be able to.
[0098]
Further, as a means for obtaining the same effect, a silicon oxide film (chemical oxide) formed with an oxidizing aqueous solution, typically, ozone water may be left.
[0099]
The gate electrodes 243 and 244 and the capacitor electrode 245 are made of a first conductive film 241 made of tantalum nitride (TaN) with a thickness of 10 to 50 nm and tungsten (W) with a thickness of 100 to 400 nm as in the first embodiment. The second conductive film 242 is formed.
[0100]
Thereafter, as shown in FIG. 22C, first n-type impurity regions 246 and 248 and a first p-type impurity region 247 are formed by doping. These impurity regions are formed so as to overlap with the first conductive film 241 using the second conductive film 242 as a mask.
[0101]
In FIG. 22D, the sidewall spacers 249 to 251 of the gate electrode are formed using a silicon oxide film. A silicon oxide film is formed on the entire surface by a plasma CVD method, and this film is uniformly etched over the entire surface by anisotropic dry etching to form a sidewall spacer. The second n-type impurity regions 252 and 254 and the second p-type impurity region 253 are formed using the gate electrode as a mask.
[0102]
Then, as shown in FIG. 23A, a silicon oxynitride film 256 containing hydrogen is formed with a thickness of 50 nm by a plasma CVD method. Further, a silicon nitride film 257 formed by a high-frequency magnetron sputtering method is formed. After that, hydrogenation is performed by heat treatment at 410 ° C .; however, the silicon nitride film 257 prevents the hydrogen from being diffused into a gaseous phase, thereby increasing the effect of hydrogenation. Further, instead of the silicon nitride film 257, aluminum oxynitride (AlNxOy: X = 2.5 to 47.5 atomic%) may be used. Aluminum oxynitride has the same effect as the silicon nitride film, and also has an effect of dissipating heat generated by the TFT because of its high thermal conductivity. That is, it is possible to reduce the influence of heat generated by miniaturizing the element and improving the degree of integration.
[0103]
The interlayer insulating film 258 can be formed of a silicon oxide film formed by a plasma CVD method, phosphorus glass (PSG) formed by a normal pressure CVD method, boron glass (BSG), or phosphorus glass (PBSG). The opening of the contact portion is formed at the same time as the formation of the coating with a photosensitive organic resin material such as polyimide or acrylic.
[0104]
Then, the wiring 259 is formed using Al, Ti, Mo, W, or the like. A silicon nitride film 260 having a thickness of 20 to 100 nm is formed by high frequency magnetron sputtering so as to cover the wiring 259 and the interlayer insulating film 258. This serves as a barrier film for preventing diffusion of Cu when forming a Cu wiring on this upper layer (FIG. 23B).
[0105]
Then, a second interlayer insulating film 261 is formed with a thickness of 0.5 to 5 μm using a silicon oxide film or an organic resin material. An opening for forming a wiring is formed in the second interlayer insulating film 261, and thereafter a barrier layer 262 made of a tantalum nitride film is formed with a thickness of 100 to 200 nm on the entire surface by a sputtering method. The tantalum nitride film is used as a barrier layer for preventing diffusion of Cu. Further, a seed layer is formed by forming a Cu film by a sputtering method, and a Cu layer 263 is formed to a thickness of 1 to 10 μm by a plating method using copper sulfate. In addition to the plating method, a Cu layer can be formed by a sputtering method and reflowed by a heat treatment at 450 ° C. to realize flattening (FIG. 23C).
[0106]
The Cu wiring 264 is formed by etching the Cu layer 263. Since the Cu wiring is easily oxidized and is thermally unstable, a protective film covering the Cu wiring 264 is formed of a silicon nitride film 265 by high frequency magnetron sputtering with a thickness of 20 to 200 nm. The silicon nitride film is dense and can prevent oxidation of Cu and diffusion to a peripheral portion. Further, by sandwiching the Cu wiring 264 between the silicon nitride film 260 and the silicon nitride film 265, it is possible to prevent the TFT from being contaminated by Cu. If necessary, a third interlayer insulating film 266 is formed, and by performing the same operation as in FIG. 23C, a multilayer wiring can be formed, and a semiconductor device such as a microprocessor or a memory can be formed (FIG. 23). (D)). The wiring layer can be multilayered if necessary.
[0107]
(Embodiment 6)
The semiconductor device may be completed by combining the wiring forming process described in Embodiment 4 with Embodiment 5. That is, Cu wiring can be formed by damascene technology. Also in this case, the silicon nitride film according to the present invention is applied.
[0108]
(Embodiment 7)
One embodiment of a microcomputer as a typical semiconductor device manufactured according to Embodiments 1 to 6 will be described with reference to FIGS. As shown in FIG. 18, a microcomputer can be realized by integrating various functional circuit portions on a substrate made of glass or quartz having a thickness of 0.3 to 1.1 mm. Various functional circuit portions can be formed mainly of the TFTs and the capacitor portions manufactured in Embodiment Modes 1 to 6.
[0109]
The components of the microcomputer 2100 shown in FIG. 18 include a CPU 2101, a ROM 2102, an interrupt controller 2103, a cache memory 2104, a RAM 2105, a DMAC 2106, a clock generation circuit 2107, a serial interface 2108, a power generation circuit 2109, an ADC / DAC 2110, a timer counter 2111, WDT 2112, I / O port 2102, and the like.
[0110]
The microcomputer 2100 formed on a glass substrate is fixed to a base 2201 made of ceramic or FRP (fiber reinforced plastic) by face-down bonding. The back surface of the glass substrate of the microcomputer 2100 is coated with aluminum oxynitride 2203 having good thermal conductivity to enhance the heat dissipation effect. Further, a heat dissipating fin 2204 made of aluminum is provided in contact with the heat dissipating fin 2204 to prevent heat generated by the operation of the microcomputer 2100. The whole is covered with a sealing resin 2205, and connection with an external circuit is made by pins 2202.
[0111]
In the present embodiment, the form of the microcomputer has been described as an example. However, if the configuration and combination of various functional circuits are changed, various types of media such as a media processor, a graphics LSI, a cryptographic LSI, a memory, a graphics LSI, a mobile phone LSI, etc. A functional semiconductor device can be completed.
[0112]
【The invention's effect】
According to the present invention, even on a glass substrate having a strain point of 700 ° C. or less, hydrogen is reduced to 1 × 10 ²¹ / Cm ³ Contains oxygen at the following concentration and contains 5 × 10 ¹⁸ ~ 5 × 10 ²¹ / Cm ³ Ammonium hydrogen fluoride (NH ₄ HF ₂ ) With ammonium fluoride (NH ₄ An etching rate with respect to a mixed aqueous solution containing 15.4% of F) has a characteristic of 10 nm / min or less, and a dense silicon nitride film having high blocking properties against mobile ions such as Li can be obtained.
[0113]
By using this silicon nitride film as a gate insulating film or a protective film, particularly as a barrier film for Cu wiring in each part of the semiconductor device, it is possible to provide a semiconductor device realizing high performance and high reliability.
[0114]
By having such hydrogen and oxygen contents and etching characteristics, in application to a gate insulating film, a gate leak current is reduced, and a field effect mobility, a subthreshold coefficient, a conductance (gm), and the like are improved. The change with time of the transistor characteristics in continuous operation is reduced, and the manufacturing yield and the variation in characteristics can be improved. Further, such an effect can be more effectively exerted by interposing a silicon oxide film between the crystalline semiconductor film and the silicon nitride film.
[Brief description of the drawings]
FIG. 1 is a graph showing CV characteristics when a silicon nitride film according to the present invention is used and there is no diffusion of Li in a MOS structure.
FIG. 2 is a graph showing CV characteristics when using a silicon nitride film according to the present invention and diffusion of Li occurs in a MOS structure.
FIG. 3 is a graph showing the results of measuring the concentrations of H, C, and O contained in the silicon nitride film of the present invention by SIMS.
FIG. 4 is a graph showing the transmittance of the silicon nitride film of the present invention and the silicon nitride film of the comparative example.
FIG. 5 is a graph showing infrared absorption spectra of a silicon nitride film of the present invention and a silicon nitride film of a comparative example.
FIG. 6 is a graph showing CV characteristics when a silicon nitride film formed by a plasma CVD method is used and a diffusion of Li occurs in a MOS structure.
FIG. 7 is a top view illustrating a configuration of a magnetron sputtering apparatus applied to the present invention.
FIG. 8 is a cross-sectional view illustrating details of a film forming chamber of a magnetron sputtering apparatus applied to the present invention.
FIG. 9 is a diagram schematically illustrating a film formation mechanism of a silicon nitride film in high frequency magnetron sputtering according to the present invention.
FIG. 10 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 11 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 12 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 13 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 14 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 15 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 16 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 17 illustrates details of an etching shape of a semiconductor film.
FIG. 18 illustrates a configuration of a microcomputer according to the present invention.
FIG. 19 illustrates a package structure of a microcomputer according to the present invention.
FIG. 20 illustrates a structure of a heat treatment chamber.
FIG. 21 is a diagram illustrating a blinking light source, a change in temperature of a semiconductor substrate, and a method of supplying a coolant.
FIG. 22 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 23 is a longitudinal sectional view illustrating a manufacturing process of a semiconductor device of the present invention.

Claims (19)

Hydrogen is contained at a concentration of 1 × 10 ²¹ / cm ³ or less, 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% of ammonium fluoride (NH ₄ F) are formed on the insulating substrate. A semiconductor device comprising a gate insulating film including at least one silicon nitride film having a characteristic that an etching rate with respect to a mixed aqueous solution is 10 nm / min or less. Hydrogen is contained at a concentration of 1 × 10 ²¹ / cm ³ or less, 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% of ammonium fluoride (NH ₄ F) are formed on the insulating substrate. At least one silicon nitride film having a characteristic that an etching rate with respect to a mixed aqueous solution is 10 nm / min or less is formed in a gate insulating film of a field-effect transistor having a channel length of 0.35 to 2.5 μm. Semiconductor device. Hydrogen is contained at a concentration of 1 × 10 ²¹ / cm ³ or less, 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% of ammonium fluoride (NH ₄ F) are formed on the insulating substrate. A silicon nitride film having a characteristic that an etching rate with respect to a mixed aqueous solution is 10 nm / min or less is formed on a crystalline semiconductor film via a silicon oxide film in a gate insulating film of a field effect transistor having a channel length of 0.35 to 2.5 μm. A semiconductor device characterized by being formed. 4. The semiconductor device according to claim 1, wherein the silicon nitride film contains oxygen at a concentration of 5 × 10 ^{18 to} 5 × 10 ²¹ / cm ^3. 5. 4. The semiconductor device according to claim 2, wherein the gate insulating film is formed on a crystalline semiconductor film in which a radius of curvature of a protrusion on a surface is 1 μm or less. The semiconductor device according to claim 1, wherein the insulating substrate is a glass substrate having a strain point of 700 ° C. or lower. On a glass substrate having a strain point of 700 ° C. or less, hydrogen is contained at a concentration of 1 × 10 ²¹ / cm ³ or less, ammonium hydrogen fluoride (NH ₄ HF ₂ ) 7.13% and ammonium fluoride (NH ₄ F) A silicon nitride film having a characteristic of an etching rate of 10 nm / min or less for a mixed aqueous solution containing 15.4% of Si is formed as a dielectric film of a capacitor portion. On a glass substrate having a strain point of 700 ° C. or less, hydrogen is contained at a concentration of 1 × 10 ²¹ / cm ³ or less, ammonium hydrogen fluoride (NH ₄ HF ₂ ) 7.13% and ammonium fluoride (NH ₄ F) A silicon nitride film having a characteristic of an etching rate of 10 nm / min or less with respect to a mixed aqueous solution containing 15.4% of the compound is formed on an interlayer insulating film made of an organic resin. Hydrogen is contained at a concentration of 1 × 10 ²¹ / cm ³ or less, 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and 15.4% of ammonium fluoride (NH ₄ F) are formed on the insulating substrate. A semiconductor device, wherein a silicon nitride film having a characteristic that an etching rate with respect to a mixed aqueous solution is 10 nm / min or less is formed as a protective film of a semiconductor element. The semiconductor device according to claim 9, wherein the insulating substrate is a glass substrate having a strain point of 700 ° C. or lower. 10. The semiconductor device according to claim 7, wherein the silicon nitride film contains oxygen at a concentration of 5 × 10 ^{18 to} 5 × 10 ²¹ / cm ³ . It is formed on a glass substrate having a strain point of 700 ° C. or less, contains hydrogen at a concentration of 1 × 10 ²¹ / cm ³ or less, contains 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH _4). A silicon nitride film having a characteristic that an etching rate with respect to a mixed aqueous solution containing 15.4% of F) is 10 nm / min or less. It is formed on an organic resin film, contains hydrogen at a concentration of 1 × 10 ²¹ / cm ³ or less, contains ammonium hydrogen fluoride (NH ₄ HF ₂ ) 7.13%, and ammonium fluoride (NH ₄ F) 15. A silicon nitride film having an etching rate of 10 nm / min or less for a mixed aqueous solution containing 4%. The silicon nitride film according to claim 12, wherein oxygen is contained at a concentration of 5 × 10 ^{18 to} 5 × 10 ²¹ / cm ³ . The crystalline semiconductor film formed on the insulating substrate is subjected to an oxidation treatment, a first step of performing an oxide film removal treatment, and application of high-frequency power under a glow discharge of only Ar and N ₂ or N ₂ to remove silicon. The method includes the following steps: a second step of forming a silicon nitride film by sputtering a target; and a third step of forming a conductive film by applying DC power. A method for manufacturing a semiconductor device, which is performed continuously in an inert atmosphere or under reduced pressure. A first stage of performing an oxidation process and an oxide film removal process on the crystalline semiconductor film formed on the insulating substrate, a second stage of forming a silicon oxide film by a heat treatment in an oxidizing atmosphere, A third step of sputtering a silicon target to form a silicon nitride film under a glow discharge of only Ar and N ₂ or N ₂ , and a fourth step of forming a conductive film by applying DC power. A method for manufacturing a semiconductor device, including each of the steps, wherein the first to fourth steps are continuously performed in an inert atmosphere or under reduced pressure without exposure to the air. In claim 16, the ratio of Ar for _{N 2} in the second step, a method for manufacturing a semiconductor device, characterized in that 0.01 to 0.5. In claim 16, the ratio of Ar for _{N 2} in the third step, the method for manufacturing a semiconductor device, characterized in that 0.01 to 0.5. In claim 16, the production of the oxidation atmosphere in the second _stage, NF 3, HF, and wherein a the addition of one or more selected from ClF ₃ 0.01 to 0.1% Method.

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