JPH0750362A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0750362A
JPH0750362A JP4256672A JP25667292A JPH0750362A JP H0750362 A JPH0750362 A JP H0750362A JP 4256672 A JP4256672 A JP 4256672A JP 25667292 A JP25667292 A JP 25667292A JP H0750362 A JPH0750362 A JP H0750362A
Authority
JP
Japan
Prior art keywords
conductor layer
semiconductor device
conductive layer
dielectric substrate
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4256672A
Other languages
Japanese (ja)
Other versions
JP2611718B2 (en
Inventor
Kazuyoshi Kamimura
和義 上村
Kazuhiro Tawara
和弘 田原
Sadayoshi Yoshida
貞義 吉田
Takeshi Umemoto
毅 梅本
Tatsuya Miya
龍也 宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4256672A priority Critical patent/JP2611718B2/en
Priority to KR1019930019629A priority patent/KR940008547A/en
Publication of JPH0750362A publication Critical patent/JPH0750362A/en
Application granted granted Critical
Publication of JP2611718B2 publication Critical patent/JP2611718B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device which can be stably operated even at the high frequencies exceeding 10 GHz using the semiconductor device on which a high frequency semiconductor chip is mounted. CONSTITUTION:The first conductive layer 2 is formed on the surface of a dielectric substrate 1, the second conductive layer 3 is formed on the rear of the substrate 1, the third conductive layer 4 is formed on the side face of the substrate 1, the prescribed number of through holes 10 are formed on the dielectric substrate 1, and the fourth conductive layer 11 is formed in the through holes. The first conductive layer 2, which transmits high frequency waves, is electrically connected to the second conductive layer 3 by the third conductive layer 4 and the fourth conductive layer 11. By the presence of the fourth conductive layer 11, the stub circuit of a brazed and soldered part 9 is cancelled, and the mismatching of impedance in a high frequency zone can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、高周波用半導体装置に
関し、特に高周波帯域まで対応できる容器を有する半導
体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency semiconductor device, and more particularly to a semiconductor device having a container capable of handling a high frequency band.

【０００２】[0002]

【従来の技術】衛星放送等の普及に伴い、１０ＧＨｚを
越える周波数帯域を使用する半導体装置が民生化され、
高周波帯での半導体装置の小型化，表面実装化，低価格
化の要求が強まってきているが、この種の半導体装置を
実現するために、半導体チップを搭載する高周波帯域で
使用可能な、小型で低価格かつシステムの組立自動化の
ための表面実装タイプの半導体チップ実装用の容器が必
要となる。2. Description of the Related Art With the spread of satellite broadcasting and the like, semiconductor devices using a frequency band exceeding 10 GHz have been commercialized,
Although there is an increasing demand for miniaturization, surface mounting, and cost reduction of semiconductor devices in the high frequency band, in order to realize this type of semiconductor device, a small size that can be used in the high frequency band in which a semiconductor chip is mounted is used. Therefore, a low-cost container for mounting surface-mounting type semiconductor chips for system assembly automation is required.

【０００３】従来この種の小型，表面実装型の半導体容
器及び、半導体装置の構造として特公昭５２−２０２３
０号公報に提案されている半導体装置がある。図８は同
公報の半導体装置を示している。すなわち誘電体基板１
の表面に形成された第１の導体層２と誘電体基板１の裏
面に形成された第２の導体層３と誘電体基板１の側面に
形成された第３の導体層４と、少なくとも一つの第１の
導体層２に搭載された半導体チップ５と、半導体チップ
５の電極６と他の第１の導体層２′とを電気的につなぐ
接続手段７と第２の導体層３にロウ材１３によりロウ付
けされた外部取出し用導体リード８を含み、第１の導体
層２と第２の導体層３をつなぐ所定個の第３の導体層４
を有し、誘電体基板１の表面上より透視的にみて、第１
の導体層２と第２の導体層３がそれぞれ誘電体基板１の
表裏で占有するところの領域が互いに重複しない構造を
もつ。しかるにこの従来の半導体装置は、第２の導体層
３に導体リード８をロウ付けするためのロウ付け部９が
必ず存在し、実用上のリード強度を確保するためには、
このロウ付け部９をある程度大きくする必要があった。
例えば、厚さ０．２ｍｍ程度，幅０．４ｍｍ程度の外部
引き出し用導体リードを上記従来の半導体装置に適用
し、導体リードの９０°方向引っ張り強度を０．５ｋｇ
以上確保するには、少なくとも、０．８ｍｍ程度以上の
ロウ付け部長さが必要である。Conventionally, as a structure of a small-sized, surface-mounting type semiconductor container and a semiconductor device of this type, Japanese Patent Publication No. 52-2023.
There is a semiconductor device proposed in Japanese Unexamined Patent Publication No. FIG. 8 shows the semiconductor device of the publication. That is, the dielectric substrate 1
At least one of the first conductor layer 2 formed on the front surface of the dielectric substrate 1, the second conductor layer 3 formed on the back surface of the dielectric substrate 1, and the third conductor layer 4 formed on the side surface of the dielectric substrate 1. The semiconductor chip 5 mounted on one of the first conductor layers 2, the connecting means 7 for electrically connecting the electrode 6 of the semiconductor chip 5 and the other first conductor layer 2 ′ and the solder to the second conductor layer 3. A predetermined number of third conductor layers 4 including the external lead conductor leads 8 brazed by the material 13 and connecting the first conductor layer 2 and the second conductor layer 3
And has a first surface as seen from a perspective of the surface of the dielectric substrate 1.
In the structure, the regions occupied by the conductor layer 2 and the second conductor layer 3 on the front and back sides of the dielectric substrate 1 do not overlap each other. However, in this conventional semiconductor device, the brazing portion 9 for brazing the conductor lead 8 to the second conductor layer 3 is always present, and in order to secure practical lead strength,
It was necessary to make the brazing portion 9 large to some extent.
For example, a conductor lead for external extraction having a thickness of about 0.2 mm and a width of about 0.4 mm is applied to the conventional semiconductor device described above, and the tensile strength of the conductor lead in the 90 ° direction is 0.5 kg.
To secure the above, at least a brazing portion length of about 0.8 mm or more is required.

【０００４】このリードロウ付け部９は、この半導体装
置が、他の半導体装置に実装される場合、例えば裏面が
接地パターンとしたテフロン等の実装基板に実装された
場合リードロウ付け部９と実装基板の裏面パターンとの
間に容量が形成されるため、このリードロウ付け部９は
オープンスタブ回路として働くことになる。このオープ
ンスタブ回路は、半導体チップと外部回路をつなぐ高周
波伝送線路の間に挿入された形となり、このタイプの半
導体装置の使用周波数が高くなるほど、このオープンス
タブ回路の影響により、半導体チップと、外部回路との
間にインピーダンスの不整合が生ずることになる。When the semiconductor device is mounted on another semiconductor device, for example, when the lead brazing portion 9 is mounted on a mounting substrate such as Teflon having a back surface as a ground pattern, the lead brazing portion 9 and the mounting substrate are mounted. Since a capacitance is formed between the lead pattern and the back surface pattern, the lead brazing portion 9 functions as an open stub circuit. This open stub circuit is inserted between the high frequency transmission line connecting the semiconductor chip and the external circuit, and the higher the operating frequency of this type of semiconductor device is, the more influence the open stub circuit has on the semiconductor chip and the external circuit. An impedance mismatch with the circuit will occur.

【０００５】又、オープンスタブ回路を回避する従来の
表面実装型の半導体装置の構造を図９に示す。スルーホ
ールとスルーホールに形成した第４の導体層のみで第１
の導体層と第２の導体層を接続する方法が考えられる
が、容器部のスルー特性がよくないという欠点があっ
た。FIG. 9 shows the structure of a conventional surface mount type semiconductor device which avoids the open stub circuit. First through only the through hole and the fourth conductor layer formed in the through hole
Although a method of connecting the conductor layer and the second conductor layer can be considered, there is a drawback that the through characteristic of the container is not good.

【０００６】[0006]

【発明が解決しようとする課題】以上の説明の様に、特
公昭５２−２０２３０号公報に示される従来の半導体装
置では、外部回路との接続部に、オープンスタブ回路を
形成してしまい、高い周波数において、インピーダンス
の不整合を生じてしまうという欠点があった。As described above, in the conventional semiconductor device disclosed in Japanese Examined Patent Publication No. 52-20230, an open stub circuit is formed at a connection portion with an external circuit, which is expensive. There is a drawback that impedance mismatch occurs at the frequency.

【０００７】また、スルーホールを形成して、基板側面
部に導電層を形成しない構造では容器部のスルー特性が
よくないという欠点があった。Further, in the structure in which the through hole is formed and the conductive layer is not formed on the side surface of the substrate, the through characteristic of the container portion is not good.

【０００８】[0008]

【課題を解決するための手段】本発明によれば、誘電体
基板の一主面上に形成された第１の導体層と、誘電体基
板の他の主面に形成された第２の導体層と、誘電体基板
の側面に形成された第３の導体層と、誘電体基板を貫通
するスルーホールと、スルーホール中に形成された第４
の導体層と、誘電体基板の一主面上に搭載された半導体
チップと、第１の導体層と半導体チップの電極とをつな
ぐ接続手段と、第２の導体層にロウ付けされた外部引き
出し用の導体リードとを有し、誘電体基板の一主面上で
第１の導体層に第３の導体層と第４の導体層が接続さ
れ、誘電体基板の他の主面上で第２の導体層に第１の導
体層と第３の導体層が接続され、第２の導体層と外部引
き出し用の導体リードとが接続されている半導体装置が
得られる。According to the present invention, a first conductor layer formed on one main surface of a dielectric substrate and a second conductor layer formed on another main surface of the dielectric substrate. A layer, a third conductor layer formed on the side surface of the dielectric substrate, a through hole penetrating the dielectric substrate, and a fourth hole formed in the through hole.
Conductor layer, a semiconductor chip mounted on one main surface of the dielectric substrate, connecting means for connecting the first conductor layer and the electrode of the semiconductor chip, and an external lead brazed to the second conductor layer. And a third conductor layer and a fourth conductor layer are connected to the first conductor layer on one main surface of the dielectric substrate, and the third conductor layer on the other main surface of the dielectric substrate. A semiconductor device is obtained in which the first conductor layer and the third conductor layer are connected to the second conductor layer, and the second conductor layer and the conductor lead for external extraction are connected.

【０００９】[0009]

【作用】本発明の半導体装置は、高周波伝送に使用する
誘電体基板の表面の第１の導体層とその誘電体基板の裏
面の第２の導体層とを電気的に接続する手段として誘電
体基板の側面に形成した、第３の導体層と、誘電体基板
に形成されたスルーホールに形成した第４の導体層の両
者により接続するという特徴を持つ。The semiconductor device of the present invention uses the dielectric as a means for electrically connecting the first conductor layer on the front surface of the dielectric substrate used for high frequency transmission and the second conductor layer on the back surface of the dielectric substrate. It is characterized in that both the third conductor layer formed on the side surface of the substrate and the fourth conductor layer formed in the through hole formed in the dielectric substrate are connected.

【００１０】従来の半導体装置に存在したオープンスタ
ブ回路の先端に近い場所にスルーホールと、スルーホー
ルに形成した第４の導体層により電気的に接続すること
によりオープンスタブとしての効果を打ち消し、容器に
よるインピーダンスの不整合を防止できる。The effect as an open stub is canceled by electrically connecting the through hole at a position near the tip of the open stub circuit existing in the conventional semiconductor device with the fourth conductor layer formed in the through hole, thereby canceling the effect as an open stub. It is possible to prevent impedance mismatch due to.

【００１１】図１０に導体層の抵抗とインダクタンスを
表わすモデル図を示す。（ａ）は従来構造の第１の例。
（ｂ）は従来構造の第２の例、（ｃ）は本発明による第
１の実施例をそれぞれ表す。本発明によれば、抵抗成分
及びインダクタンス成分を並列に接続した構造となり、
従来の直列型とは全く異なる飛躍的な特性の改善を得る
ことができる。FIG. 10 is a model diagram showing the resistance and inductance of the conductor layer. (A) is a first example of a conventional structure.
(B) shows the second example of the conventional structure, and (c) shows the first example according to the present invention. According to the present invention, a resistance component and an inductance component are connected in parallel,
It is possible to obtain a dramatic improvement in characteristics, which is completely different from the conventional series type.

【００１２】[0012]

【実施例】以下図面に従って、本発明の半導体装置を説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device of the present invention will be described below with reference to the drawings.

【００１３】図１は、本発明による半導体装置の第１の
実施例であり、厚さ０．４ｍｍ程度のアルミナ等の誘電
体基板１の表面に形成された第１の導体層２と誘電体基
板１の裏面に形成された第２の導体層３と、誘電体基板
１の側面に形成された第３の導体層４と、誘電体基板１
に形成されたスルーホール１０とスルーホール１０に穴
うめされた第４の導体層１１とを有する。第４の導体層
１１はスルーホール１０に穴うめされても、スルーホー
ルの壁面に形成されるのでもよい。第１の導体層２は、
第３の導体層４と、第４の導体層１１の両者により第２
の導体層３に電気的に接続されている誘電体基板の表面
には、他の第１の導体層２′が形成されており、そこに
ＧａＡｓＩＣ等の半導体チップ５がＡｕＳｎ等のロウ材
によりロウ付けされている。半導体チップ５の電極６
と、第１の導体層２とは金ワイヤ等の接続手段７により
電気的に接続されている。第２の導体層には、外部引き
出しリード８及び接地用裏面メタル１２が銀ロウ等ロウ
材１３によりロウ付されている。又、誘電体基板１に
は、セラミックキャップ１４が樹脂１５により接着され
ている。FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, in which a first conductor layer 2 formed on the surface of a dielectric substrate 1 made of alumina or the like having a thickness of about 0.4 mm and a dielectric material are formed. The second conductor layer 3 formed on the back surface of the substrate 1, the third conductor layer 4 formed on the side surface of the dielectric substrate 1, and the dielectric substrate 1
The through hole 10 formed in the above and a fourth conductor layer 11 filled in the through hole 10. The fourth conductor layer 11 may be filled in the through hole 10 or may be formed on the wall surface of the through hole. The first conductor layer 2 is
The third conductor layer 4 and the fourth conductor layer 11 both provide a second
The other first conductor layer 2'is formed on the surface of the dielectric substrate which is electrically connected to the conductor layer 3 of, and the semiconductor chip 5 such as GaAsIC is formed by the brazing material such as AuSn. It is brazed. Electrode 6 of semiconductor chip 5
And the first conductor layer 2 are electrically connected by a connecting means 7 such as a gold wire. The external lead 8 and the backside metal 12 for grounding are brazed to the second conductor layer by a brazing material 13 such as silver brazing. A ceramic cap 14 is adhered to the dielectric substrate 1 with a resin 15.

【００１４】図２は、本発明の第２の実施例を示す断面
図であり、図７はその一部平面図である。基本的構成は
第１の実施例と同様である。本実施例では第１の導体層
２と、第２の導体層３をつなぐスルーホールが２つあり
このスルーホール１０，１０′に各々第４の導体層１１
と１１′が形成されている。本実施例ではスルーホール
に形成された第４の導体層のインダクタンス成分をさら
に低減できるという効果がある。FIG. 2 is a sectional view showing a second embodiment of the present invention, and FIG. 7 is a partial plan view thereof. The basic configuration is similar to that of the first embodiment. In this embodiment, there are two through holes connecting the first conductor layer 2 and the second conductor layer 3, and the fourth conductor layer 11 is provided in each of the through holes 10 and 10 '.
And 11 'are formed. The present embodiment has the effect of further reducing the inductance component of the fourth conductor layer formed in the through hole.

【００１５】製造方法としては、まず、図３に示す未焼
結アルミナテープ（グリーンテープ）に所定の金型によ
りスルーホール部及び側面メタル（第３の導体層）形成
部を打ち抜く（スルーホール部は図中に不記）。ここで
本実施例では、誘電体基板を複数個取りとし、かつ、側
面メタル形成部１６も、最初スルーホール同様円形に打
ち抜く。その後、導体（タングステン等）印刷（第１，
第２の導体層）及びスルーホールメタル形成（第３，第
４の導体層）を行ない、その後、絶縁層印刷を行なう。
本実施例ではソルダーダム及びキャップ封着部に絶縁層
印刷を行なっている。その後金型により、切断溝１７を
形成し、約１６００℃の温度で焼成する。焼成された複
数個取り、基板は上記切断溝で切断し個片に切断しＮｉ
メッキを施す切断により、側メタ部は、半円又は１／４
円として形成される。個片基板は、Ａｕ−Ｃｕ等により
リードフレームに接合する。その後Ａｕ等の仕上げメッ
キを施こし完成する（図４，５，６参照）。図４はスル
ーホールの位置を上面から見た平面図であり、図５は下
面図である。図４及び図５には長さ（単位：ｍｍ）が記
入されている。図中の長さ通りであることが好ましいが
全ての±１０％程度変化させても良い。As a manufacturing method, first, a through-hole portion and a side surface metal (third conductor layer) forming portion are punched out (through-hole portion) on an unsintered alumina tape (green tape) shown in FIG. 3 by a predetermined die. Is not shown in the figure). Here, in this embodiment, a plurality of dielectric substrates are taken, and the side surface metal forming portion 16 is first punched out in a circular shape like the through hole. After that, printing conductors (tungsten etc.) (first,
The second conductor layer) and the through-hole metal are formed (third and fourth conductor layers), and then the insulating layer is printed.
In this embodiment, the insulating layer is printed on the solder dam and the cap sealing portion. After that, a cutting groove 17 is formed by a die, and firing is performed at a temperature of about 1600 ° C. Take a plurality of fired pieces, cut the substrate into the above-mentioned cutting grooves, and cut into individual pieces.
Side meta part is semi-circle or 1/4 by cutting with plating
Formed as a circle. The individual substrate is bonded to the lead frame by Au-Cu or the like. After that, finish plating such as Au is applied to complete the process (see FIGS. 4, 5 and 6). FIG. 4 is a plan view of the position of the through hole as viewed from above, and FIG. 5 is a bottom view. The length (unit: mm) is entered in FIGS. 4 and 5. It is preferable that the length is as shown in the figure, but it may be changed by about ± 10%.

【００１６】[0016]

【発明の効果】以上説明した様に、本発明の半導体装置
では、外部引き出し用の導体リードのロウ付け部のほぼ
先端に近い部分にスルーホールが形成され、スルーホー
ルに形成された第４の導体層と、誘電体基板の側面に形
成された第３の導体層の両者により、第１の導体層２
と、第２の導体層を電気的に接続されている。第４の導
体層による接続により導体リードロウ付部の部分はオー
プンスタブとしては作用せず、高周波帯域における半導
体チップと、外部回路との接続の不整合を抑制できる。As described above, in the semiconductor device of the present invention, a through hole is formed in a portion near the tip of the brazing portion of the conductor lead for external extraction, and the fourth hole is formed in the through hole. The first conductor layer 2 is formed by both the conductor layer and the third conductor layer formed on the side surface of the dielectric substrate.
And the second conductor layer is electrically connected. Due to the connection by the fourth conductor layer, the portion with the conductor lead brazing does not act as an open stub, and the mismatch of the connection between the semiconductor chip and the external circuit in the high frequency band can be suppressed.

【００１７】図１１（ａ），（ｂ）は、本発明の第１の
実施例の容器部分におけるスルー特性を反射損（Ｓ11）
と、挿入損（Ｓ21）によりそれぞれ表わしたものであ
り、おおよそ２０ＧＨｚまで、反射損（Ｓ11）を−１５
ｄＢ程度以下に確保できるのがわかる。11 (a) and 11 (b) show reflection loss (S 11 ) of the through characteristic in the container portion of the first embodiment of the present invention.
And the insertion loss (S 21 ) respectively, and the reflection loss (S 11 ) is −15 up to about 20 GHz.
It can be seen that the value can be secured at about dB or less.

【００１８】図１２（ａ），（ｂ）は従来構造の容器部
と、本発明の構造の容器部を簡単なモデルにより従来構
造の欠点と本発明の効果を確認したもので半導体チップ
から外部引き出しリードまでのスルー特性を反射損（Ｓ
11）と挿入損（Ｓ21）によりそれぞれ表現している。こ
こに実線は本発明の構造モデル，破線は従来の第１の例
の構造モデルの特性である。図１２（ａ）が示す様に、
従来の第１の例の構造モデルでは周波数１５ＧＨｚ以上
で反射損（Ｓ11）が悪くなりはじめ３０ＧＨｚ付近で共
振をもっている。これに対し本発明の構造モデルでは、
周波数４０ＧＨｚまで共振はなく、反射損（Ｓ11）も従
来に比べ１２ＧＨｚ以上で改善されている。12 (a) and 12 (b) show the defect of the conventional structure and the effect of the present invention by a simple model of the container part of the conventional structure and the container part of the structure of the present invention. Reflection loss (S
11 ) and insertion loss (S 21 ) respectively. Here, the solid line is the structural model of the present invention, and the broken line is the characteristic of the conventional structural model of the first example. As shown in FIG. 12 (a),
In the conventional structural model of the first example, the reflection loss (S 11 ) begins to deteriorate at a frequency of 15 GHz or higher and has resonance at around 30 GHz. On the other hand, in the structural model of the present invention,
There is no resonance up to a frequency of 40 GHz, and the reflection loss (S 11 ) is also improved at 12 GHz or more as compared with the conventional case.

【００１９】又、オープンスタブ回路を回避する図９の
様な表面実装型の半導体装置の構造として、スルーホー
ルと、スルーホールに形成した第４の導体層のみで第１
の導体層と第２の導体層を接続する従来構造の第２の例
が考えられるが、図１３（ａ），（ｂ）で反射損
（Ｓ11）と挿入損（Ｓ21）に分けて容器部のスルー特性
を比較した実測データに示す様に、やはり本発明による
構造は、反射損（Ｓ11）特性に優れている事が判る。Further, as a structure of the surface mount type semiconductor device as shown in FIG. 9 which avoids the open stub circuit, only the through hole and the fourth conductor layer formed in the through hole are provided.
The second example of the conventional structure in which the conductor layer of FIG. 13 and the second conductor layer are connected is conceivable. In FIGS. 13A and 13B, the reflection loss (S 11 ) and the insertion loss (S 21 ) are divided into As shown in the measured data comparing the through characteristics of the container, it can be seen that the structure according to the present invention is also excellent in the reflection loss (S 11 ) characteristics.

【００２０】以上説明した様に本発明の半導体装置によ
れば１０ＧＨｚ以上の周波数帯域においても実用上十分
な所要特性を得る事ができる。又、本半導体装置の容器
の主要部は一枚の誘電体基板と、印刷技術とスルーホー
ル技術とリード部の１回のロー付けにより、作成でき、
非常に安価に作成することができる。As described above, according to the semiconductor device of the present invention, it is possible to obtain practically required characteristics even in the frequency band of 10 GHz or higher. Also, the main part of the container of this semiconductor device can be created by a single dielectric substrate, printing technology, through hole technology, and brazing of the lead part once.
Can be created very cheaply.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による半導体装置の第１の実施例の断面
図。FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention.

【図２】本発明による半導体装置の第２の実施例の断面
図。FIG. 2 is a sectional view of a second embodiment of a semiconductor device according to the present invention.

【図３】本発明による半導体装置の第１の実施例の切断
前の基板を示す平面図。FIG. 3 is a plan view showing a substrate before cutting of the first embodiment of the semiconductor device according to the present invention.

【図４】本発明による半導体装置の第１の実施例の平面
図。FIG. 4 is a plan view of the first embodiment of the semiconductor device according to the present invention.

【図５】本発明による半導体装置の第１の実施例を示す
平面図。FIG. 5 is a plan view showing a first embodiment of the semiconductor device according to the present invention.

【図６】本発明による半導体装置の第１の実施例の下面
図。FIG. 6 is a bottom view of the first embodiment of the semiconductor device according to the present invention.

【図７】本発明による半導体装置の第２の実施例を示す
部分平面図。FIG. 7 is a partial plan view showing a second embodiment of the semiconductor device according to the present invention.

【図８】従来の半導体装置の第１の例の断面図。FIG. 8 is a sectional view of a first example of a conventional semiconductor device.

【図９】従来の半導体装置の第２の例の断面図。FIG. 9 is a sectional view of a second example of a conventional semiconductor device.

【図１０】導電層部の抵抗とインダクタンスを表わし、
（ａ）は従来の第１の例（ｂ）は従来の第２の例（ｃ）
は本発明による第１の実施例をそれぞれ示すモデル図。FIG. 10 shows resistance and inductance of a conductive layer portion,
(A) is a conventional first example (b) is a conventional second example (c)
Are model diagrams respectively showing a first embodiment according to the present invention.

【図１１】本発明による第１の実施例の容器部のスルー
特性図。FIG. 11 is a through characteristic diagram of the container portion according to the first embodiment of the present invention.

【図１２】本発明による第１の実施例と従来の第１の例
の容器部の比較特性図。FIG. 12 is a comparative characteristic diagram of the container portion of the first example according to the present invention and the conventional first example.

【図１３】本発明による第１の実施例と従来の第２の例
の容器部の比較特性図。FIG. 13 is a comparative characteristic diagram of the container portion of the first example according to the present invention and the conventional second example.

【符号の説明】[Explanation of symbols]

１ 誘電体基板 ２ 第１の導体層 ３ 第２の導体層 ４ 第３の導体層 ５ 半導体チップ ６ 半導体チップの電極 ７ 接続手段（Ａｕワイヤ等） ８ 外部引き出し用導体リード ９ ロウ付け部 １０ スルーホール １１ 第４の導体層 １２ 裏面メタル １３ ロウ材 １４ セラミックキャップ １５ 樹脂 １６ 側面メタル用打ち抜き穴 １７ 切断溝 1 Dielectric Substrate 2 First Conductor Layer 3 Second Conductor Layer 4 Third Conductor Layer 5 Semiconductor Chip 6 Semiconductor Chip Electrode 7 Connection Means (Au Wire etc.) 8 External Lead Conductor Lead 9 Brazing Part 10 Through Hole 11 Fourth conductor layer 12 Backside metal 13 Brazing material 14 Ceramic cap 15 Resin 16 Side metal punching hole 17 Cutting groove

───────────────────────────────────────────────────── フロントページの続き (72)発明者 梅本 毅 東京都港区芝五丁目７番１号日本電気株式 会社内 (72)発明者 宮 龍也 東京都港区芝五丁目７番１号日本電気株式 会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takeshi Umemoto 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Tatsuya Miya 5-7-1, Shiba, Minato-ku, Tokyo NEC Stock Company

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 誘電体基板の一主面上に形成された第１
の導体層と、前記誘電体基板の他の主面上に形成された
第２の導体層と、前記誘電体基板の側面に形成された第
３の導体層と、前記誘電体基板を貫通するスルーホール
と、前記スルーホール中に形成された第４の導体層と、
前記誘電体基板の一主面上に搭載された半導体チップ
と、前記第１の導体層と前記半導体チップの電極とをつ
なぐ接続手段と、前記第２の導体層にロウ付けされた外
部引き出し用の導体リードとを有し、前記誘電体基板の
一主面上で前記第１の導体層に前記第３の導体層と前記
第４の導体層が接続され、前記誘電体基板の他の主面上
で前記第２の導電層に前記第１の導電層と前記第３の導
電層が接続され、前記第２の導体層と前記外部引き出し
用の導体リードとが接続されていることを特徴とする半
導体装置。1. A first substrate formed on one main surface of a dielectric substrate.
Of the conductor layer, the second conductor layer formed on the other main surface of the dielectric substrate, the third conductor layer formed on the side surface of the dielectric substrate, and penetrating the dielectric substrate. A through hole and a fourth conductor layer formed in the through hole,
A semiconductor chip mounted on one main surface of the dielectric substrate, a connecting means for connecting the first conductor layer and an electrode of the semiconductor chip, and an external lead wire brazed to the second conductor layer. And a third conductor layer and a fourth conductor layer are connected to the first conductor layer on one main surface of the dielectric substrate, and the other main portion of the dielectric substrate is provided. On the surface, the first conductive layer and the third conductive layer are connected to the second conductive layer, and the second conductive layer and the conductor lead for external drawing are connected. Semiconductor device.
JP4256672A 1992-09-25 1992-09-25 Semiconductor device Expired - Fee Related JP2611718B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4256672A JP2611718B2 (en) 1992-09-25 1992-09-25 Semiconductor device
KR1019930019629A KR940008547A (en) 1992-09-25 1993-09-24 High Frequency Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4256672A JP2611718B2 (en) 1992-09-25 1992-09-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0750362A true JPH0750362A (en) 1995-02-21
JP2611718B2 JP2611718B2 (en) 1997-05-21

Family

ID=17295868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4256672A Expired - Fee Related JP2611718B2 (en) 1992-09-25 1992-09-25 Semiconductor device

Country Status (2)

Country Link
JP (1) JP2611718B2 (en)
KR (1) KR940008547A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132748B2 (en) 2002-12-09 2006-11-07 Oki Electric Industry Co., Ltd. Semiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132748B2 (en) 2002-12-09 2006-11-07 Oki Electric Industry Co., Ltd. Semiconductor apparatus

Also Published As

Publication number Publication date
KR940008547A (en) 1994-04-29
JP2611718B2 (en) 1997-05-21

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