JP3426878B2 - Wiring board mounting structure - Google Patents

Wiring board mounting structure

Info

Publication number
JP3426878B2
JP3426878B2 JP30012996A JP30012996A JP3426878B2 JP 3426878 B2 JP3426878 B2 JP 3426878B2 JP 30012996 A JP30012996 A JP 30012996A JP 30012996 A JP30012996 A JP 30012996A JP 3426878 B2 JP3426878 B2 JP 3426878B2
Authority
JP
Japan
Prior art keywords
wiring board
transmission line
semiconductor element
signal transmission
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30012996A
Other languages
Japanese (ja)
Other versions
JPH10144818A (en
Inventor
慎一 郡山
謙治 北澤
幹男 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP30012996A priority Critical patent/JP3426878B2/en
Priority to US08/884,223 priority patent/US5952709A/en
Publication of JPH10144818A publication Critical patent/JPH10144818A/en
Application granted granted Critical
Publication of JP3426878B2 publication Critical patent/JP3426878B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は配線基板の実装構造
に関するもので、特に、マイクロ波帯からミリ波帯領域
の高周波用の半導体素子を収納あるいは搭載するのに好
適な半導体素子収納用パッケ−ジあるいは多層配線基板
等の配線基板を、高周波信号の伝送損失を低減して外部
電気回路基板に実装するための実装構造に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board mounting structure, and more particularly to a semiconductor element housing package suitable for housing or mounting high frequency semiconductor elements in the microwave band to millimeter wave band region. The present invention relates to a mounting structure for mounting a wiring board such as a wiring board or a multilayer wiring board on an external electric circuit board while reducing transmission loss of high frequency signals.

【0002】[0002]

【従来の技術】近年、高度情報化時代を迎え、情報伝達
に用いられる電波は1〜30GHzのマイクロ波領域か
ら、更に30〜300GHzのミリ波領域の周波数まで
活用することが検討されており、例えば、車間レ−ダ−
やオフィス内高速データ通信システム(無線LAN)の
ようなミリ波の電波を用いたさまざまな応用システムも
提案されるようになっている。
2. Description of the Related Art In recent years, in the age of advanced information technology, it has been considered to use radio waves used for information transmission from a microwave range of 1 to 30 GHz to a millimeter range of 30 to 300 GHz. For example, an inter-vehicle radar
Various application systems using millimeter-waves, such as an office high-speed data communication system (wireless LAN), have also been proposed.

【0003】かかる応用システム等に用いられる高周波
用の半導体素子を収納あるいは搭載する配線基板には、
例えば、誘電体から成る絶縁基体と枠体により形成され
た空所に前記半導体素子を収納して気密に封止するとと
もに、高周波端子部分の絶縁と気密封止がされた半導体
素子収納用パッケージが提案されている。
A wiring board for housing or mounting a high frequency semiconductor element used in such an application system,
For example, a semiconductor element housing package in which the semiconductor element is housed and hermetically sealed in a space formed by an insulating base body made of a dielectric material and a frame body, and a high frequency terminal is insulated and hermetically sealed is provided. Proposed.

【0004】しかし、前記構成の半導体素子収納用パッ
ケージへの高周波信号の入出力及び外部電気回路基板へ
の実装は、高周波用の半導体素子と電気的に接続された
ストリップ線路等の信号伝送線路を枠体を通して空所の
内側から外側に引き出し、これを更に絶縁基体の側面を
経由して底面に配設し、該半導体素子収納用パッケージ
の高周波端子と外部電気回路基板の配線層をワイヤーあ
るいはリボン等で接続する必要があり、モジュール製造
時の量産性及び低コスト化に問題があった。
However, for inputting / outputting a high-frequency signal to the package for accommodating a semiconductor element having the above-described structure and mounting it on an external electric circuit board, a signal transmission line such as a strip line electrically connected to the semiconductor element for high frequency is used. It is drawn from the inside of the space to the outside through the frame, and is further arranged on the bottom surface via the side surface of the insulating substrate, and the high frequency terminal of the package for housing the semiconductor element and the wiring layer of the external electric circuit board are wired or ribboned. Therefore, there is a problem in mass productivity and cost reduction during module manufacturing.

【0005】かかる問題を解消するために、表面実装型
の半導体素子収納用パッケージをリフローで一括して実
装し、スルーホール等を用いて半導体素子と信号伝送線
路を接続して高周波信号を伝搬することが提案されてい
るが、前記パッケージの配線層とスルーホールの接続部
分でインピーダンスの不整合と、高周波信号による電磁
界分布の不連続な変化を起こさせてしまうためと考えら
れるが、反射損や放射損が大となり高周波信号の特性劣
化が起こり易くなるという恐れがある。
In order to solve such a problem, surface mounting type semiconductor element accommodating packages are collectively packaged by reflow, and a semiconductor element and a signal transmission line are connected using a through hole or the like to propagate a high frequency signal. It is thought that this is because the impedance mismatch at the connection between the wiring layer of the package and the through hole and the discontinuous change of the electromagnetic field distribution due to the high frequency signal are caused. There is a risk that the radiation loss will be large and the characteristics of the high frequency signal will be easily deteriorated.

【0006】また、前記半導体素子収納用パッケージの
配線層とスルーホールの接続部分の信号による電磁界分
布の不連続性を緩和するために、スルーホールを斜めに
設けて配線層とスルーホールの成す角度を鈍角にするこ
と等も考えられるが、加工性や量産性に難点がある。
In order to alleviate the discontinuity of the electromagnetic field distribution due to the signal at the connection between the wiring layer of the semiconductor element housing package and the through hole, the through hole is obliquely formed to form the wiring layer and the through hole. It may be possible to make the angle obtuse, but there is a problem in workability and mass productivity.

【0007】そこで、図5に示すように半導体素子14
の収納面側と絶縁基体15の底面に信号伝送線路16、
17を形成し、絶縁基体15内部に配設したグランド層
18に設けたスロット孔19を介して高周波信号の入出
力部を電磁結合した半導体素子収納用パッケージが考え
られ、このような半導体素子収納用パッケージを外部電
気回路基板20に実装する際には、その底面に形成され
た信号伝送線路17を外部電気回路基板20の配線層2
1と半田等で接続して実装されている。
Therefore, as shown in FIG.
The signal transmission line 16, on the storage surface side of the
A semiconductor element housing package in which 17 is formed and the high frequency signal input / output portion is electromagnetically coupled through a slot hole 19 provided in the ground layer 18 provided inside the insulating substrate 15 is conceivable. When mounting the package for external electrical circuit board 20, the signal transmission line 17 formed on the bottom surface of the package is mounted on the wiring layer 2 of the external electrical circuit board 20.
1 and is connected by soldering or the like.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、前記実
装構造では、信号の周波数によっては実装部分の接続部
で反射が生じて信号の伝送損失が大となったり、信号の
伝送自体が困難になるという課題があった。
However, in the above-mentioned mounting structure, depending on the frequency of the signal, reflection may occur at the connecting portion of the mounting portion, resulting in a large signal transmission loss or difficulty in signal transmission itself. There were challenges.

【0009】[0009]

【発明の目的】本発明は前記課題を解消せんとして成さ
れたもので、その目的は高周波用の半導体素子を収納あ
るいは搭載するための配線基板を外部電気回路基板に実
装する際、外部電気回路基板への表面実装が可能で、か
つ高周波信号の伝送損失を低減した高周波用の半導体素
子を収納あるいは搭載するのに好適な半導体素子収納用
パッケージや多層配線基板等を外部電気回路基板に実装
した配線基板の実装構造を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to mount an external electric circuit on a wiring board for accommodating or mounting a high frequency semiconductor element on the external electric circuit board. A semiconductor element housing package, multilayer wiring board, etc. suitable for housing or mounting a high frequency semiconductor element capable of surface mounting on a board and reducing transmission loss of high frequency signals are mounted on an external electric circuit board. It is to provide a mounting structure of a wiring board.

【0010】[0010]

【課題を解決するための手段】本発明者等は、前記課題
に鑑み高周波信号の特性劣化を発生することなく外部電
気回路基板への表面実装が可能となる構成について検討
を重ねた結果、半導体素子の搭載面側の絶縁基体表面に
一方の信号伝送線路を形成し、絶縁基体底面には他方の
信号伝送線路を形成せず、外部電気回路基板に形成され
た配線層をもう一方の信号伝送線路とし、それらを電磁
結合させることにより表面実装時における高周波信号の
伝送損失を低減できることを見いだし本発明に至った。
In view of the above-mentioned problems, the inventors of the present invention have made repeated studies on a structure which enables surface mounting on an external electric circuit board without causing deterioration of characteristics of high frequency signals. One signal transmission line is formed on the surface of the insulating substrate on the mounting side of the element, the other signal transmission line is not formed on the bottom surface of the insulating substrate, and the wiring layer formed on the external electric circuit board is used to transmit the other signal. It was found that the transmission loss of a high frequency signal at the time of surface mounting can be reduced by using a line and electromagnetically coupling them, and the present invention has been completed.

【0011】即ち、本発明の配線基板の実装構造は、
電体材料を絶縁基体とする半導体素子を収納あるいは搭
載するための配線基板の表面に、前記半導体素子と電気
的に接続するための第1の信号伝送線路を形成するとと
もに、前記絶縁基体内にスロット孔を有するグランド層
を形成し、一方でかかる配線基板を実装する外部電気回
路基板に形成された配線層を第2の信号伝送線路とし
て、前記配線基板に形成されたグランド層のスロット孔
を介して前記第1の信号伝送線路と第2の信号伝送線路
とを半田等の接着材による接続部を設けることなく電磁
結合するように、前記配線基板を外部電気回路基板の配
線層に実装して成ることを特徴とするものである。
[0011] In other words, the mounting structure of the wiring substrate of the present invention, induction
Stores or mounts semiconductor elements that use an electrical insulator as an insulating substrate.
On the surface of the wiring board for mounting,
To form a first signal transmission line for electrically connecting
A ground layer having slot holes in the insulating substrate
An external electrical circuit to form the
The wiring layer formed on the circuit board is used as the second signal transmission line.
Slot holes in the ground layer formed on the wiring board
Via the first signal transmission line and the second signal transmission line
Electromagnetic waves without the need to provide a connection part with an adhesive such as solder
The wiring board to the external electrical circuit board
It is characterized by being mounted on a line layer .

【0012】また、前記配線基板は、絶縁基体と一体的
に形成され内側に半導体素子を収容する空所を形成する
ための枠体を備えた、あるいは絶縁基体上に搭載した半
導体素子を凹状蓋体により内部に封止した半導体素子収
納用パッケ−ジであることを特徴とするものである。
Further, the wiring board is provided with a frame body integrally formed with the insulating base body for forming a space for accommodating the semiconductor element therein, or a semiconductor element mounted on the insulating base body has a concave lid. The package is a package for housing a semiconductor device, which is sealed inside by a body.

【0013】更に、前記信号伝送線路は、タングステン
(W)やパラジウム(Pd)、Ag、Cu、Au等が使
用できるが、とりわけAg、Cu、Auの内の少なくと
も1種により形成したもので、周波数10GHz以上の
信号が伝送されることを特徴とするものである。
Further, although the signal transmission line may be made of tungsten (W), palladium (Pd), Ag, Cu, Au, etc., it is particularly formed of at least one of Ag, Cu, Au, It is characterized in that a signal having a frequency of 10 GHz or higher is transmitted.

【0014】尚、前記絶縁基体と信号伝送線路は同時焼
成により作製することが望ましいものである。
It is desirable that the insulating substrate and the signal transmission line be manufactured by simultaneous firing.

【0015】[0015]

【作用】本発明によれば、誘電体材料を絶縁基体とする
配線基板に収容あるいは搭載される半導体素子と電気的
に接続された第1の信号伝送線路と、前記配線基板を表
面実装する外部電気回路基板の表面に形成された配線層
を第2の信号伝送線路とで高周波信号を伝送する一対の
信号伝送線路を形成するようにして電磁結合することに
より、前記絶縁基体の第1の信号伝送線路と外部電気回
路基板の配線層から成る第2の信号伝送線路との間には
半田等の接着材による接続部が無く、信号の伝送損失を
更に低減でき、かつ必要な高周波信号を通過伝送するこ
とが可能となる。
According to the present invention, a first signal transmission line electrically connected to a semiconductor element accommodated or mounted in a wiring board having a dielectric material as an insulating base, and an external surface mounting the wiring board. The wiring layer formed on the surface of the electric circuit board is electromagnetically coupled with the second signal transmission line so as to form a pair of signal transmission lines for transmitting a high-frequency signal, so that the first signal of the insulating substrate is formed. There is no connection part between the transmission line and the second signal transmission line composed of the wiring layer of the external electric circuit board by an adhesive such as solder, so that the transmission loss of the signal can be further reduced and the necessary high frequency signal can be passed. It becomes possible to transmit.

【0016】また、高周波信号が伝送される信号伝送線
路をAg、Cu、Au等の電気抵抗の小さな導体材料と
することにより、更に高周波信号の損失を低減でき、そ
の上、これらの導体材料を前記信号伝送線路形成に用い
る場合、絶縁基体や枠体等を構成する誘電体材料をガラ
スセラミック材料により構成すると、伝送線路との同時
焼成が可能となり、その量産性を高めることができ配線
基板として安価に製造することもできる。
Further, by using a conductor material having a small electric resistance such as Ag, Cu or Au for the signal transmission line through which the high frequency signal is transmitted, the loss of the high frequency signal can be further reduced, and further, these conductor materials are used. When used for forming the signal transmission line, if the dielectric material constituting the insulating substrate, the frame body, etc. is made of a glass ceramic material, it can be co-fired with the transmission line, and its mass productivity can be improved, so that it can be used as a wiring board. It can also be manufactured at low cost.

【0017】[0017]

【発明の実施の形態】本発明の配線基板の実装構造を図
面に基づき詳述する。図1は本発明の配線基板を半導体
素子収納用パッケ−ジに適用し、高周波用の半導体素子
を収納して外部電気回路基板に表面実装した実装構造を
示す断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The wiring board mounting structure of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a mounting structure in which a wiring board of the present invention is applied to a package for housing a semiconductor element, a semiconductor element for high frequency is housed and surface-mounted on an external electric circuit board.

【0018】図1において、1は絶縁基体2と、半導体
素子3を収容する空所9を形成するための枠体10と、
絶縁基体2の表面に形成された第1の信号伝送線路4
と、絶縁基体2の内部に設けたスロット孔5を有するグ
ランド層6とから成る半導体素子収納用パッケージを成
す配線基板であり、該配線基板1は外部電気回路基板7
に形成された配線層に表面実装され、配線層が第2の信
号伝送線路8を成している。
In FIG. 1, reference numeral 1 denotes an insulating substrate 2, a frame body 10 for forming a space 9 for accommodating a semiconductor element 3,
First signal transmission line 4 formed on the surface of the insulating base 2.
And a ground layer 6 having a slot hole 5 provided inside the insulating substrate 2, which is a wiring board forming a semiconductor element housing package. The wiring board 1 is an external electric circuit board 7
Surface-mounted on the wiring layer formed on the wiring layer, and the wiring layer forms the second signal transmission line 8.

【0019】前記絶縁基体2の内部には、導体層から成
るグランド層6がほぼ全面に形成され、グランド層6内
には、導体層が形成されないスロット孔5が形成されて
おり、第1の信号伝送線路4と第2の信号伝送線路8と
は、スロット孔5を介して各線路の端部が対峙するよう
に形成されて電磁結合され、損失の小さい信号の伝達が
行われる。尚、スロット孔5はグランド層6に複数個形
成されていても良い。
Inside the insulating substrate 2, a ground layer 6 made of a conductor layer is formed on almost the entire surface, and inside the ground layer 6, a slot hole 5 in which the conductor layer is not formed is formed. The signal transmission line 4 and the second signal transmission line 8 are formed via the slot holes 5 such that the ends of the lines face each other and are electromagnetically coupled to each other to transmit a signal with small loss. A plurality of slot holes 5 may be formed in the ground layer 6.

【0020】本発明によれば、前記空所9内に形成され
る第1の信号伝送線路4としては、周知の伝送線路の組
み合わせによって構成されるが、例えば、マイクロスト
リップ線路やストリップ線路、コプレーナ線路、グラン
ド付コプレーナ線路が絶縁基体2の表面に形成されてい
る。
According to the present invention, the first signal transmission line 4 formed in the void 9 is formed by a combination of well-known transmission lines. For example, a microstrip line, a strip line, or a coplanar line is used. A line and a coplanar line with ground are formed on the surface of the insulating base 2.

【0021】また、前記枠体10の上面には、空所9内
に収納された半導体素子3を外部の雰囲気から保護する
ために、蓋体11がメタライズやガラス等により接合さ
れて空所9を気密に封止しており、通常、蓋体11は電
磁波が外部に漏洩するのを防止するために、例えば各種
セラミック製やNi・Co・Fe合金等の金属製、ある
いはガラスセラミックス等の絶縁材にCu等の金属膜が
被覆された複合材等によって構成され、更に、その材料
中に電磁波を吸収させることができるカーボン等の電磁
波吸収物質を分散させたり、表面に塗布することも可能
である。
A lid 11 is joined to the upper surface of the frame body 10 by metallization, glass or the like in order to protect the semiconductor element 3 housed in the cavity 9 from the external atmosphere, and thus the space 9 is formed. In order to prevent electromagnetic waves from leaking to the outside, the lid 11 is usually made of various ceramics, metal such as Ni / Co / Fe alloy, or insulating such as glass ceramics. It is also possible to dispose an electromagnetic wave absorbing substance such as carbon capable of absorbing an electromagnetic wave in the material, or to coat the surface with a composite material or the like in which the material is coated with a metal film such as Cu. is there.

【0022】図2は、図1の配線基板の空所内の配線を
説明するための図であり、空所9内には半導体素子3と
第1の信号伝送線路4を形成するマイクロストリップ導
体路の他に、半導体素子3に電力を供給するための電源
層13が形成されており、前記マイクロストリップ導体
路及び電源層13の一端は、半導体素子3とリボンやワ
イヤ、TAB等によってそれぞれ電気的に接続され、マ
イクロストリップ導体路の他端は、配線基板1の絶縁基
体2中に形成されたグランド層6に設けたスロット孔5
を介して外部電気回路基板7の配線層である第2の信号
伝送線路8と電磁結合されている。
FIG. 2 is a view for explaining the wiring in the void of the wiring board of FIG. 1, in which the semiconductor element 3 and the first signal transmission line 4 are formed in the void 9. Besides, a power supply layer 13 for supplying electric power to the semiconductor element 3 is formed, and one end of the microstrip conductor path and the power supply layer 13 are electrically connected to the semiconductor element 3 by a ribbon, a wire, a TAB, or the like. And the other end of the microstrip conductor path is connected to the slot hole 5 provided in the ground layer 6 formed in the insulating substrate 2 of the wiring board 1.
Is electromagnetically coupled to the second signal transmission line 8 which is a wiring layer of the external electric circuit board 7 via.

【0023】図3は、本発明の配線基板を、絶縁基体上
に搭載した半導体素子を凹状蓋体により内部に封止する
半導体素子収納用パッケ−ジに適用して外部電気回路基
板に表面実装した実装構造を示す断面図である。尚、図
中、12は凹状蓋体でありその他の符号は図1の符号と
同一である。
FIG. 3 shows a wiring board of the present invention applied to a package for accommodating a semiconductor element in which a semiconductor element mounted on an insulating substrate is sealed inside by a concave lid to be surface-mounted on an external electric circuit board. It is sectional drawing which shows the mounted structure. In the figure, reference numeral 12 is a concave lid, and other reference numerals are the same as those in FIG.

【0024】また、図4は、本発明の配線基板を、絶縁
基体上の配線用電極に半導体素子を直接接続した多層配
線基板に適用して外部電気回路基板に表面実装した実装
構造を示す断面図であり、図中の符号は図3と同様、図
1の符号と同一である。
FIG. 4 is a cross-sectional view showing a mounting structure in which the wiring board of the present invention is applied to a multilayer wiring board in which semiconductor elements are directly connected to wiring electrodes on an insulating substrate and surface-mounted on an external electric circuit board. It is a figure, and the code | symbol in a figure is the same as the code | symbol of FIG. 1 like FIG.

【0025】図1乃至図4において、グランド層6に形
成されたスロット孔5を介して、それぞれの線路の端部
が平均的に必要な伝送信号周波数の1/2波長相当の長
さで重なるような位置に形成されることが望ましく、ス
ロット孔5の形状は、長辺と短辺とから成る長方形や楕
円形状の細長い孔であり、該形状は使用周波数と周波数
の帯域幅を特定することができる。
1 to 4, the ends of the respective lines are overlapped with each other through the slot holes 5 formed in the ground layer 6 by a length corresponding to 1/2 wavelength of the required transmission signal frequency on average. It is desirable that the slot hole 5 be formed in such a position as to be a rectangular or elliptical elongated hole having a long side and a short side, and the shape specifies a frequency to be used and a bandwidth of the frequency. You can

【0026】そのため、スロット孔5の長辺は伝送信号
周波数の1/2波長相当の長さにするのが望ましく、ス
ロット孔5の短辺は1/5波長相当の長さから1/50
波長相当の長さに設定するのが望ましい。
Therefore, it is desirable that the long side of the slot hole 5 has a length corresponding to 1/2 wavelength of the transmission signal frequency, and the short side of the slot hole 5 has a length corresponding to 1/5 wavelength to 1/50.
It is desirable to set the length corresponding to the wavelength.

【0027】尚、半導体素子3は、ストリップ導体路上
に直接収納あるいは搭載することにより、小さな伝送損
失で接続することができるが、前記導体路と半導体素子
3との接続方法はこれに限定されるものではなく、例え
ば、金リボンや複数のワイヤボンディングで接続した
り、ポリイミド等の基板にCu等の導体を形成した導体
板等により接続することもできる。
The semiconductor element 3 can be connected with a small transmission loss by directly housing or mounting it on the strip conductor path, but the method of connecting the conductor path and the semiconductor element 3 is not limited to this. For example, a gold ribbon or a plurality of wire bonds may be used for connection, or a conductor plate in which a conductor such as Cu is formed on a substrate such as polyimide may be used for connection.

【0028】また、本発明の配線基板の絶縁基体として
は、アルミナ(Al2 3 )、ガラスセラミックス、窒
化アルミニウム(AlN)等のセラミックスや有機樹脂
を構成要素とする有機質絶縁材によって構成されるが、
高周波信号の伝送損失を小さくするためには、信号伝送
線路の導体としてAg、Cu、Au等の低抵抗導体を用
いることが望ましく、この点からは前記絶縁基体は焼成
温度が800〜1000℃程度のガラスセラミックスが
最適であり、この組み合わせにより絶縁基体と信号伝送
線路との同時焼成も可能となる。
The insulating substrate of the wiring board of the present invention is made of ceramics such as alumina (Al 2 O 3 ), glass ceramics, aluminum nitride (AlN), or an organic insulating material having organic resin as a constituent element. But,
In order to reduce the transmission loss of high frequency signals, it is desirable to use a low resistance conductor such as Ag, Cu or Au as the conductor of the signal transmission line. From this point, the insulating substrate has a firing temperature of about 800 to 1000 ° C. The glass-ceramic of (1) is most suitable, and this combination also enables simultaneous firing of the insulating substrate and the signal transmission line.

【0029】即ち、前記低抵抗導体を信号伝送線路とし
て採用することにより、周波数が高くなるとその平方根
に比例して増大する導体損を低減でき、従来のAl2
3 とWの組み合わせで同時焼成した場合よりも導体損を
更に低減することが可能となり、特に周波数が10GH
z以上の領域になるとその効果は更に顕著となる。
That is, by adopting the low resistance conductor as a signal transmission line, it is possible to reduce the conductor loss which increases in proportion to the square root of the conventional Al 2 O when the frequency becomes higher.
It is possible to further reduce the conductor loss compared to the case of simultaneous firing with the combination of 3 and W, especially when the frequency is 10 GH.
The effect becomes more remarkable in the region of z or more.

【0030】次に、前記組み合わせにより本発明の配線
基板を製造するには、例えば、ガラスセラミックスを構
成する原料粉末に有機物系のバインダーを混合して調製
した成形材料を、ドクターブレード法やプレス成形法、
圧延法等の周知の成形方法でシート状の成形体を得た
後、該シート状成形体を打ち抜き加工して空所とスルー
ホール等を形成し、次いでAg、Cu、Au等の低抵抗
金属を主体とするペーストを用いて信号伝送線路等の線
路パターンや、スロット孔を形成するグランド層パター
ンを印刷形成する。
Next, in order to manufacture the wiring board of the present invention by the above combination, for example, a molding material prepared by mixing a raw material powder constituting glass ceramics with an organic binder is prepared by a doctor blade method or press molding. Law,
After a sheet-shaped molded body is obtained by a well-known molding method such as a rolling method, the sheet-shaped molded body is punched to form voids and through holes, and then a low resistance metal such as Ag, Cu or Au. A line pattern such as a signal transmission line or a ground layer pattern for forming a slot hole is formed by printing using a paste mainly composed of.

【0031】その後、前記所要パターンを印刷形成した
シート状成形体を位置合わせして複数枚積層し、該積層
体を800〜1000℃の温度で、窒素等の非酸化性雰
囲気中で焼成することにより配線基板が得られる。
After that, a plurality of sheet-shaped compacts on which the required patterns are printed and formed are aligned and laminated, and the laminates are fired at a temperature of 800 to 1000 ° C. in a non-oxidizing atmosphere such as nitrogen. A wiring board is obtained by.

【0032】かくして得られた配線基板の空所内に、半
導体素子をAu・Ge合金等により所定位置に接着固定
した後、ワイヤボンディングやリボンにより信号伝送線
路と電気的に接続し、枠体の上面に蓋体をAu・Si合
金により接着して空所内に半導体素子を気密封止するこ
とにより半導体製品となり、該半導体製品がフッ素樹脂
のような低損失材料から成る外部電気回路基板に表面実
装されることにより半導体装置となる。
After the semiconductor element is adhered and fixed in a predetermined position with Au / Ge alloy or the like in the space of the wiring board thus obtained, it is electrically connected to the signal transmission line by wire bonding or a ribbon, and the upper surface of the frame body. A lid is adhered to the substrate by an Au / Si alloy to hermetically seal the semiconductor element in the cavity to form a semiconductor product, which is surface-mounted on an external electric circuit board made of a low loss material such as fluororesin. As a result, a semiconductor device is obtained.

【0033】[0033]

【実施例】本発明の配線基板の実装構造における高周波
信号の伝送特性を評価するために、誘電率が5.6のガ
ラスセラミック材料を絶縁基体と枠体用材料とし、信号
伝送線路として表1に示す低抵抗金属の導体材料とを組
み合わせたものと、絶縁基体と枠体用材料を誘電率が
8.9のアルミナ材料とし、信号伝送線路としてWとを
組み合わせたものでそれぞれ3層構造の評価用パッケー
ジを作製した。
EXAMPLE In order to evaluate the transmission characteristics of high frequency signals in the mounting structure of the wiring board of the present invention, a glass ceramic material having a dielectric constant of 5.6 was used as the insulating substrate and the frame material, and the signal transmission line is shown in Table 1. The combination of the conductor material of low resistance metal shown in (1) and the combination of the insulating substrate and the frame material made of alumina material having a dielectric constant of 8.9 and W as the signal transmission line have a three-layer structure. An evaluation package was produced.

【0034】この評価用パッケージの電磁結合は、半導
体素子と接続する信号伝送線路としてマイクロストリッ
プラインを採用し、そこから絶縁基体内のグランド層に
形成したスロット孔を介して実装時にストリップライン
になる外部電気回路基板の配線層に結合するものとし
た。
The electromagnetic coupling of this evaluation package employs a microstrip line as a signal transmission line connected to a semiconductor element, and becomes a stripline at the time of mounting through a slot hole formed in the ground layer in the insulating substrate. It should be connected to the wiring layer of the external electric circuit board.

【0035】また、前記外部電気回路基板としては、誘
電率が2.2の厚さ1mmのフッ素樹脂基板を用いた。
As the external electric circuit board, a fluororesin board having a dielectric constant of 2.2 and a thickness of 1 mm was used.

【0036】一方、低抵抗金属の導体材料で信号伝送線
路を形成した評価用パッケージには、評価用の高周波信
号の周波数は20GHzと60GHzに設定し、20G
Hz用には評価用パッケージの信号伝送線路の線路幅を
0.3mm、スロット孔から突き出している部分の長さ
を1.85mmとし、スロット孔の寸法を0.3mm×
4.0mm角に設定した。
On the other hand, in the evaluation package in which the signal transmission line is formed of a conductor material of low resistance metal, the frequency of the high frequency signal for evaluation is set to 20 GHz and 60 GHz,
For Hz, the line width of the signal transmission line of the evaluation package is 0.3 mm, the length of the portion protruding from the slot hole is 1.85 mm, and the dimension of the slot hole is 0.3 mm ×
The size was set to 4.0 mm square.

【0037】また、60GHz用には同様に線路幅を
0.3mm、スロット孔から突き出している部分の長さ
を0.6mmとし、スロット孔の寸法を0.3mm×
1.3mm角に設定した。
Similarly, for 60 GHz, the line width is 0.3 mm, the length of the portion protruding from the slot is 0.6 mm, and the size of the slot is 0.3 mm.
It was set to 1.3 mm square.

【0038】他方、Wで信号伝送線路を形成した評価用
パッケージには、評価用の高周波信号の周波数は60G
Hzに設定し、信号伝送線路の線路幅を0.24mm、
スロット孔から突き出している部分の長さを0.5mm
とし、スロット孔の寸法を0.2mm×1.0mm角に
設定した。
On the other hand, in the evaluation package in which the signal transmission line is formed by W, the frequency of the high frequency signal for evaluation is 60G.
And set the line width of the signal transmission line to 0.24 mm,
The length of the part protruding from the slot hole is 0.5 mm
The dimension of the slot hole was set to 0.2 mm × 1.0 mm square.

【0039】更に、比較のために従来のようにパッケー
ジの底面に高周波信号を受信するための信号伝送線路を
形成したものを、前記評価用パッケージとそれぞれ同一
寸法で作製した。
Further, for comparison, a conventional package having a signal transmission line for receiving a high frequency signal formed on the bottom surface of the package was made to have the same size as that of the evaluation package.

【0040】かくして得られた各評価用パッケージを2
個、前記フッ素樹脂基板に突き合わせて半田で実装し、
ネットワークアナライザーを用いて、一方の評価用パッ
ケージの内部端子から高周波信号を入射してフッ素樹脂
基板上の配線を経由し、もう一方の評価用パッケージの
内部端子に透過してきた伝送信号を計測し、電力比のS
21パラメーター(dB)を算出して評価用パッケージ
の高周波端子1個分の伝送損失を評価した。
Each of the evaluation packages obtained as described above is used as 2
Individually, butted against the fluororesin board and mounted with solder,
Using a network analyzer, measure the transmission signal that entered the high frequency signal from the internal terminal of one evaluation package, passed through the wiring on the fluororesin substrate, and transmitted to the internal terminal of the other evaluation package, Power ratio S
21 parameters (dB) were calculated to evaluate the transmission loss of one high frequency terminal of the evaluation package.

【0041】[0041]

【表1】 [Table 1]

【0042】表1の結果から明らかなように、本発明の
請求範囲外である比較例の試料番号1、3、5、7、
9、11、13、15及び17は、いずれも配線基板底
面に電磁結合により伝送される信号を受信するための伝
送線路を有することから、透過する信号は20GHzで
−1.8dB以下、60GHzで−3.8dB以下であ
るのに対し、本発明では受信のための伝送線路がなく、
外部電気回路基板上の配線層に直接電磁結合させること
により低抵抗導体を用いた試料番号2、4、6、8、1
0、12、14、16では、透過が20GHzで−1.
3dB以上、60GHzで−2.4dB以上、特にW導
体を用いた試料番号18は、その比較例が60GHzで
−5.9であるのに対して−2.5と、いずれも透過信
号が大きくなっていることが分かる。
As is clear from the results shown in Table 1, sample numbers 1, 3, 5, 7 of Comparative Examples, which are outside the scope of the claims of the present invention,
Since 9, 11, 13, 15, and 17 all have a transmission line for receiving a signal transmitted by electromagnetic coupling on the bottom surface of the wiring board, the transmitted signal is 20 GHz at −1.8 dB or less, 60 GHz at 60 GHz. -3.8 dB or less, the present invention does not have a transmission line for reception,
Sample numbers 2, 4, 6, 8 and 1 using low resistance conductors by electromagnetically coupling directly to the wiring layer on the external electric circuit board
For 0, 12, 14, and 16, the transmission is -1.
3 dB or more, -2.4 dB or more at 60 GHz, and in particular, sample No. 18 using the W conductor has a transmission signal of -2.5, while the comparative example is -5.9 at 60 GHz. You can see that

【0043】以上の結果から、前記誘電体材料にAl2
3 を、導体材料にWを用いた場合でも、配線基板底面
に信号伝送線路を設けず、外部電気回路基板上の配線層
に直接電磁結合させた実装構造とすることにより、透過
する信号を大きくすることが可能であり、信号伝送線路
の導体に低抵抗金属を用いれば、Wを用いたメタライズ
に比べて高周波信号の伝送損失を更に低減できることが
分かる。
From the above results, Al 2 was added to the dielectric material.
Even when W is used as the conductor material, O 3 has a mounting structure in which the signal transmission line is not provided on the bottom surface of the wiring board and is electromagnetically coupled directly to the wiring layer on the external electric circuit board. It can be increased, and it can be understood that the transmission loss of the high frequency signal can be further reduced by using the low resistance metal for the conductor of the signal transmission line, as compared with the metallization using W.

【0044】尚、このとき信号の反射を示すS11は、
配線基板底面に伝送線路がある比較例の場合には−10
dB以上であったが、配線基板底面に伝送線路がない本
発明では−10dB未満であった。
At this time, S11 indicating the reflection of the signal is
In the case of the comparative example in which the transmission line is on the bottom surface of the wiring board, -10
Although it was more than dB, it was less than -10 dB in the present invention in which there is no transmission line on the bottom surface of the wiring board.

【0045】このことより、配線基板底面に伝送線路が
ある場合、外部電気回路基板上の配線層との接合により
反射が大きくなり透過する信号が小さくなっていること
が分かる。
From this, it is understood that when the transmission line is on the bottom surface of the wiring board, the reflection with the wiring layer on the external electric circuit board increases and the transmitted signal decreases.

【0046】[0046]

【発明の効果】以上詳述した通り、本発明の配線基板の
実装構造は、半導体素子を収納あるいは搭載する側の絶
縁基体に設けた信号伝送線路と、係る配線基板を表面実
装する外部電気回路基板の配線層とで高周波信号を伝送
する一対の信号伝送線路を形成するようにして電磁結合
したことから、信号の伝送損失を極めて小さなものとし
て表面実装することが可能となり、しかも高周波信号が
伝送される信号伝送線路をAg、Cu、Au等の電気抵
抗の小さな導体材料で形成すれば高周波信号の損失を更
に低減できる上、絶縁基体や枠体を構成する誘電体材料
と伝送線路との同時焼成が可能となり、その量産性を高
めることができ配線基板を安価に製造することが可能と
なる。
As described in detail above, the mounting structure of the wiring board of the present invention has a signal transmission line provided on an insulating substrate on which a semiconductor element is housed or mounted, and an external electric circuit for surface mounting the wiring board. Electromagnetically coupled to form a pair of signal transmission lines that transmit high-frequency signals with the wiring layer of the board, which enables surface mounting with extremely low signal transmission loss, and high-frequency signal transmission. If the signal transmission line to be used is made of a conductor material having a small electric resistance such as Ag, Cu, Au, etc., the loss of high frequency signals can be further reduced, and at the same time, the dielectric material forming the insulating substrate or frame and the transmission line can be simultaneously formed. Baking is possible, mass productivity can be improved, and a wiring board can be manufactured at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線基板を半導体素子収納用パッケ−
ジに適用し、高周波用の半導体素子を収納して外部電気
回路基板に表面実装した実装構造を示す断面図である。
FIG. 1 is a package for storing a semiconductor device in which the wiring board of the present invention is used.
FIG. 9 is a cross-sectional view showing a mounting structure applied to a semiconductor device, housing a high-frequency semiconductor element, and surface-mounting it on an external electric circuit board.

【図2】図1の配線基板の空所内の配線を説明するため
の図である。
FIG. 2 is a diagram for explaining wiring in a void of the wiring board of FIG.

【図3】本発明の配線基板を、絶縁基体上に搭載した半
導体素子を凹状蓋体により内部に封止する半導体素子収
納用パッケ−ジに適用して外部電気回路基板に表面実装
した実装構造を示す断面図である。
FIG. 3 is a mounting structure in which the wiring board of the present invention is applied to a semiconductor element housing package in which a semiconductor element mounted on an insulating base is sealed inside by a concave lid, and is surface-mounted on an external electric circuit board. FIG.

【図4】本発明の配線基板を、絶縁基体上の配線用電極
に半導体素子を直接接続した多層配線基板に適用して外
部電気回路基板に表面実装した実装構造を示す断面図で
ある。
FIG. 4 is a cross-sectional view showing a mounting structure in which the wiring board of the present invention is applied to a multilayer wiring board in which a semiconductor element is directly connected to a wiring electrode on an insulating base and surface-mounted on an external electric circuit board.

【図5】従来の、半導体素子収納面側と絶縁基体の底面
側に信号伝送線路をそれぞれ形成し、絶縁基体中のグラ
ンド層に設けたスロット孔を介して高周波信号の入出力
部を電磁結合する半導体素子収納用パッケージを、外部
電気回路基板に表面実装した実装構造を示す断面図であ
る。
FIG. 5 is a related art in which signal transmission lines are formed on a semiconductor element housing surface side and a bottom surface side of an insulating base, respectively, and a high-frequency signal input / output unit is electromagnetically coupled through a slot hole provided in a ground layer in the insulating base. FIG. 3 is a cross-sectional view showing a mounting structure in which the semiconductor element housing package described above is surface-mounted on an external electric circuit board.

【符号の説明】[Explanation of symbols]

1 配線基板 2 絶縁基体 3 半導体素子 4 第1の信号伝送線路 5 スロット孔 6 グランド層 7 外部電気回路基板 8 第2の信号伝送線路 9 空所 10 枠体 11 蓋体 12 凹状蓋体 1 wiring board 2 Insulating substrate 3 Semiconductor element 4 First signal transmission line 5 slot holes 6 ground layer 7 External electric circuit board 8 Second signal transmission line 9 vacant places 10 frame 11 lid 12 Concave lid

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平6−21253(JP,A) 特開 平6−85099(JP,A) 特開 平8−172141(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-21253 (JP, A) JP-A-6-85099 (JP, A) JP-A-8-172141 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 23/12

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】誘電体材料を絶縁基体とする半導体素子を
収納あるいは搭載するための配線基板の表面に、前記半
導体素子を電気的に接続するための第1の信号伝送線路
を形成するとともに、前記絶縁基体内にスロット孔を有
するグランド層を形成し、一方でかかる配線基板を実装
する外部電気回路基板に形成された配線層を第2の信号
伝送線路として、前記配線基板に形成されたグランド層
のスロット孔を介して前記第1の信号伝送線路と第2の
信号伝送線路とを半田等の接着材による接続部を設ける
ことなく電磁結合するように、前記配線基板を外部電気
回路基板の配線層に実装して成ることを特徴とする配線
基板の実装構造。
1. A first signal transmission line for electrically connecting the semiconductor element is formed on a surface of a wiring board for accommodating or mounting a semiconductor element having a dielectric material as an insulating substrate. A ground layer having a slot hole is formed in the insulating substrate, while a wiring layer formed on an external electric circuit board on which the wiring board is mounted is used as a second signal transmission line, and a ground formed on the wiring board. A connection portion is provided between the first signal transmission line and the second signal transmission line via a slot hole in a layer by an adhesive material such as solder.
A wiring board mounting structure, characterized in that the wiring board is mounted on a wiring layer of an external electric circuit board so as to be electromagnetically coupled without any need .
【請求項2】前記配線基板が、絶縁基体と一体的に形成
され内側に半導体素子を収容する空所を形成するための
枠体を備え、該空所に収納した半導体素子を蓋体により
内部に封止する半導体素子収納用パッケージであること
を特徴とする請求項1記載の配線基板の実装構造。
2. The wiring board is provided with a frame body which is formed integrally with an insulating base body to form a cavity for accommodating a semiconductor element therein, and the semiconductor element accommodated in the cavity is internally covered by a lid body. The mounting structure for a wiring board according to claim 1, which is a package for housing a semiconductor element which is sealed in a package.
【請求項3】前記配線基板が、絶縁基体上に搭載した半
導体素子を凹状蓋体により内部に封止する半導体素子収
納用パッケ−ジであることを特徴とする請求項1記載の
配線基板の実装構造。
3. The wiring board according to claim 1, wherein the wiring board is a package for accommodating a semiconductor element, in which a semiconductor element mounted on an insulating substrate is sealed with a concave lid. Mounting structure.
【請求項4】前記信号伝送線路が銀(Ag)、銅(C
u)及び金(Au)の内の少なくとも1種により形成さ
れていることを特徴とする請求項1乃至請求項3のいず
れかに記載の配線基板の実装構造。
4. The signal transmission line comprises silver (Ag) and copper (C).
The wiring board mounting structure according to any one of claims 1 to 3, wherein the wiring board mounting structure is formed of at least one of u) and gold (Au).
【請求項5】前記信号伝送線路は、周波数10GHz以
上の信号が伝送されることを特徴とする請求項1乃至請
求項4のいずれかに記載の配線基板の実装構造。
5. The wiring board mounting structure according to claim 1, wherein a signal having a frequency of 10 GHz or more is transmitted through the signal transmission line.
JP30012996A 1995-12-28 1996-11-12 Wiring board mounting structure Expired - Fee Related JP3426878B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP30012996A JP3426878B2 (en) 1996-11-12 1996-11-12 Wiring board mounting structure
US08/884,223 US5952709A (en) 1995-12-28 1997-06-27 High-frequency semiconductor device and mounted structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30012996A JP3426878B2 (en) 1996-11-12 1996-11-12 Wiring board mounting structure

Publications (2)

Publication Number Publication Date
JPH10144818A JPH10144818A (en) 1998-05-29
JP3426878B2 true JP3426878B2 (en) 2003-07-14

Family

ID=17881089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30012996A Expired - Fee Related JP3426878B2 (en) 1995-12-28 1996-11-12 Wiring board mounting structure

Country Status (1)

Country Link
JP (1) JP3426878B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4237517B2 (en) * 2003-03-05 2009-03-11 シャープ株式会社 High frequency semiconductor device mounting structure, high frequency transmitter and high frequency receiver using the same
CN100364076C (en) * 2003-09-08 2008-01-23 日月光半导体制造股份有限公司 Bridging chip package structure
JP2010034212A (en) * 2008-07-28 2010-02-12 Toshiba Corp High-frequency ceramic package and method of fabricating the same

Also Published As

Publication number Publication date
JPH10144818A (en) 1998-05-29

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