JP2004134413A

JP2004134413A - Package for housing semiconductor device and semiconductor device

Info

Publication number: JP2004134413A
Application number: JP2002278528A
Authority: JP
Inventors: Yoshiaki Ueda; 植田　義明; Masakazu Yasui; 安井　正和
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2002-08-13
Filing date: 2002-09-25
Publication date: 2004-04-30
Anticipated expiration: 2022-09-25
Also published as: JP4009169B2

Abstract

<P>PROBLEM TO BE SOLVED: To extend a flat part of an I/O terminal in an inside direction of a package for housing a semiconductor element and to eliminate a repeating substrate by effectively preventing a connecting failure to a frame of the I/O terminal or connecting failure of wire bonding due to warpage of the flat plate. <P>SOLUTION: The I/O terminal 3 inserted into a mounting part 2a of the frame 2 is set three times as long as a site 3ab of an outside of the frame 2 in length of a site 3aa of the inside of the frame 2 in a direction parallel to a line conductor 3a-A of the flat plate 3a. An extended part 5 extended to the inside of the frame 2 is formed so as not to arrive at the conductor 3a at both ends A of a standing wall 3b. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、ＦＥＴ等の半導体素子を収納するための半導体素子収納用パッケージおよび半導体装置に関する。
【０００２】
【従来の技術】
従来、マイクロ波帯域やミリ波帯域の高周波信号により作動するＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ：電界効果型トランジスタ）等の半導体素子を収納するための半導体素子収納用パッケージ（以下、半導体パッケージともいう）には、大電力を入力したり、半導体素子と外部電気回路との高周波信号の入出力を行うための入出力端子が設けられている。この半導体パッケージの斜視図を図４に示し、半導体パッケージに用いられる入出力端子の斜視図を図５に示す。
【０００３】
入出力端子１０３は、略長方形の平板部１０３ａの上面に略直方体の立壁部１０３ｂが積層されて成り、一般的にセラミックグリーンシート積層法によって多数個取りの手法を用いて作製され、半導体素子１０９と外部電気回路（図示せず）との高周波信号の入出力を行う機能を有するとともに、半導体パッケージの内外を気密に遮断している。
【０００４】
入出力端子１０３の平板部１０３ａは、アルミナ（Ａｌ_２Ｏ_３）質焼結体，窒化アルミニウム（ＡｌＮ）質焼結体，ムライト（３Ａｌ_２Ｏ_３・２ＳｉＯ_２）質焼結体等の焼結体（セラミックス）から成り、その上面に、一辺から立壁部１０３ｂを挟んで対向する他辺にかけて、タングステン（Ｗ），モリブデン（Ｍｏ）−マンガン（Ｍｎ）等のメタライズ層から成る線路導体１０３ａ−Ａ、および同一面接地導体１０３ａ−Ｂが形成される。平板部１０３ａの下面には、その略全面に線路導体１０３ａ−Ａと同様のメタライズ層から成る下部接地導体１０３ａ−Ｃが形成され、また線路導体１０３ａ−Ａと略平行な両側面には、その中央部に線路導体１０３ａ−Ａと同様のメタライズ層から成る側部接地導体１０３ａ−Ｄが形成されている。
【０００５】
メタライズ層から成る線路導体１０３ａ−Ａ，同一面接地導体１０３ａ−Ｂ，下部接地導体１０３ａ−Ｃ，側部接地導体１０３ａ−Ｄは、Ｗ，Ｍｏ−Ｍｎ等から成る。例えば、Ｗから成る場合、Ｗの粉末を主成分として有機溶剤、溶媒を添加混練して得た金属ペーストを、平板部１０３ａ用のセラミックグリーンシートに予め従来周知のスクリーン印刷法により所定パターンに印刷塗布しておき、これを焼成することにより形成される。
【０００６】
一方、立壁部１０３ｂは、平板部１０３ａと同様のセラミックスから成り、その上面の略全面に線路導体１０３ａ−Ａと同様のメタライズ層から成る上部接地導体１０３ｂ−Ａが形成される。また、平板部１０３ａの線路導体１０３ａ−Ａに略平行な両側面に略面一な立壁部１０３ｂの両側面（両端面）には、その略全面に線路導体１０３ａ−Ａと同様のメタライズ層から成る側部接地導体１０３ｂ−Ｄが、側部接地導体１０３ａ−Ｄに連続して形成される。
【０００７】
メタライズ層から成る上部接地導体１０３ｂ−Ａ，側部接地導体１０３ｂ−Ｄは、平板部１０３ａに形成される線路導体１０３ａ−Ａ等と同様の方法によりセラミックグリーンシートの積層体に所定パターンで印刷塗布しておき、焼成することにより形成される。
【０００８】
この半導体パッケージは、基体１０１と、その上面に接合された枠体１０２と、枠体１０２の側部に嵌着された入出力端子１０３と、枠体１０２上面に接合されたシールリング１０６（図６）とを具備している。基体１０１は、半導体素子１０９を載置する載置部１０１ａを有し、半導体素子１０９の作動時に発する熱を外部に効率よく放散するための銅（Ｃｕ）等の金属または銅−タングステン（Ｗ）等の複合金属材料から成る。枠体１０２は、基体１０１上面の外周部に載置部１０１ａを囲繞するように銀ロウ等のロウ材で接合され、側部に入出力端子１０３を嵌着する取付部１０２ａが形成されたものであり、Ｆｅ−Ｎｉ−Ｃｏ合金やＦｅ−Ｎｉ合金等の金属から成る。
【０００９】
入出力端子１０３の線路導体１０３ａ−Ａに略平行な側面のメタライズ層は、立壁部１０３ｂの両側面の略全面に形成された側部接地導体１０３ｂ−Ｄと、平板部１０３ａの両側面の中央部に形成された側部接地導体１０３ａ−Ｄとから成る。この側面のメタライズ層が入出力端子１０３の側面の中央部に形成されているとともに、平板部１０３ａの上面の両端に位置する同一面接地導体１０３ａ−Ｂと側面のメタライズ層とが電気的に接続されていることにより、同一面接地導体１０３ａ−Ｂによる接地が充分なものとなり、いわゆるコプレナー構造を形成する。そして、このコプレナー構造により線路導体１０３ａ−Ａにおける高周波の伝送特性が良好なものとなる。具体的にはノイズの影響が少ない高周波の伝送が可能となる。
【００１０】
また、リード端子１０４は、線路導体１０３ａ−Ａの枠体１０２外側の部位に銀ロウ等のロウ材を介して接合され、外部電気回路と入出力端子１０３との高周波信号の入出力を行うものであり、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る。シールリング１０６は、枠体１０２上面に銀ロウ等のロウ材で接合され、その上面に蓋体（図示せず）をシーム溶接等により接合するための接合媒体として機能する（例えば、下記の特許文献１参照）。
【００１１】
そして、入出力端子１０３に半導体素子１０９を電気的に接続して半導体パッケージ内に半導体素子１０９を収容するに際して、コンデンサやコイルなどの電子部品を半導体パッケージ内に設置することが近年頻繁に行なわれている。このとき、電子部品との位置関係から半導体素子１０９と入出力端子１０３との距離が大きくならざるを得ないことが多く、例えば、図５に示すように上面に接続用配線１０５ｂを有する中継基板Ｂを半導体素子１０９と入出力端子１０３との間に配設する構成とする。その際、ボンディングワイヤワイヤ１０５ｃによって、半導体素子１０９と接続用配線１０５ｂとの間、接続用配線１０５ｂと入出力端子１０３との間が電気的に接続される。
【００１２】
このような半導体パッケージに、半導体素子１０９を載置部１０１ａに錫（Ｓｎ）−鉛（Ｐｂ）半田等の低融点ロウ材で載置固定するとともに、線路導体１０３ａ−Ａと半導体素子１０９とを中継基板１０５を介して、ボンディングワイヤ１０５ｃで電気的に接続し、次にシールリング１０６上面に蓋体をシーム溶接等により接合することにより、製品としての半導体装置となる。この半導体装置は、例えば半導体素子１０９がＦＥＴであれば、外部電気回路から供給される電力により半導体素子１０９を作動させて外部から入力される大容量の情報を高速で処理し外部に出力するものであり、通信分野に多用されている。
【００１３】
【特許文献１】
特開平１０−２４２７１６号公報（第７−９頁、図１）
【００１４】
【発明が解決しようとする課題】
しかしながら、上記従来の半導体パッケージにおいては、図６に示すように、半導体素子１０９から出力される高周波信号等の電気信号を外部電気回路装置に伝送するには、電気信号はボンディングワイヤ１０５ｃ、中継基板Ｂ上面の接続用配線１０５ｂ、ボンディングワイヤ１０５ｃおよび入出力端子１０３を介して伝送されるため、中継基板Ｂがない従来の半導体パッケージに比して伝送経路において約２倍以上のインダクタンスが生じてしまうという問題点があった。また、その結果、高周波信号の伝送損失が発生したり、ボンディングワイヤ１０５ｃがコイルとして作用して、ボンディングワイヤ１０５ｃから高周波信号が電磁波として漏れたり、外部からのノイズがボンディングワイヤ１０５ｃに入り込んでノイズが増加するといった不具合が発生していた。
【００１５】
そこで、入出力端子１０３の平板部１０３ａを枠体１０２内側に延出させて、その延出部に半導体素子１０９からの電気信号を伝送するボンディングワイヤ１０５ｃを直接接続することによって、中継基板１０５を不要とし、ワイヤボンディング１０５ｃの長さを略１／２とすることが考えられる。しかしながら、平板部１０３ａの枠体１０２内側の部位を延出させない場合の３倍以上に長くすると、平板部１０３ａの下面に形成している下部接地導体１０３ａ−Ｃの収縮率や収縮開始のタイミングなどの収縮挙動と平板部１０３ａを構成する絶縁体の収縮挙動との差により、入出力端子３の平板部３ａに上に凸の反りや下に凸の反りが発生し、そのため入出力端子１０３の接合不良やそれに起因するボンディングワイヤ１０５ｃの接続不良が発生していた。すなわち、下部接地導体１０３ａ−Ｃと略同じ面積で略同じ厚さの導体が、平板部１０３ａの厚さ方向の中心に対して略対称の位置（平板部１０３ａの内部や上面）に形成されていれば、問題が生じることがないが、そのように構成することは高周波の伝送特性上非常に困難である。
【００１６】
従って、本発明は上記従来の問題点に鑑み完成されたものであり、その目的は、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良を有効に防止して、入出力端子の平板部を半導体パッケージの内側方向に延出させた構成とするとともに中継基板を不要とすることである。また、その結果、入出力端子に半導体素子からの信号を伝送するワイヤを直接的に接続できるようにして、半導体素子から伝送される高周波信号の伝送経路において大きなインダクタンスが発生せず、よって高周波信号の伝送特性を良好なものとすることである。さらに、半導体パッケージを小型化することにより高周波信号の電磁波の共振点が低下するのを防ぎ、その結果、半導体パッケージ内部に収容する半導体素子を長期に亘り正常かつ安定に作動させることである。さらに、中継基板を不要とすることにより製造工程を少なくし、効率的に製造できるものとすることである。
【００１７】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子が載置される載置部を有する基体と、該基体の前記上側主面に前記載置部を囲繞するように取着された金属製の枠体と、該枠体の側部に形成された貫通孔または切欠きから成る入出力端子の取付部と、上面に一辺から対向する他辺にかけて形成された線路導体を有する略四角形の誘電体から成る平板部および該平板部の上面に前記線路導体の一部を間に挟んで接合された誘電体から成る立壁部を有する、前記取付部に嵌着された入出力端子とを具備した半導体素子収納用パッケージにおいて、前記入出力端子は、前記平板部の前記線路導体に平行な方向における前記枠体内側の部位の長さが前記枠体外側の部位の長さの３倍以上とされており、前記立壁部の両端部に前記枠体内側に延出する延出部が幅方向で前記線路導体に達しないようにしてそれぞれ形成されていることを特徴とする。
【００１８】
本発明の半導体素子収納用パッケージは、入出力端子は、平板部の線路導体に平行な方向における枠体内側の部位の長さが枠体外側の部位の長さの３倍以上とされており、立壁部の両端部に枠体内側に延出する延出部が幅方向で線路導体に達しないようにしてそれぞれ形成されていることから、平板部における反りの発生が延出部により抑えられ、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良が有効に防止される。また中継基板が不要となるため、半導体素子からの電気信号を伝送するボンディングワイヤを入出力端子の線路導体に直接的に接続でき、半導体素子から出力された高周波信号の伝送経路において大きなインダクタンスが発生せず、よって高周波信号の伝送特性を良好なものとすることができる。さらに、半導体素子収納用パッケージが小型化されることにより、高周波信号の電磁波の共振点が低下するのを防ぐことができ、その結果、半導体素子収納用パッケージ内部に収容する半導体素子を長期に亘り正常かつ安定に作動させることができる。さらに、中継基板が不要となることにより製造工程が少なくなり、効率的に製造できることとなる。
【００１９】
本発明の半導体素子収納用パッケージにおいて、好ましくは、前記延出部は、その幅が前記平板部の上面の前記線路導体に直交する方向の長さの１／６倍乃至１／４倍とされていることを特徴とする。
【００２０】
本発明の半導体素子収納用パッケージは、延出部はその幅が平板部の上面の線路導体に直交する方向の長さの１／６倍乃至１／４倍とされていることから、入出力端子の平板部に反りが発生するのをより有効に防止することができる。その結果、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良がより有効に防止される。
【００２１】
本発明の半導体素子収納用パッケージにおいて、好ましくは、前記平板部の上面で前記線路導体の両側に略等間隔をもって同一面接地導体が形成されており、該同一面接地導体は、前記平板部と前記立壁部との前記線路導体に略平行な側面における境界線に沿って導体非形成部が設けられている。
【００２２】
本発明の半導体素子収納用パッケージは、同一面接地導体は平板部と立壁部との線路導体に略平行な側面における境界線に沿って導体非形成部が形成されていることから、平板部と立壁部との接合面において特に剥離が生じ易い端部で、平板部と立壁部とが同一面接地導体を介することなく密着されるため、接合強度が大きくなって平板部と立壁部との間で剥離が生じ難いものとすることができる。
【００２３】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記載置部に載置固定されるとともに前記入出力端子に電気的に接続された半導体素子と、前記枠体の上面に接合された蓋体とを具備したことを特徴とする。
【００２４】
本発明の半導体装置は、上記の構成により、高周波信号の伝送特性が良好であり半導体素子が長期に亘って安定に作動する、高性能で信頼性の高いものとなる。
【００２５】
【発明の実施の形態】
本発明の半導体素子収納用パッケージを以下に詳細に説明する。図１は本発明の半導体パッケージについて実施の形態の例を示す斜視図、図２は図１の入出力端子の斜視図、図３（ａ）は本発明の半導体パッケージについて実施の形態の他の例を示す入出力端子の透視斜視図、図３（ｂ）は図３（ａ）の要部拡大透視斜視図である。
【００２６】
図１〜図３において、１は基体、１ａは載置部、２は枠体、２ａは入出力端子３の取付部、３は入出力端子、３ａは入出力端子３の平板部、３ａ−Ａは線路導体、３ａ−Ｂは同一面接地導体、３ａ−Ｃは下部接地導体、３ａ−Ｄは側部接地導体、３ｂは立壁部、３ｂ−Ａは上部接地導体、３ｂ−Ｄは側部接地導体、Ａは立壁部３ｂの両端部、４はリード端子、５は立壁部３ｂの延出部、５ａは延出部５の端面、６はシールリングである。これら基体１と枠体２と入出力端子３とシールリング６とで、内部にＦＥＴ等の半導体素子９を収納するための半導体パッケージが基本的に構成される。また、半導体パッケージ内に半導体素子９を収容してシールリング６の上面に蓋体（図示せず）を取着することにより半導体装置となる。
【００２７】
本発明の半導体パッケージは、上側主面に半導体素子９が載置される載置部１ａを有する基体１と、基体１の上側主面に載置部１ａを囲繞するように取着された金属製の枠体２と、枠体２の側部に形成された貫通孔または切欠きから成る入出力端子３の取付部２ａと、上面に一辺から対向する他辺にかけて線路導体３ａ−Ａを有する略四角形の誘電体から成る平板部３ａおよび平板部３ａの上面に線路導体３ａ−Ａの一部を間に挟んで接合された誘電体から成る立壁部３ｂを有する、取付部２ａに嵌着された入出力端子３とを具備した基本構成である。
【００２８】
本発明の基体１は、上側主面に半導体素子９を載置する載置部１ａを有し、半導体素子９を支持する支持部材として機能するとともに、半導体素子９の熱を外部に効率良く放散する機能を有する。この基体１は、その形状は略長方形の平板状であり、Ｆｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗ等の金属、アルミナ，窒化アルミニウム，ムライト等のセラミックスから成る。金属から成る場合、例えば、Ｆｅ−Ｎｉ−Ｃｏ合金のインゴット（塊）に圧延加工や打ち抜き加工等の従来周知の金属加工法を施すことによって所定形状に製作される。また、セラミックスから成る場合、その原料粉末に適当な有機バインダや溶剤等を添加混合しスラリー状と成し、このスラリーをドクターブレード法やカレンダーロール法などの成形法によってセラミックグリーンシートと成し、しかる後、セラミックグリーンシートに適当な打ち抜き加工を施し、これを複数枚積層し焼成することによって作製される。
【００２９】
なお、基体１が金属からなる場合、その表面に耐蝕性に優れかつロウ材との濡れ性に優れる金属、具体的には厚さ０．５〜９μｍのＮｉ層と、厚さ０．５〜５μｍのＡｕ層を順次メッキ法により被着させておくのがよく、基体１が酸化腐蝕するのを有効に防止できるとともに、基体１の載置部１ａに半導体素子９を強固に接着固定させることができる。また、基体１がセラミックスから成る場合、載置部１ａに耐蝕性に優れかつロウ材との濡れ性に優れる金属、具体的には厚さ０．５〜９μｍのＮｉ層と厚さ０．５〜５μｍのＡｕ層を順次メッキ法により被着させておくのがよく、基体１の上側主面の載置部１ａに半導体素子９を強固に接着固定させることができる。
【００３０】
また、基体１の上側主面には、載置部１ａを囲繞するように、側部に入出力端子３を嵌着するための貫通孔または切欠きから成る取付部２ａが形成された枠体２が銀ロウ等のロウ材で接合されており、枠体２の内側に半導体素子９を収納するための空所が形成される。この枠体２は、基体１と同様の金属から成り、箱状体の側壁を成すものであり、その製作は基体１と同様の加工法により、側部に取付部２ａを有する形状に加工される。
【００３１】
なお、枠体２の基体１への接合は、基体１の上側主面と枠体２の下面とを、基体１の上側主面に敷設した適度なボリュームを有するプリフォームとされた銀ロウ等のロウ材を介して接合される。さらに、枠体２の表面には、基体１と同様に厚さ０．５〜９μｍのＮｉ層や厚さ０．５〜５μｍのＡｕ層等の金属層をメッキ法により被着させておくと良い。
【００３２】
また、枠体２の取付部２ａには、半導体素子９と外部電気回路との高周波信号の入出力を行うとともに半導体パッケージの内外を気密に遮断する入出力端子３が、その周囲に設けられているメタライズ層（上部接地導体３ｂ−Ａ、側部接地導体３ａ−Ｄ，３ｂ−Ｄ、下部接地導体３ａ−Ｃ）を介して銀ロウ等のロウ材で接合される。この入出力端子３は、略長方形等の略四角形の平板部３ａの上面に、横倒しにされた四角柱状の立壁部３ｂが積層されて成る。
【００３３】
入出力端子３の平板部３ａおよび立壁部３ｂは、アルミナ，窒化アルミニウム，ムライト等のセラミックスから成る。そして、平板部３ａの上面には、１辺から対向する他辺にかけて、Ｗ，Ｍｏ−Ｍｎ等のメタライズ層から成る線路導体３ａ−Ａが形成され、好ましくは線路導体３ａ−Ａの両側に略等間隔をもって上記メタライズ層から成る同一面接地導体３ａ−Ｂが形成される。これにより、線路導体３ａ−Ａに対する接地が充分なものとなり、いわゆるコプレナー構造を形成するため、線路導体３ａ−Ａにおける高周波信号の伝送特性が向上する。また、平板部３ａの下面の略全面には、線路導体３ａ−Ａと同様のメタライズ層から成る下部接地導体３ａ−Ｃが形成される。
【００３４】
なお、同一面接地導体３ａ−Ｂは、平板部３ａの上面の端（辺）に接するように形成されているのがよい。これにより、線路導体３ａ−Ａに対する接地が良好となり、線路導体３ａ−Ａにおける高周波信号の伝送特性が向上する。また、図３（ａ），（ｂ）に示すように、平板部３ａと立壁部３ｂとの線路導体３ａ−Ａに略平行な側面における境界線に沿って導体非形成部３ｃが設けられていてもよい。これにより、平板部３ａと立壁部３ｂとの接合面において特に剥離が生じ易い端部で、平板部３ａと立壁部３ｂとが同一面接地導体３ａ−Ｂを介することなく密着されるため、接合強度が大きくなって平板部３ａと立壁部３ｂとの間で剥離が生じ難いものとすることができる。
【００３５】
導体非形成部３ｃは、同一面接地導体３ａ−Ｂの幅に対して１／３倍乃至２／３倍の幅とされているのがよい。１／３倍未満であれば、導体非形成部３ｃにおいて平板部３ａと立壁部３ｂとが同一面接地導体３ａ−Ｂを介することなく接合される部分の面積が小さくなって平板部３ａと立壁部３ｂとの間で剥離が生じ易くなり、立壁部３ｂが平板部３ａの反りを抑制する効果が低下し易くなる。また、２／３倍を超えると、同一面接地導体３ａ−Ｂの面積が小さくなって線路導体３ａ−Ａに対する接地が不十分となり、線路導体３ａ−Ａにおける高周波信号（５ＧＨｚ以上）の伝送特性が低下し易くなる。
【００３６】
また、導体非形成部３ｃは、図３（ｂ）に示すように、同一面接地導体３ａ−Ｂと側部接地導体３ａ−Ｄとを電気的に接続する細い線路状の接続部３ｃ−Ａが導体非形成部３ｃを横切るように形成されていてもよい。これにより、平板部３ａと立壁部３ｂとの接合強度を維持することができるとともに、同一面接地導体３ａ−Ｂの接地性を向上させることができる。
【００３７】
接続部３ｃ−Ａは、幅が０．２〜０．５ｍｍとされているのがよい。０．２ｍｍ未満であると、接続部３ｃ−Ａの抵抗が大きくなり、同一面接地導体３ａ−Ｂの接地性の向上は見込めない。また、０．５ｍｍを超えると、導体を介しての平板部３ａと立壁部３ｂとの接合面積が大きくなるために平板部３ａと立壁部３ｂとの接合強度が低下して平板部３ａと立壁部３ｂとが剥離し易くなる。
【００３８】
また、接続部３ｃ−Ａは、合計の面積が導体非形成部３ｃの面積の０．１５〜０．４倍とされているのがよい。０．１５倍未満であると、接続部３ｃ−Ａの抵抗が大きくなり、同一面接地導体３ａ−Ｂの接地性の向上は見込めない。また、０．４倍を超えると、平板部３ａと立壁部３ｂとの間においてセラミック同士の接合面積が充分に確保できなくなり、その為に接合強度が低下して平板部３ａと立壁部３ｂとが剥離し易くなる。
【００３９】
平板部３ａの線路導体３ａ−Ａ、同一面接地導体３ａ−Ｂ、下部接地導体３ａ−Ｃ、側部接地導体３ａ−Ｄ、および接続部３ｃ−ＡはＷ，Ｍｏ−Ｍｎ等のメタライズ層から成る。例えばＷからなる場合、Ｗ粉末を主成分とする金属粉末に有機溶剤、溶媒を添加混合して得た金属ペーストを、平板部３ａ形成用のセラミックグリーンシートに、予め従来周知のスクリーン印刷法により所定パターンに印刷塗布しておき、焼成することによって形成される。
【００４０】
また、平板部３ａの上面には立壁部３ｂが積層される。この立壁部３ｂは、平板部３ａと同様のセラミックスから成り、その上面の延出部５を除く略全面に線路導体３ａ−Ａと同様のメタライズ層から成る上部接地導体３ｂ−Ａが形成され、また側面には側部接地導体３ｂ−Ｄが形成される。さらに、立壁部３ｂの上部接地導体３ｂ−Ａ、側部接地導体３ｂ−Ｄは、平板部３ａに形成される下部接地導体３ａ−Ｃの形成と同様の方法により所定パターンに印刷塗布しておき、焼成することにより形成される。
【００４１】
本発明においては、図２，図３（ａ）に示すように、入出力端子３は、平板部３ａの線路導体３ａ−Ａに平行な方向における枠体２内側の部位の長さが枠体２外側の部位の長さの３倍以上とされており、立壁部３ｂの両端部Ａに枠体２内側に延出する延出部５が幅方向で線路導体３ａ−Ａに達しないようにしてそれぞれ形成されている。延出部５は平板部３ａの上面との間に同一面接地導体３ａ−Ｂを挟持するようにして形成される。このとき、延出部５は、同一面接地導体３ａ−Ｂの幅方向で全面を覆っていてもよく、または幅方向で同一面接地導体３ａ−Ｂの一部が露出していてもよく、いずれの場合でも線路導体３ａ−Ａにおける高周波信号の伝送特性に変わりがないことが確認された。
【００４２】
また、平板部３ａの線路導体３ａ−Ａに略平行な側面からその側面に略面一な立壁部３ｂの側面にかけて、メタライズ層（側部接地導体３ａ−Ｄ，側部接地導体３ｂ−Ｄ）が同一面接地導体３ａ−Ｂや下部接地導体３ａ−Ｃおよび上部接地導体３ｂ−Ａと電気的に接続されて形成される。側部接地導体３ａ−Ｄは、図２に示すように、同一面接地導体３ａ−Ｂが平板部３ａの上面の端（辺）に接するように形成されている場合、側部接地導体３ｂ−Ｄと略同じ幅で側部接地導体３ｂ−Ｄに連続して形成されるのがよい。これにより、入出力端子３を取付部２ａに嵌着させるに際してロウ材の連続したメニスカスの形成を促し、入出力端子３と取付部２ａとの接着性が向上して、気密性の良い構造とすることができる。また、側部接地導体３ａ−Ｄは、図３（ａ），（ｂ）に示すように、導体非形成部３ｃが平板部３ａと立壁部３ｂとの線路導体３ａ−Ａに略平行な側面における境界線に沿って形成されている場合、平板部３ａの線路導体３ａ−Ａに略平行な側面全面に形成されていてもよい。これにより、同一面接地導体３ａ−Ｂに導体非形成部３ｃが形成されていても同一面接地導体３ａ−Ｂと側部接地導体３ａ−Ｄとを電気的に接続することができ、線路導体３ａ−Ａに対する接地が良好となり、線路導体３ａ−Ａにおける高周波信号の伝送特性が向上する。
【００４３】
以上の構成により、入出力端子３の平板部３ａの焼成時において発生する反りを抑制することができ、ワイヤボンディングの接続不良が発生するのを有効に防止できる。また、製造工程において同一面接地導体３ａ−Ｂとなる金属ペーストの印刷層にニジミが発生しても、延出部５によりニジミの広がりが抑制され、線路導体３ａ−Ａと同一面接地導体３ａ−Ｂとの間が短絡することが抑えられる。
【００４４】
また、延出部５の側面においては、浮遊容量の増大を極力少なくするため、立壁部３ｂにおける側部接地導体層３ｂ−Ｄは、延出部５の側面側へ０．２５〜０．３ｍｍ程度延出して形成されていてもよい。このように側部接地導体３ｂ−Ｄを延出部５の側面側へ延出しておくと、入出力端子３を取付部２ａに嵌着させるに際してロウ材によるメニスカスの形成を促すことを可能として、信頼性の良い構造を実現するとともに、浮遊容量の増大がほとんどないようにできる。
【００４５】
本発明において、平板部３ａの線路導体３ａ−Ａに平行な方向における枠体２内側の部位の長さが枠体２外側の部位の長さの３倍以上とされており、これにより、平板部３ａの枠体２内側の部位に中継基板が不要となるため、入出力端子３に直接的に半導体素子９を電気的に接続できる。その結果、半導体素子９から出力された高周波信号の伝送経路において大きなインダクタンスが発生せず、高周波信号の伝送特性を良好なものとできる。
【００４６】
平板部３ａの線路導体３ａ−Ａに平行な方向における枠体２内側の部位３ａａ（図２）の長さが枠体２外側の部位３ａｂ（図２）の長さの３倍未満の場合、平板部３ａに大きな反りがほとんど発生することがなく、延出部５は不要となるが、入出力端子３に接近させて半導体素子９を搭載することが困難となり、中継基板が必要になる。
【００４７】
３倍を超える場合、立壁部３ｂに延出部５がないと、平板部３ａに少なからず反りが発生し、ときには反りが２０μｍを超える場合がある。この場合、入出力端子３を取付部２ａに嵌着するに際してロウ材の厚みにバラツキが発生し、入出力端子３が傾いた状態で取付部２ａに嵌着される。その結果、線路導体３ａ−Ａの枠体２内側の部位にワイヤボンディングした時にその接続不良を誘発させることとなる。しかし、本発明のように、３倍を超える場合に立壁部３ｂに延出部５があると、平板部３ａの反りは大幅に抑制され、その結果、中継基板が不要となる。
【００４８】
本発明において、延出部５は、その幅をｂ（ｍｍ）、平板部３ａの上面の線路導体３ａ−Ａに直交する方向の長さをａ（ｍｍ）としたとき、ａ／６≦ｂ≦ａ／４であることが好ましい。ｂ＜ａ／６であると、平板部３ａの反りを抑制する効果が低下するとともに、同一面接地導体３ａ−Ｂとなる金属ペーストをセラミックグリーンシートに印刷する際に発生するニジミが広がるのを延出部５で抑えることが困難になり、線路導体３ａ−Ａと同一面接地導体３ａ−Ｂとが短絡し易くなる。ｂ＞ａ／４となると、平板部３ａの反りを抑制する効果は十分であるが、線路導体３ａ−Ａの幅を所望の大きさとすることが困難となって抵抗が増大し、高周波信号の伝送遅延や反射が発生し、また大電流の入力用として用いた場合には発熱し易くなる。
【００４９】
また、延出部５の線路導体３ａ−Ａに平行な方向の長さは、平板部３ａの部位３ａａの長さの１／２〜３／４であることが好ましい。１／２未満では、平板部３ａの反りを抑えることが困難になる。３／４を超えると、延出部５が障害になって線路導体３ａ−Ａや同一面接地導体３ａ−Ｂにボンディングワイヤを接続することが困難になる。
【００５０】
また、図２，図３（ａ），（ｂ）に示すように、同一面接地導体３ａ−Ｂは、延出部５に覆われていない露出した部位の長さは延出部５の端面５ａから０．５ｍｍ以上、好ましくは０．７５ｍｍ以上あれば良く、この長さがあれば半導体素子９へのボンディングワイヤを介しての電気的接続が容易となる。
【００５１】
このような半導体パッケージは、半導体素子９を載置部１ａにＳｎ−Ｐｂ半田等の低融点ロウ材で載置固定するとともに、線路導体３ａ−Ａ、同一面接地導体３ａ−Ｂと半導体素子９とをボンディングワイヤで電気的に接続し、シールリング６上面にＦｅ−Ｎｉ−Ｃｏ合金等から成る蓋体（図示せず）をシーム溶接等により接合することにより、製品としての半導体装置となる。この半導体装置は、例えば外部電気回路から供給される高周波信号等の駆動信号によって半導体素子９を作動させ、大容量の情報を高速に伝送する、通信基地局などの通信装置等に用いられる。
【００５２】
【実施例】
本発明の半導体素子収納用パッケージの実施例を以下に説明する。
【００５３】
（実施例１）
まず、立壁部３ｂに延出部５がない従来構成の入出力端子３のサンプルとして、外形寸法が縦４〜７ｍｍ×横４ｍｍ×厚さ１ｍｍでありアルミナセラミックスから成る平板部３ａと、外形寸法が縦１ｍｍ×横４ｍｍ×厚さ１ｍｍでありアルミナセラミックスから成る立壁部３ｂとを有し、厚さ１５μｍで幅が１ｍｍのＷから成る線路導体３ａ−Ａ、線路導体３ａ−Ａと同じ厚さおよび幅のＷから成る同一面接地導体３ａ−Ｂ、厚さ１５μｍのＷから成る下部接地導体３ａ−Ｃ、厚さ１５μｍのＭｏ−Ｍｎから成る側部接地導体３ａ−Ｄ、厚さ１５μｍのＷから成る上部接地導体３ｂ−Ａ、厚さ１５μｍのＭｏ−Ｍｎから成る側部接地導体３ｂ−Ｄを形成して成る入出力端子３を作製した。このとき、平板部３ａの枠体２外側の部位３ａｂの長さを１ｍｍとし、平板部３ａの枠体２内側の部位３ａａの長さを部位３ａｂの２，２．５，３，３．５，４，５（倍）とした６種の入出力端子３を各５個ずつ作製した。
【００５４】
また、本発明の入出力端子３のサンプルとして、上記６種の入出力端子３において、立壁部３ｂに延出部５を設け、延出部５の幅を０．８ｍｍとし、延出部５の端面５ａが平板部３ａの線路方向の端から０．５ｍｍの位置に位置するようにして作製した入出力端子３を各５個用意した。
【００５５】
これらのサンプルについて、平板部３ａの反り（平均値）、ボンディングワイヤの接続状態を評価した。平板部３ａの反りは、平板部３ａの下面の対角線に沿って表面粗さ計で測定した。ボンディングワイヤの接続状態は、接続不可のものや接続不良のもの（傾いた状態で接続されたもの等）がないか調べた。その結果を表１に示す。
【００５６】
なお、表１において、Ｌｒは、平板部３ａの部位３ａｂに対する部位３ａａの比（倍）を示す。
【００５７】
【表１】

【００５８】
表１より、比較例のサンプルでは、平板部３ａの部位３ａｂの長さに対して部位３ａａの長さが３倍以上になると、平板部３ａの反りが大きくなってボンディングワイヤの接続不良が発生した。これに対し、本発明のサンプルでは、平板部３ａの反りが抑制され、ボンディングワイヤの接続状態が大幅に改善されることが判った。また、本発明のサンプルでは、平板部３ａにボンディングワイヤを介して半導体素子９を直接電気的に接続することができ、中継基板が不要となった。
【００５９】
（実施例２）
次に、平板部３ａの部位３ａａの長さを４ｍｍ、部位３ａｂの長さを１ｍｍとし、延出部５の幅を０．４，０．５，０．６，０．６７，０．８，０．９，１，１．１，１．２（ｍｍ）とした９種のサンプルを各５個合計４５個作製して、平板部３ａの反り（平均値）、ボンディングワイヤの接続状態を評価した。平板部３ａの反りの大きさは平均値が１５μｍ未満を良好とし、１５μｍを超える場合を不良とした。評価結果を表２に示す。
【００６０】
【表２】

【００６１】
表２より、本発明のサンプルは、平板部３ａの部位３ａａの長さを部位３ａｂの長さの４倍と長くしても、立壁部３ｂの延出部５の幅を平板部３ａの上面の横の長さ（線路導体３ａ−Ａに直交する方向の長さ）４ｍｍの１／６倍（０．６７ｍｍ）以上とすることにより、平板部３ａの反りを小さくできることが明らかになった。また、延出部５の幅が平板部３ａの上面の横の長さの１／４倍（１ｍｍ）を超えると、キャピラリが延出部５に接触してワイヤボンディングが実施できない場合が発生した。そのため、入出力端子３全体を大きくすることとなり、その場合には半導体パッケージが大型化するという不具合を招来した。
【００６２】
（実施例３）
次に、実施例１で用いた平板部３ａの枠体２内側の部位３ａａの長さが部位３ａｂの２，２．５，３，３．５，４，５（倍）であるとともに、幅が０．８ｍｍで端面５ａが平板部３ａの線路方向の端から０．７ｍｍの位置に位置する延出部５が形成されたサンプルと、新たにこれらの同一面接地導体３ａ−Ｂに導体非形成部３ｃを長さが１．７，２．２，２．７，３．２，３．７，４．７（ｍｍ）であり、幅が０．５ｍｍとなるように作製したサンプルとを各５個用意した。
【００６３】
これらのサンプルについて、−６５〜１２５℃の温度サイクル試験を１０サイクル（１サイクル６０分）実施した後、金属顕微鏡を用いて４０倍に拡大してサンプルを観察することにより延出部５と平板部３ａとの界面における剥離（デラミネーション）の発生率を求め、延出部５と平板部３ａとの接着性の評価をした。これらの評価結果を表３に示す。
【００６４】
【表３】

【００６５】
表３より、導体非形成部３ｃを形成していないサンプルでは、平板部３ａの部位３ａａの長さが部位３ａｂの長さの３倍以上となるとデラミネーションが発生した。これに対し、導体非形成部３ｃを形成したサンプルでは、平板部３ａの部位３ａａの長さが部位３ａｂの長さの５倍でもデラミネーションが発生することなく優れていることが判った。
【００６６】
（実施例４）
次に、実施例２で用いた平板部３ａの部位３ａａの長さが４ｍｍ、部位３ａｂの長さが１ｍｍであるとともに、延出部５の幅が０．４，０．５，０．６，０．６７，０．８，０．９，１，１．１，１．２（ｍｍ）であるサンプルと、新たにこれらの同一面接地導体３ａ−Ｂに導体非形成部３ｃを長さが３．３ｍｍであり、幅が０．５ｍｍとなるように作製したサンプルとを各５個用意した。
【００６７】
これらのサンプルについて、−６５〜１２５℃の温度サイクル試験を１０サイクル（１サイクル６０分）実施した後、金属顕微鏡を用いて４０倍に拡大してサンプルを観察することにより延出部５と平板部３ａとの界面における剥離（デラミネーション）の発生率を求め、延出部５と平板部３ａとの接着性の評価をした。これらの評価結果を表４に示す。
【００６８】
【表４】

【００６９】
表４より、導体非形成部３ｃを形成していないサンプルでは、延出部５の幅が平板部３ａの上面の横の長さの１／４倍（１ｍｍ）未満となるとデラミネーションが発生率した。これに対し、導体非形成部３ｃを形成したサンプルでは、延出部５の幅が平板部３ａの上面の横の長さの１／１０倍（０．４ｍｍ）でもデラミネーションが発生することなく優れていることが判った。
【００７０】
（実施例５）
次に、実施例３で用いた導体非形成部３ｃの長さが１．７，２．２，２．７，３．２，３．７，４．７（ｍｍ）であり幅が０．５ｍｍのサンプルと、新たにこれらの導体非形成部３ｃに、同一面接地導体３ａ−Ｂと側部接地導体３ａ−Ｄとを電気的に接続する幅が０．３ｍｍの接続導体３ｃ−Ａを１５０μｍの間隔を開けて導体非形成部３ｃを横切るように３本設けたサンプルとを各５個用意した。
【００７１】
これらのサンプルについて、ＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）を半導体パッケージ内に実装し、５ＧＨｚの高周波信号を伝送させた際の入出力端子３における高周波信号の反射損失をネットワークアナライザーを用いて測定することにより、高周波信号の伝送性を評価した。これらの評価結果を表５に示す。
【００７２】
【表５】

【００７３】
表５より、導体非形成部３ｃに接続部３ｃ−Ａを設けていないサンプルでは、伝送損失が−２２ｄＢ以上と大きくなった。これに対し、導体非形成部３ｃに接続部３ｃ−Ａを設けたサンプルでは、−２３ｄＢ以下と小さく優れていることが判った。
【００７４】
なお、本発明は上記実施の形態および実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更を施すことは何等差し支えない。例えば、半導体素子９が半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）等の光半導体素子である場合においても本発明の効果は同様であり、その場合は枠体２に光ファイバ取着用の貫通孔を設ければ良い。
【００７５】
【発明の効果】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子が載置される載置部を有する基体と、基体の上側主面に載置部を囲繞するように取着された金属製の枠体と、枠体の側部に形成された貫通孔または切欠きから成る入出力端子の取付部と、上面に一辺から対向する他辺にかけて形成された線路導体を有する略四角形の誘電体から成る平板部および平板部の上面に線路導体の一部を間に挟んで接合された誘電体から成る立壁部を有する、取付部に嵌着された入出力端子とを具備し、入出力端子は、平板部の線路導体に平行な方向における枠体内側の部位の長さが枠体外側の部位の長さの３倍以上とされており、立壁部の両端部に枠体内側に延出する延出部が幅方向で線路導体に達しないようにしてそれぞれ形成されていることにより、平板部における反りの発生が延出部により抑えられ、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良が有効に防止される。また中継基板が不要となるため、入出力端子に直接的に半導体素子を電気的に接続でき、半導体素子から出力された高周波信号の伝送経路において大きなインダクタンスが発生せず、よって高周波信号の伝送特性を良好なものとすることができる。さらに、半導体素子収納用パッケージが小型化されることにより、高周波信号の電磁波の共振点が低下するのを防ぐことができ、その結果、半導体素子収納用パッケージ内部に収容する半導体素子を長期に亘り正常かつ安定に作動させることができる。さらに、中継基板が不要となることにより製造工程が少なくなり、効率的に製造できることとなる。
【００７６】
本発明の半導体素子収納用パッケージは、好ましくは、延出部はその幅が平板部の上面の線路導体に直交する方向の長さの１／６倍〜１／４倍とされていることにより、入出力端子の平板部に反りが発生するのをより有効に防止することができる。その結果、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良がより有効に防止される。
【００７７】
本発明の半導体素子収納用パッケージは、同一面接地導体は平板部と立壁部との線路導体に略平行な側面における境界線に沿って導体非形成部が設けられていることから、平板部と立壁部との接合面において特に剥離が生じ易い端部で、平板部と立壁部とが同一面接地導体を介することなく接着されるため、接合強度が大きくなって平板部と立壁部との間で剥離が生じ難いものとすることができる。
【００７８】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、載置部に載置固定されるとともに入出力端子に電気的に接続された半導体素子と、枠体の上面に接合された蓋体とを具備したことにより、高周波信号の伝送特性が良好であり半導体素子が長期に亘って安定に作動する、高性能で信頼性の高いものとなる。
【図面の簡単な説明】
【図１】本発明の半導体素子収納用パッケージについて実施の形態の例を示す斜視図である。
【図２】図１の半導体素子収納用パッケージにおける入出力端子を示す斜視図である。
【図３】（ａ）は本発明の半導体素子収納用パッケージにおける入出力端子について実施の形態の他の例を示す透視斜視図であり、（ｂ）は図３（ａ）の要部拡大透視斜視図である。
【図４】従来の半導体素子収納用パッケージの斜視図である。
【図５】図４の半導体素子収納用パッケージにおける入出力端子の斜視図である。
【図６】中継基板を設けた従来の半導体素子収納用パッケージの断面図である。
【符号の説明】
１：基体
１ａ：載置部
２：枠体
２ａ：取付部
３：入出力端子
３ａ：平板部
３ａ−Ａ：線路導体
３ａ−Ｂ：同一面接地導体
３ｂ：立壁部
３ｃ：導体非形成部
５：延出部
９：半導体素子
Ａ：立壁部の両端部[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element housing package for housing a semiconductor element such as an FET and a semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor element housing package (hereinafter, also referred to as a semiconductor package) for housing a semiconductor element such as an FET (Field Effect Transistor) operated by a high frequency signal in a microwave band or a millimeter wave band. And an input / output terminal for inputting high power and inputting / outputting a high-frequency signal between the semiconductor element and an external electric circuit. FIG. 4 is a perspective view of the semiconductor package, and FIG. 5 is a perspective view of input / output terminals used in the semiconductor package.
[0003]
The input / output terminal 103 is formed by stacking a substantially rectangular parallelepiped standing wall portion 103b on the upper surface of a substantially rectangular flat plate portion 103a, and is generally manufactured by a ceramic green sheet stacking method using a multi-cavity method. And a function of inputting and outputting high-frequency signals to and from an external electric circuit (not shown), and hermetically shuts off the inside and outside of the semiconductor package.
[0004]
The flat plate portion 103a of the input / output terminal 103 is made of alumina (Al ₂ O ₃ ) Sintered body, aluminum nitride (AlN) sintered body, mullite (3Al ₂ O ₃ ・ 2SiO ₂ ) Made of a sintered body (ceramic) such as a porous sintered body, and the upper surface thereof is made of tungsten (W), molybdenum (Mo) -manganese (Mn), etc. The line conductors 103a-A and the coplanar ground conductors 103a-B made of a metallized layer are formed. A lower ground conductor 103a-C made of the same metallization layer as the line conductor 103a-A is formed on substantially the entire lower surface of the flat plate portion 103a, and on both side surfaces substantially parallel to the line conductor 103a-A. A side ground conductor 103a-D made of the same metallized layer as the line conductor 103a-A is formed at the center.
[0005]
The line conductors 103a-A, the same plane ground conductors 103a-B, the lower ground conductors 103a-C, and the side ground conductors 103a-D made of metallized layers are made of W, Mo-Mn, or the like. For example, when composed of W, a metal paste obtained by adding and kneading an organic solvent and a solvent with a powder of W as a main component is previously printed on a ceramic green sheet for the flat plate portion 103a in a predetermined pattern by a conventionally well-known screen printing method. It is formed by applying and firing this.
[0006]
On the other hand, the standing wall portion 103b is made of the same ceramics as the flat plate portion 103a, and an upper ground conductor 103b-A made of the same metallized layer as the line conductor 103a-A is formed on almost the entire upper surface thereof. Further, on both side surfaces (both end surfaces) of the upright wall portion 103b, which is substantially flush with both side surfaces of the flat plate portion 103a, which are substantially parallel to the line conductor 103a-A, almost the entire surface thereof is formed of the same metallized layer as the line conductor 103a-A. The side ground conductor 103b-D is formed continuously with the side ground conductor 103a-D.
[0007]
The upper ground conductor 103b-A and the side ground conductor 103b-D made of a metallized layer are printed and coated in a predetermined pattern on a laminate of ceramic green sheets by the same method as the line conductor 103a-A formed on the flat plate portion 103a. It is formed by baking.
[0008]
This semiconductor package includes a base 101, a frame 102 bonded to the upper surface thereof, input / output terminals 103 fitted to the sides of the frame 102, and a seal ring 106 bonded to the upper surface of the frame 102 (see FIG. 6). The base 101 has a mounting portion 101a on which the semiconductor element 109 is mounted, and a metal such as copper (Cu) or copper-tungsten (W) for efficiently dissipating heat generated during operation of the semiconductor element 109 to the outside. And the like. The frame body 102 is joined to the outer peripheral portion of the upper surface of the base body 101 with a brazing material such as silver brazing so as to surround the mounting portion 101a, and has a mounting portion 102a for fitting the input / output terminal 103 on a side portion. And made of a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy.
[0009]
The metallized layer on the side surface substantially parallel to the line conductor 103a-A of the input / output terminal 103 is formed by a side ground conductor 103b-D formed on substantially the entire side surface of the standing wall portion 103b and a center of both side surfaces of the flat plate portion 103a. And side ground conductors 103a-D formed in the section. The metallized layer on this side surface is formed at the center of the side surface of the input / output terminal 103, and the same-plane ground conductors 103a-B located at both ends of the upper surface of the flat plate portion 103a are electrically connected to the metallized layer on the side surface. By doing so, the grounding by the coplanar grounding conductors 103a-B becomes sufficient and a so-called coplanar structure is formed. The coplanar structure improves the high-frequency transmission characteristics of the line conductor 103a-A. Specifically, high-frequency transmission with little influence of noise becomes possible.
[0010]
The lead terminal 104 is connected to a portion of the line conductor 103a-A outside the frame 102 via a brazing material such as silver brazing, and performs input / output of a high-frequency signal between an external electric circuit and the input / output terminal 103. And made of a metal such as an Fe—Ni—Co alloy. The seal ring 106 is joined to the upper surface of the frame 102 with a brazing material such as silver brazing, and functions as a joining medium for joining a lid (not shown) to the upper surface by seam welding or the like (for example, the following patent). Reference 1).
[0011]
Recently, when the semiconductor element 109 is electrically connected to the input / output terminal 103 and the semiconductor element 109 is accommodated in the semiconductor package, electronic components such as capacitors and coils are frequently installed in the semiconductor package. ing. At this time, the distance between the semiconductor element 109 and the input / output terminal 103 often has to be increased due to the positional relationship with the electronic component. For example, as shown in FIG. B is provided between the semiconductor element 109 and the input / output terminal 103. At this time, the bonding wire 105c electrically connects the semiconductor element 109 to the connection wiring 105b and the connection wiring 105b to the input / output terminal 103.
[0012]
In such a semiconductor package, the semiconductor element 109 is mounted and fixed on the mounting portion 101a with a low melting point brazing material such as tin (Sn) -lead (Pb) solder, and the line conductor 103a-A and the semiconductor element 109 are connected. A semiconductor device as a product is obtained by electrically connecting with a bonding wire 105c via the relay substrate 105 and then joining a lid to the upper surface of the seal ring 106 by seam welding or the like. If the semiconductor device 109 is, for example, an FET, the semiconductor device operates the semiconductor device 109 with power supplied from an external electric circuit to process large-capacity information input from the outside at high speed and output the information to the outside. And are frequently used in the communication field.
[0013]
[Patent Document 1]
JP-A-10-242716 (pages 7-9, FIG. 1)
[0014]
[Problems to be solved by the invention]
However, in the above-mentioned conventional semiconductor package, as shown in FIG. 6, in order to transmit an electric signal such as a high-frequency signal output from the semiconductor element 109 to an external electric circuit device, the electric signal is transmitted through a bonding wire 105c and a relay board. Since the signal is transmitted via the connection wiring 105b, the bonding wire 105c, and the input / output terminal 103 on the top surface B, about twice or more inductance is generated in the transmission path as compared with the conventional semiconductor package without the relay board B. There was a problem. As a result, a transmission loss of a high-frequency signal occurs, the bonding wire 105c acts as a coil, a high-frequency signal leaks from the bonding wire 105c as an electromagnetic wave, and noise from the outside enters the bonding wire 105c and the noise is reduced. There was a problem such as increase.
[0015]
Therefore, by extending the flat plate portion 103a of the input / output terminal 103 inside the frame body 102 and directly connecting a bonding wire 105c for transmitting an electric signal from the semiconductor element 109 to the extended portion, the relay board 105 is formed. It is conceivable that the length is not required and the length of the wire bonding 105c is reduced to approximately １／. However, if the length of the flat portion 103a inside the frame 102 is not less than three times as long as the lower portion, the lower ground conductor 103a-C formed on the lower surface of the flat portion 103a has a contraction rate and contraction start timing. Of the input / output terminal 3 due to the difference between the contraction behavior of the input / output terminal 3 and the contraction behavior of the insulator constituting the flat portion 103a. The connection failure and the connection failure of the bonding wire 105c resulting therefrom have occurred. That is, a conductor having substantially the same area and substantially the same thickness as the lower grounding conductors 103a-C is formed at a position substantially symmetrical with respect to the center in the thickness direction of the flat plate portion 103a (inside or upper surface of the flat plate portion 103a). If this is the case, no problem arises, but such a configuration is very difficult in terms of high-frequency transmission characteristics.
[0016]
Therefore, the present invention has been completed in view of the above-mentioned conventional problems, and its object is to effectively prevent poor connection of the input / output terminal to the frame and poor connection of wire bonding due to warpage of the flat plate portion, Another object of the present invention is to provide a configuration in which the flat portion of the input / output terminal is extended inward of the semiconductor package and eliminate the need for a relay board. As a result, a wire for transmitting a signal from the semiconductor element can be directly connected to the input / output terminal, so that a large inductance does not occur in a transmission path of the high-frequency signal transmitted from the semiconductor element, and thus the high-frequency signal is not generated. Is to improve the transmission characteristics of the device. Further, by reducing the size of the semiconductor package, it is possible to prevent the resonance point of the electromagnetic wave of the high-frequency signal from lowering, and as a result, to operate the semiconductor element housed inside the semiconductor package normally and stably for a long time. Another object is to eliminate the need for a relay board, thereby reducing the number of manufacturing steps and enabling efficient manufacturing.
[0017]
[Means for Solving the Problems]
The package for housing a semiconductor element of the present invention is attached to a base having a mounting portion on which a semiconductor element is mounted on an upper main surface and to surround the mounting portion on the upper main surface of the base. A substantially square shape having a metal frame, a mounting portion for an input / output terminal formed of a through hole or a notch formed in a side portion of the frame, and a line conductor formed from one side to the opposite side on the upper surface. A flat portion made of a dielectric material, and an input / output terminal fitted to the mounting portion, having an upright wall portion made of a dielectric joined to a top surface of the flat portion with a part of the line conductor interposed therebetween. In the semiconductor device housing package provided, the input / output terminal is such that a length of a portion inside the frame in a direction parallel to the line conductor of the flat plate portion is at least three times a length of a portion outside the frame. And the inside of the frame at both ends of the upright wall portion. Extending portion extending to and characterized by being formed respectively so as not reach the line conductor in the width direction on.
[0018]
In the package for accommodating a semiconductor element of the present invention, the length of the portion inside the frame in the direction parallel to the line conductor of the flat plate portion is at least three times the length of the portion outside the frame in the input / output terminal. Since the extending portions extending to the inside of the frame body at both ends of the standing wall portion are formed so as not to reach the line conductor in the width direction, the occurrence of warpage in the flat plate portion is suppressed by the extending portions. In addition, poor connection of the input / output terminal to the frame due to warpage of the flat plate portion and poor connection of wire bonding can be effectively prevented. Since a relay board is not required, a bonding wire for transmitting an electric signal from the semiconductor element can be directly connected to the line conductor of the input / output terminal, and a large inductance is generated in a transmission path of a high-frequency signal output from the semiconductor element. Therefore, the transmission characteristics of the high-frequency signal can be improved. Further, since the semiconductor device housing package is reduced in size, it is possible to prevent the resonance point of the electromagnetic wave of the high frequency signal from lowering. As a result, the semiconductor device housed inside the semiconductor device housing package can be kept for a long time. It can be operated normally and stably. Further, since the relay board is not required, the number of manufacturing steps is reduced, and the manufacturing can be efficiently performed.
[0019]
In the semiconductor device housing package of the present invention, preferably, the extension has a width that is 1/6 to 1/4 times the length of the upper surface of the flat plate in the direction orthogonal to the line conductor. It is characterized by having.
[0020]
In the package for housing a semiconductor element of the present invention, since the width of the extension is 1/6 to 1/4 of the length in the direction orthogonal to the line conductor on the upper surface of the flat plate, It is possible to more effectively prevent the flat portion of the terminal from being warped. As a result, poor connection of the input / output terminals to the frame and poor connection of wire bonding due to the warpage of the flat plate portion are more effectively prevented.
[0021]
In the package for accommodating a semiconductor element of the present invention, preferably, a coplanar ground conductor is formed at substantially equal intervals on both sides of the line conductor on the upper surface of the flat plate portion. A conductor non-forming portion is provided along a boundary between the upright wall and a side surface substantially parallel to the line conductor.
[0022]
In the package for housing a semiconductor element of the present invention, the grounded conductor on the same plane is formed with a non-conductor portion along a boundary line on a side surface substantially parallel to the line conductor between the flat plate portion and the standing wall portion. At the end where the peeling is particularly likely to occur on the joint surface with the standing wall, the flat plate and the standing wall are in close contact with each other without passing through the ground conductor on the same plane, so that the joining strength is increased and the gap between the flat plate and the standing wall is increased. And hardly causes peeling.
[0023]
The semiconductor device of the present invention includes the semiconductor element housing package of the present invention, a semiconductor element mounted and fixed to the mounting portion and electrically connected to the input / output terminal, and an upper surface of the frame body. And a joined lid.
[0024]
With the above configuration, the semiconductor device of the present invention has good transmission characteristics for high-frequency signals and high performance and high reliability in which the semiconductor element operates stably for a long period of time.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
The package for housing a semiconductor element of the present invention will be described in detail below. FIG. 1 is a perspective view showing an example of an embodiment of a semiconductor package of the present invention, FIG. 2 is a perspective view of an input / output terminal of FIG. 1, and FIG. 3A is another example of an embodiment of the semiconductor package of the present invention. FIG. 3B is an enlarged perspective view of a main part of FIG. 3A, showing an example of an input / output terminal.
[0026]
1 to 3, 1 is a base, 1 a is a mounting portion, 2 is a frame, 2 a is a mounting portion of the input / output terminal 3, 3 is an input / output terminal, 3 a is a flat portion of the input / output terminal 3, 3 a− A is a line conductor, 3a-B is a ground conductor on the same plane, 3a-C is a lower ground conductor, 3a-D is a side ground conductor, 3b is an upright wall portion, 3b-A is an upper ground conductor, and 3b-D is a side portion. A ground conductor, A is both ends of the standing

wall

3b, 4 is a lead terminal, 5 is an extending portion of the standing

wall

3b, 5a is an end face of the extending portion 5, and 6 is a seal ring. The base 1, the frame 2, the input / output terminals 3, and the seal ring 6 basically constitute a semiconductor package for housing a semiconductor element 9 such as an FET therein. A semiconductor device is obtained by accommodating a semiconductor element 9 in a semiconductor package and attaching a lid (not shown) on the upper surface of the seal ring 6.
[0027]
The semiconductor package of the present invention includes a base 1 having a mounting portion 1a on which an semiconductor element 9 is mounted on an upper main surface, and a metal attached to the upper main surface of the base 1 so as to surround the mounting portion 1a. Frame 2, a mounting portion 2a of an input / output terminal 3 formed of a through hole or a notch formed in a side portion of the frame 2, and a line conductor 3a-A on the upper surface from one side to the other opposite side. It is fitted to a mounting portion 2a having a flat portion 3a made of a substantially rectangular dielectric and an upright wall portion 3b made of a dielectric joined to a top surface of the flat portion 3a with a part of the line conductor 3a-A interposed therebetween. This is a basic configuration including input / output terminals 3.
[0028]
The base 1 of the present invention has a mounting portion 1a for mounting the semiconductor element 9 on the upper main surface, functions as a support member for supporting the semiconductor element 9, and efficiently radiates heat of the semiconductor element 9 to the outside. It has a function to do. The substrate 1 has a substantially rectangular flat plate shape and is made of a metal such as an Fe-Ni-Co alloy or Cu-W, or a ceramic such as alumina, aluminum nitride, or mullite. When it is made of a metal, for example, it is manufactured into a predetermined shape by applying a conventionally known metal working method such as rolling or punching to an ingot of an Fe-Ni-Co alloy. In the case of ceramics, an appropriate organic binder and a solvent are added to the raw material powder and mixed to form a slurry, and the slurry is formed into a ceramic green sheet by a forming method such as a doctor blade method or a calender roll method. Thereafter, the ceramic green sheet is manufactured by subjecting the ceramic green sheet to an appropriate punching process, laminating a plurality of the sheets, and firing.
[0029]
When the substrate 1 is made of a metal, a metal having excellent corrosion resistance and excellent wettability with a brazing material on its surface, specifically, a Ni layer having a thickness of 0.5 to 9 μm and a thickness of 0.5 to 9 μm, It is preferable that a 5 μm Au layer is sequentially applied by a plating method, so that oxidation and corrosion of the base 1 can be effectively prevented, and the semiconductor element 9 is firmly adhered and fixed to the mounting portion 1 a of the base 1. Can be. When the base 1 is made of ceramic, the mounting portion 1a is formed of a metal having excellent corrosion resistance and excellent wettability with a brazing material, specifically, a Ni layer having a thickness of 0.5 to 9 μm and a thickness of 0.5 mm. It is preferable that Au layers having a thickness of about 5 μm are sequentially applied by plating, and the semiconductor element 9 can be firmly adhered and fixed to the mounting portion 1 a on the upper main surface of the base 1.
[0030]
In addition, a frame body on the upper main surface of the base 1 is formed a mounting portion 2a formed of a through hole or a notch for fitting the input / output terminal 3 to a side portion so as to surround the mounting portion 1a. 2 is joined by a brazing material such as silver brazing, and a space for accommodating the semiconductor element 9 is formed inside the frame 2. The frame 2 is made of the same metal as the base 1 and forms the side wall of the box-shaped body. The frame 2 is manufactured by the same processing method as the base 1 into a shape having the mounting portion 2a on the side. You.
[0031]
The joining of the frame body 2 to the base body 1 is performed by connecting the upper main surface of the base body 1 and the lower surface of the frame body 2 to a preform having a moderate volume, which is laid on the upper main surface of the base body 1. Are joined via the brazing material. Further, a metal layer such as a Ni layer having a thickness of 0.5 to 9 μm or an Au layer having a thickness of 0.5 to 5 μm is formed on the surface of the frame body 2 by plating, similarly to the base 1. good.
[0032]
An input / output terminal 3 for inputting / outputting a high-frequency signal between the semiconductor element 9 and an external electric circuit and hermetically shutting off the inside and outside of the semiconductor package is provided around the mounting portion 2 a of the frame 2. Through metallized layers (upper ground conductors 3b-A, side ground conductors 3a-D, 3b-D, and lower ground conductors 3a-C). The input / output terminal 3 is formed by stacking an upright quadrangular prism-shaped standing wall portion 3b on the upper surface of a substantially rectangular flat plate portion 3a such as a substantially rectangular shape.
[0033]
The flat plate portion 3a and the vertical wall portion 3b of the input / output terminal 3 are made of ceramics such as alumina, aluminum nitride, and mullite. A line conductor 3a-A made of a metallized layer of W, Mo-Mn or the like is formed on the upper surface of the flat plate portion 3a from one side to the other opposite side, and is preferably formed on both sides of the line conductor 3a-A. The same-surface ground conductors 3a-B made of the metallized layers are formed at regular intervals. Thereby, the grounding to the line conductor 3a-A becomes sufficient, and a so-called coplanar structure is formed, so that the transmission characteristic of the high-frequency signal in the line conductor 3a-A is improved. A lower ground conductor 3a-C made of the same metallized layer as the line conductor 3a-A is formed on substantially the entire lower surface of the flat plate portion 3a.
[0034]
It is preferable that the same-surface ground conductors 3a-B are formed so as to be in contact with an edge (side) of the upper surface of the flat plate portion 3a. Thereby, the grounding of the line conductor 3a-A is improved, and the transmission characteristic of the high-frequency signal in the line conductor 3a-A is improved. As shown in FIGS. 3A and 3B, a conductor non-forming portion 3c is provided along a boundary between a flat plate portion 3a and an upright wall portion 3b on a side surface substantially parallel to the line conductor 3a-A. You may. Accordingly, the flat plate portion 3a and the upright wall portion 3b are brought into close contact with each other at the end where the peeling is particularly likely to occur at the joint surface between the flat plate portion 3a and the upright wall portion 3b without passing through the same-surface ground conductors 3a-B. The strength can be increased, and peeling between the flat plate portion 3a and the standing wall portion 3b is less likely to occur.
[0035]
The width of the non-conductor portion 3c is preferably 1/3 to 2/3 of the width of the ground conductor 3a-B on the same plane. If it is less than 1/3, the area of the portion where the flat plate portion 3a and the standing wall portion 3b are joined in the conductor non-formed portion 3c without passing through the same-surface ground conductors 3a-B becomes small, and the flat plate portion 3a and the standing wall portion 3c become smaller. Separation is likely to occur with the portion 3b, and the effect of the standing wall portion 3b suppressing the warpage of the flat plate portion 3a is likely to decrease. On the other hand, if it exceeds 2/3 times, the area of the same-surface ground conductor 3a-B becomes small and the grounding to the line conductor 3a-A becomes insufficient, and the transmission characteristic of the high-frequency signal (5 GHz or more) in the line conductor 3a-A is obtained. Tends to decrease.
[0036]
As shown in FIG. 3B, the conductor non-formed portion 3c is a thin line-shaped connection portion 3c-A that electrically connects the same-plane ground conductor 3a-B and the side ground conductor 3a-D. May be formed so as to cross the non-conductor-formed portion 3c. Thereby, the joining strength between the flat plate portion 3a and the standing wall portion 3b can be maintained, and the grounding property of the same-surface ground conductors 3a-B can be improved.
[0037]
The connecting portion 3c-A preferably has a width of 0.2 to 0.5 mm. If it is less than 0.2 mm, the resistance of the connection portion 3c-A increases, and the improvement of the grounding properties of the same-surface ground conductors 3a-B cannot be expected. On the other hand, if the thickness exceeds 0.5 mm, the joining area between the flat plate portion 3a and the standing wall portion 3b via the conductor becomes large, so that the joining strength between the flat plate portion 3a and the standing wall portion 3b decreases, and the flat plate portion 3a and the standing wall The portion 3b is easily peeled off.
[0038]
The total area of the connection portions 3c-A is preferably 0.15 to 0.4 times the area of the non-conductor portion 3c. If it is less than 0.15 times, the resistance of the connection portion 3c-A increases, and the improvement of the grounding property of the same-surface ground conductors 3a-B cannot be expected. On the other hand, if it exceeds 0.4 times, it is not possible to secure a sufficient bonding area between the ceramics between the flat plate portion 3a and the standing wall portion 3b, so that the bonding strength is reduced and the flat plate portion 3a and the standing wall portion 3b are not joined together. Are easily peeled off.
[0039]
The line conductor 3a-A, the same plane ground conductor 3a-B, the lower ground conductor 3a-C, the side ground conductor 3a-D, and the connection part 3c-A of the flat plate part 3a are made of metallized layers such as W, Mo-Mn. Become. For example, when composed of W, a metal paste obtained by adding and mixing an organic solvent and a solvent to a metal powder containing W powder as a main component is applied to a ceramic green sheet for forming the flat plate portion 3a in advance by a conventionally known screen printing method. It is formed by printing and applying a predetermined pattern and baking it.
[0040]
An upright wall portion 3b is laminated on the upper surface of the flat plate portion 3a. The vertical wall portion 3b is made of the same ceramics as the flat plate portion 3a, and an upper grounding conductor 3b-A made of the same metallized layer as the line conductor 3a-A is formed on almost the entire surface except the extension 5 on the upper surface thereof. A side ground conductor 3b-D is formed on the side surface. Further, the upper ground conductor 3b-A and the side ground conductor 3b-D of the upright wall 3b are printed and applied in a predetermined pattern by the same method as the formation of the lower ground conductor 3a-C formed on the flat plate 3a. Formed by firing.
[0041]
In the present invention, as shown in FIGS. 2 and 3A, the input / output terminal 3 has a length of a portion inside the frame 2 in a direction parallel to the line conductor 3a-A of the flat plate portion 3a. 2 The length of the outer portion is set to three times or more, and the extending portions 5 extending to the inside of the frame 2 at both ends A of the standing wall portion 3b are prevented from reaching the line conductors 3a-A in the width direction. Each is formed. The extension portion 5 is formed so as to sandwich the same-surface ground conductor 3a-B between the extension portion 5 and the upper surface of the flat plate portion 3a. At this time, the extension portion 5 may cover the entire surface in the width direction of the same-surface ground conductor 3a-B, or may partially expose the same-surface ground conductor 3a-B in the width direction, In any case, it was confirmed that the transmission characteristics of the high-frequency signal in the line conductors 3a-A did not change.
[0042]
The metallized layers (side ground conductors 3a-D and 3b-D) extend from the side surface of the flat plate portion 3a substantially parallel to the line conductor 3a-A to the side surface of the standing wall portion 3b substantially flush with the side surface. Are electrically connected to the same plane ground conductor 3a-B, the lower ground conductor 3a-C, and the upper ground conductor 3b-A. As shown in FIG. 2, the side ground conductor 3a-D is formed when the same-plane ground conductor 3a-B is formed so as to be in contact with an end (side) of the upper surface of the flat plate portion 3a. It is preferable that the width is substantially the same as the width D and is continuously formed on the side ground conductors 3b-D. Accordingly, when the input / output terminal 3 is fitted to the mounting portion 2a, the formation of a continuous meniscus of the brazing material is promoted, the adhesiveness between the input / output terminal 3 and the mounting portion 2a is improved, and a structure having good airtightness is obtained. can do. Further, as shown in FIGS. 3 (a) and 3 (b), the side ground conductors 3a-D have side surfaces substantially parallel to the line conductors 3a-A of the flat plate portion 3a and the vertical wall portion 3b. May be formed on the entire side surface of the flat plate portion 3a substantially parallel to the line conductor 3a-A. Thus, even if the conductor non-formed portion 3c is formed on the same-plane ground conductor 3a-B, the same-plane ground conductor 3a-B and the side ground conductor 3a-D can be electrically connected, and the line conductor Grounding with respect to 3a-A is improved, and the transmission characteristics of high-frequency signals in the line conductor 3a-A are improved.
[0043]
With the above-described configuration, it is possible to suppress the warpage that occurs when the flat plate portion 3a of the input / output terminal 3 is fired, and it is possible to effectively prevent the occurrence of poor connection in wire bonding. Also, even if bleeding occurs in the printed layer of the metal paste that becomes the same-plane ground conductor 3a-B in the manufacturing process, the spread of the bleed is suppressed by the extension portion 5, and the same-plane ground conductor 3a as the line conductor 3a-A -B is suppressed from short-circuiting.
[0044]
In order to minimize the increase in the stray capacitance on the side surface of the extension 5, the side ground conductor layer 3 b -D of the upright wall 3 b is placed 0.25 to 0.3 mm toward the side of the extension 5. It may be formed to extend to the extent. When the side ground conductors 3b-D are extended to the side surface of the extension portion 5 in this manner, it is possible to promote the formation of a meniscus by a brazing material when the input / output terminal 3 is fitted to the attachment portion 2a. In addition, a highly reliable structure can be realized, and the increase in the stray capacitance can be substantially suppressed.
[0045]
In the present invention, the length of the portion inside the frame 2 in the direction parallel to the line conductor 3a-A of the flat plate portion 3a is set to be three times or more the length of the portion outside the frame 2 and thereby, Since a relay board is not required in the portion of the portion 3a inside the frame 2, the semiconductor element 9 can be directly electrically connected to the input / output terminal 3. As a result, a large inductance does not occur in the transmission path of the high-frequency signal output from the semiconductor element 9, and the transmission characteristics of the high-frequency signal can be improved.
[0046]
When the length of the portion 3aa (FIG. 2) inside the frame 2 in the direction parallel to the line conductor 3a-A of the flat plate portion 3a is less than three times the length of the portion 3ab (FIG. 2) outside the frame 2; A large warp hardly occurs in the flat plate portion 3a, and the extension portion 5 becomes unnecessary. However, it becomes difficult to mount the semiconductor element 9 close to the input / output terminal 3, and a relay board is required.
[0047]
If it exceeds three times, if the extending portion 5 is not provided on the upright wall portion 3b, the flat plate portion 3a will be warped to a considerable extent, and sometimes the warp exceeds 20 μm. In this case, when the input / output terminal 3 is fitted to the mounting portion 2a, the thickness of the brazing material varies, and the input / output terminal 3 is fitted to the mounting portion 2a in an inclined state. As a result, when wire bonding is performed on a portion of the line conductor 3a-A inside the frame 2, poor connection is induced. However, as in the present invention, if the extending portion 5 is provided in the upright wall portion 3b when the length exceeds three times, the warpage of the flat plate portion 3a is greatly suppressed, and as a result, the relay board becomes unnecessary.
[0048]
In the present invention, when the width of the extending portion 5 is b (mm) and the length of the upper surface of the flat plate portion 3a in the direction orthogonal to the line conductor 3a-A is a (mm), a / 6 ≦ b It is preferable that ≦ a / 4. If b <a / 6, the effect of suppressing the warpage of the flat plate portion 3a is reduced, and the bleeding generated when the metal paste that becomes the same-plane ground conductor 3a-B is printed on the ceramic green sheet is increased. It becomes difficult to suppress the extension conductor 5 and the line conductor 3a-A and the ground conductor 3a-B are easily short-circuited. When b> a / 4, the effect of suppressing the warpage of the flat plate portion 3a is sufficient, but it is difficult to make the width of the line conductor 3a-A to a desired size, the resistance increases, and the Transmission delay and reflection occur, and when used for inputting a large current, heat is easily generated.
[0049]
Further, the length of the extension 5 in the direction parallel to the line conductor 3a-A is preferably １／ to ／ of the length of the portion 3aa of the flat plate 3a. If it is less than 1/2, it is difficult to suppress the warpage of the flat plate portion 3a. If it exceeds 3/4, the extension 5 becomes an obstacle, and it becomes difficult to connect a bonding wire to the line conductor 3a-A or the same-plane ground conductor 3a-B.
[0050]
As shown in FIGS. 2 and 3A and 3B, the length of the exposed portion of the coplanar ground conductor 3a-B that is not covered by the extension 5 is the end face of the extension 5. The length may be 0.5 mm or more, preferably 0.75 mm or more from 5a. With this length, electrical connection to the semiconductor element 9 via a bonding wire becomes easy.
[0051]
In such a semiconductor package, the semiconductor element 9 is mounted and fixed on the mounting portion 1a with a low melting point brazing material such as Sn-Pb solder, and the line conductor 3a-A, the same plane ground conductor 3a-B and the semiconductor element 9 are mounted. Are electrically connected to each other by a bonding wire, and a lid (not shown) made of an Fe—Ni—Co alloy or the like is joined to the upper surface of the seal ring 6 by seam welding or the like, thereby forming a semiconductor device as a product. This semiconductor device is used in a communication device such as a communication base station that operates a semiconductor element 9 by a driving signal such as a high-frequency signal supplied from an external electric circuit to transmit large-capacity information at a high speed.
[0052]
【Example】
Embodiments of the package for housing a semiconductor element of the present invention will be described below.
[0053]
(Example 1)
First, as a sample of the input / output terminal 3 having a conventional configuration in which the extending portion 5 is not provided on the vertical wall portion 3b, a flat plate portion 3a having an outer dimension of 4 to 7 mm × 4 mm × 1 mm in thickness and made of alumina ceramic, Has a vertical wall 1 mm × 4 mm × thickness 1 mm, an upright wall portion 3 b made of alumina ceramics, has a thickness of 15 μm and a width of 1 mm, and has the same thickness as the line conductors 3 a-A and 3 a-A made of W. And ground conductors 3a-B of width W, lower ground conductors 3a-C of W 15 μm thick, side ground conductors 3a-D of Mo-Mn 15 μm thick, W of 15 μm thickness An input / output terminal 3 was formed by forming an upper ground conductor 3b-A made of and a side ground conductor 3b-D made of Mo-Mn having a thickness of 15 μm. At this time, the length of the portion 3ab outside the frame 2 of the flat plate portion 3a is 1 mm, and the length of the portion 3aa inside the frame 2 of the flat plate portion 3a is 2, 2.5, 3, 3.5 of the portion 3ab. , 4, and 5 (times), five types of input / output terminals 3 were manufactured.
[0054]
In addition, as a sample of the input / output terminal 3 of the present invention, in the above-mentioned six types of input / output terminals 3, the extending portion 5 is provided on the upright wall portion 3b, the width of the extending portion 5 is 0.8 mm, and the extending portion 5 is provided. 5 input / output terminals 3 each prepared such that the end face 5a of the above-mentioned is located at a position of 0.5 mm from the end of the flat plate portion 3a in the line direction.
[0055]
For these samples, the warpage (average value) of the flat plate portion 3a and the connection state of the bonding wires were evaluated. The warpage of the flat plate portion 3a was measured by a surface roughness meter along a diagonal line on the lower surface of the flat plate portion 3a. The connection state of the bonding wires was examined to determine whether there was any connection failure or connection failure (such as a connection in an inclined state). Table 1 shows the results.
[0056]
In Table 1, Lr indicates the ratio (times) of the portion 3aa to the portion 3ab of the flat plate portion 3a.
[0057]
[Table 1]

[0058]
According to Table 1, in the sample of the comparative example, when the length of the portion 3aa is three times or more the length of the portion 3ab of the flat portion 3a, the warpage of the flat portion 3a becomes large, and the connection failure of the bonding wire occurs. did. On the other hand, in the sample of the present invention, it was found that the warpage of the flat plate portion 3a was suppressed, and the connection state of the bonding wires was greatly improved. Moreover, in the sample of the present invention, the semiconductor element 9 can be directly electrically connected to the flat plate portion 3a via the bonding wire, and the relay board is not required.
[0059]
(Example 2)
Next, the length of the portion 3aa of the flat plate portion 3a is 4 mm, the length of the portion 3ab is 1 mm, and the width of the extension portion 5 is 0.4, 0.5, 0.6, 0.67, 0.8. , 0.9, 1, 1.1, 1.2 (mm), and a total of 45 samples of each of five samples were prepared, and the warpage (average value) of the flat plate portion 3a and the connection state of the bonding wires were determined. evaluated. As for the magnitude of the warpage of the flat plate portion 3a, an average value of less than 15 μm was regarded as good, and a case of exceeding 15 μm was regarded as defective. Table 2 shows the evaluation results.
[0060]
[Table 2]

[0061]
As shown in Table 2, the sample of the present invention shows that even when the length of the portion 3aa of the flat portion 3a is set to be four times the length of the portion 3ab, the width of the extending portion 5 of the upright wall portion 3b is increased. It has been clarified that the warpage of the flat plate portion 3a can be reduced by making the horizontal length (length in the direction orthogonal to the line conductors 3a-A) 4 mm or more (0.67 mm) or more. If the width of the extension 5 exceeds 1/4 (1 mm) of the horizontal length of the upper surface of the flat plate 3a, the capillary may contact the extension 5 and wire bonding may not be performed. . As a result, the entire input / output terminal 3 becomes large, in which case the semiconductor package becomes large in size.
[0062]
(Example 3)
Next, the length of the portion 3aa inside the frame 2 of the flat plate portion 3a used in Example 1 is 2,2.5,3,3.5,4,5 (times) that of the portion 3ab and the width. Is 0.8 mm and the end face 5a is formed with the extension 5 whose position is 0.7 mm from the end of the flat plate 3a in the line direction, and a new conductor is added to these same-plane ground conductors 3a-B. A sample in which the forming portion 3c has a length of 1.7, 2.2, 2.7, 3.2, 3.7, 4.7 (mm) and a width of 0.5 mm is used. Five were prepared for each.
[0063]
These samples were subjected to a temperature cycle test at −65 to 125 ° C. for 10 cycles (one cycle of 60 minutes), and then enlarged 40 times using a metallographic microscope to observe the samples. The rate of occurrence of delamination at the interface with the portion 3a was determined, and the adhesion between the extension portion 5 and the flat plate portion 3a was evaluated. Table 3 shows the evaluation results.
[0064]
[Table 3]

[0065]
According to Table 3, in the sample in which the conductor non-formed portion 3c was not formed, delamination occurred when the length of the portion 3aa of the flat plate portion 3a was three times or more the length of the portion 3ab. On the other hand, in the sample in which the non-conductor-formed portion 3c was formed, it was found that even when the length of the portion 3aa of the flat plate portion 3a was five times the length of the portion 3ab, delamination did not occur and was excellent.
[0066]
(Example 4)
Next, the length of the portion 3aa of the flat plate portion 3a used in Example 2 was 4 mm, the length of the portion 3ab was 1 mm, and the width of the extension portion 5 was 0.4, 0.5, 0.6. , 0.67, 0.8, 0.9, 1, 1.1, 1.2 (mm), and a new conductor-free portion 3c on these same-surface ground conductors 3a-B. Was 3.3 mm and five samples each having a width of 0.5 mm were prepared.
[0067]
These samples were subjected to a temperature cycle test at −65 to 125 ° C. for 10 cycles (one cycle of 60 minutes), and then enlarged 40 times using a metallographic microscope to observe the samples. The rate of occurrence of delamination at the interface with the portion 3a was determined, and the adhesion between the extension portion 5 and the flat plate portion 3a was evaluated. Table 4 shows the evaluation results.
[0068]
[Table 4]

[0069]
According to Table 4, in the sample in which the conductor non-formed portion 3c was not formed, when the width of the extension portion 5 was less than １／ (1 mm) of the horizontal length of the upper surface of the flat plate portion 3a, delamination occurred. did. On the other hand, in the sample in which the conductor non-formed portion 3c is formed, no delamination occurs even when the width of the extending portion 5 is 1/10 (0.4 mm) the horizontal length of the upper surface of the flat plate portion 3a. It turned out to be excellent.
[0070]
(Example 5)
Next, the length of the non-conductor-formed portion 3c used in Example 3 was 1.7, 2.2, 2.7, 3.2, 3.7, 4.7 (mm) and the width was 0.3 mm. A connection conductor 3c-A having a width of 0.3 mm for electrically connecting the same-plane ground conductor 3a-B and the side ground conductor 3a-D is newly added to the 5 mm sample and these conductor non-formed portions 3c. Five samples each having three samples provided so as to cross the non-conductor-formed portion 3c at intervals of 150 μm were prepared.
[0071]
For these samples, a FET (Field Effect Transistor) is mounted in a semiconductor package, and the reflection loss of the high frequency signal at the input / output terminal 3 when transmitting a 5 GHz high frequency signal is measured using a network analyzer. The transmission of high frequency signals was evaluated. Table 5 shows the results of these evaluations.
[0072]
[Table 5]

[0073]
According to Table 5, in the sample in which the connection portion 3c-A was not provided in the conductor non-formed portion 3c, the transmission loss was as large as −22 dB or more. On the other hand, in the sample in which the connection portion 3c-A was provided in the non-conductor-formed portion 3c, it was found to be as small as −23 dB or less and excellent.
[0074]
It should be noted that the present invention is not limited to the above embodiments and examples, and various changes may be made without departing from the scope of the present invention. For example, the effect of the present invention is the same even when the semiconductor element 9 is an optical semiconductor element such as a semiconductor laser (LD) and a photodiode (PD). In this case, a through hole for attaching an optical fiber to the frame 2. Should be provided.
[0075]
【The invention's effect】
A semiconductor element storage package according to the present invention includes a base having a mounting portion on which a semiconductor element is mounted on an upper main surface, and a metal metal attached to the upper main surface of the base so as to surround the mounting portion. A frame, a mounting portion of an input / output terminal formed of a through hole or a notch formed in a side portion of the frame, and a substantially rectangular dielectric having a line conductor formed from one side to the other side facing the upper surface. An input / output terminal fitted to the mounting portion, the input / output terminal having a standing wall portion made of a dielectric joined to the upper surface of the flat portion and a portion of the line conductor with a part interposed therebetween. The length of the portion inside the frame in the direction parallel to the line conductor of the flat plate portion is set to be three times or more the length of the portion outside the frame, and extends to the inside of the frame at both ends of the vertical wall portion. The extension is formed so as not to reach the line conductor in the width direction. , Warping of the flat plate portion is restrained by the extending portion, connection failure of the bonding failure or a wire bonding with respect to the frame of the input and output terminals due to warping of the flat plate portion can be effectively prevented. In addition, since a relay board is not required, the semiconductor element can be electrically connected directly to the input / output terminals, and no large inductance is generated in the transmission path of the high-frequency signal output from the semiconductor element. Can be improved. Further, since the semiconductor device housing package is reduced in size, it is possible to prevent the resonance point of the electromagnetic wave of the high frequency signal from lowering. As a result, the semiconductor device housed inside the semiconductor device housing package can be kept for a long time. It can be operated normally and stably. Further, since the relay board is not required, the number of manufacturing steps is reduced, and the manufacturing can be efficiently performed.
[0076]
In the semiconductor device housing package of the present invention, preferably, the width of the extension portion is 1/6 to 1/4 times the length in the direction orthogonal to the line conductor on the upper surface of the flat plate portion. In addition, it is possible to more effectively prevent the flat portion of the input / output terminal from being warped. As a result, poor connection of the input / output terminals to the frame and poor connection of wire bonding due to the warpage of the flat plate portion are more effectively prevented.
[0077]
In the package for housing a semiconductor element of the present invention, the grounded conductor on the same plane is provided with a conductor non-formed portion along a boundary line on a side surface substantially parallel to the line conductor between the flat plate portion and the standing wall portion. At the end where the peeling is particularly likely to occur at the joint surface with the standing wall, the flat plate and the standing wall are bonded without passing through the ground conductor on the same plane. And hardly causes peeling.
[0078]
The semiconductor device of the present invention is joined to the semiconductor device housing package of the present invention, a semiconductor element mounted and fixed on the mounting portion and electrically connected to the input / output terminals, and an upper surface of the frame. The provision of the lid makes it possible to obtain high-performance and high-reliability semiconductor devices that have good transmission characteristics of high-frequency signals and operate stably for a long period of time.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an example of an embodiment of a package for housing a semiconductor element of the present invention.
FIG. 2 is a perspective view showing input / output terminals in the semiconductor element housing package of FIG. 1;
3A is a perspective view showing another example of the embodiment of the input / output terminals in the package for housing a semiconductor element of the present invention, and FIG. 3B is an enlarged perspective view of a main part of FIG. 3A; It is a perspective view.
FIG. 4 is a perspective view of a conventional package for housing a semiconductor element.
FIG. 5 is a perspective view of input / output terminals in the semiconductor element housing package of FIG. 4;
FIG. 6 is a sectional view of a conventional semiconductor element housing package provided with a relay substrate.
[Explanation of symbols]
1: Substrate
1a: Receiver
2: Frame
2a: mounting part
3: Input / output terminal
3a: flat part
3a-A: line conductor
3a-B: ground conductor on the same plane
3b: standing wall
3c: non-conductive portion
5: Extension
9: Semiconductor element
A: Both ends of the standing wall

Claims

A base having a mounting portion on which a semiconductor element is mounted on an upper main surface; a metal frame attached to the upper main surface of the base so as to surround the mounting portion; and the frame A flat portion made of a substantially rectangular dielectric having a through-hole or a notch mounting portion formed on a side portion of the I / O terminal and a line conductor formed on one side from the other side to the other side; A semiconductor device housing package having an input / output terminal fitted to the mounting portion, the package having an upright wall portion made of a dielectric joined to the upper surface of the portion with a part of the line conductor interposed therebetween; The writing output terminal is configured such that a length of a portion inside the frame in a direction parallel to the line conductor of the flat plate portion is at least three times a length of a portion outside the frame, and both ends of the upright wall portion An extending portion extending inside the frame body extends in the width direction so that the line guide extends in the width direction. Package for housing semiconductor chip, characterized in that it is formed respectively manner not reach.

2. The semiconductor according to claim 1, wherein the extension has a width that is １／ to ４ times a length in a direction orthogonal to the line conductor on the upper surface of the flat plate. 3. Device storage package.

On the upper surface of the flat plate portion, ground conductors on the same plane are formed on both sides of the line conductor at substantially equal intervals, and the ground conductors on the same plane are substantially parallel to the line conductors of the flat plate portion and the vertical wall portion. 3. The package for accommodating a semiconductor element according to claim 1, wherein a conductor-free portion is provided along a boundary line in the above.

4. The semiconductor element storage package according to claim 1, a semiconductor element mounted and fixed to the mounting portion and electrically connected to the input / output terminal, and A semiconductor device comprising: a lid joined to an upper surface.