JPH07500455A - 絶縁体における電荷蓄積に起因するフィールドインバージョンの抑制に関する構造 - Google Patents
絶縁体における電荷蓄積に起因するフィールドインバージョンの抑制に関する構造Info
- Publication number
- JPH07500455A JPH07500455A JP5507222A JP50722293A JPH07500455A JP H07500455 A JPH07500455 A JP H07500455A JP 5507222 A JP5507222 A JP 5507222A JP 50722293 A JP50722293 A JP 50722293A JP H07500455 A JPH07500455 A JP H07500455A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- integrated circuit
- amorphous silicon
- electrical devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009825 accumulation Methods 0.000 title 1
- 239000012212 insulator Substances 0.000 title 1
- 239000010410 layer Substances 0.000 claims description 121
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 238000001465 metallisation Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 10
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 7
- 238000000926 separation method Methods 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000006386 neutralization reaction Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- GVGLGOZIDCSQPN-PVHGPHFFSA-N Heroin Chemical compound O([C@H]1[C@H](C=C[C@H]23)OC(C)=O)C4=C5[C@@]12CCN(C)[C@@H]3CC5=CC=C4OC(C)=O GVGLGOZIDCSQPN-PVHGPHFFSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000012085 test solution Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/91—Controlling charging state at semiconductor-insulator interface
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/958—Passivation layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (7)
- 1.基板と、前記基板上に形成された複数の電気的デバイスと、前記電気的デバ イスのそれぞれの間に与えられた分離手段と、前記電気的デバイスを相互接続す る少なくとも一つのメタリゼーション層と、前記メタリゼーション層に隣接して 配置された第1の絶縁層と、前記絶縁層の真下のアモルファスシリコンの層とを 備えることを特徴とする集積回路。
- 2.前記第1の絶縁層の上にアモルファスシリコンの層を更に備えることを特徴 とする請求項1に記載の集積回路。
- 3.上部及び下部酸化層を更に備え、前記第1の絶縁層は、前記上部及び下部酸 化層の間に配置されたスピンーオンーガラス層であることを特徴とする請求項1 に記載の集積回路。
- 4.前記第1の絶縁層は、前記分離手段の頂部に形成されたBPSG層であるこ とを特徴とする請求項1に記載の集積回路。
- 5.前記第1の絶縁層の上にアモルファスシリコンの層を更に備えることを特徴 とする請求項3に記載の集積回路。
- 6.前記第1の絶縁層の上にアモルファスシリコンの層を更に備えることを特徴 とする請求項4に記載の集積回路。
- 7.基板上に複数の電気的デバイスを形成し、前記電気的デバイスの間で当該電 気的デバイスを電気的に分離する分離手段を形成し、前記分離手段上に第1の絶 縁層を形成し、前記絶縁層上にメタリゼーション層を付与し、前記メタリゼーシ ョン層上に第2の絶縁層を付与し、前記第1または第2の絶縁層のいずれかの真 下にアモルファスシリコンの層を形成する段階を具備することを特徴とする集積 回路の形成方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/775,085 US5374833A (en) | 1990-03-05 | 1991-10-11 | Structure for suppression of field inversion caused by charge build-up in the dielectric |
US775,085 | 1991-10-11 | ||
PCT/US1992/008657 WO1993007644A1 (en) | 1991-10-11 | 1992-10-09 | Structure for suppression of field inversion caused by charge build-up in the dielectric |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07500455A true JPH07500455A (ja) | 1995-01-12 |
JP3678423B2 JP3678423B2 (ja) | 2005-08-03 |
Family
ID=25103284
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50722293A Expired - Fee Related JP3678423B2 (ja) | 1991-10-11 | 1992-10-09 | 絶縁体における電荷蓄積に起因するフィールドインバージョンの抑制に関する構造 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5374833A (ja) |
EP (1) | EP0608335B1 (ja) |
JP (1) | JP3678423B2 (ja) |
DE (1) | DE69233604T2 (ja) |
WO (1) | WO1993007644A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5763937A (en) * | 1990-03-05 | 1998-06-09 | Vlsi Technology, Inc. | Device reliability of MOS devices using silicon rich plasma oxide films |
KR960015322B1 (ko) * | 1993-07-23 | 1996-11-07 | 현대전자산업 주식회사 | 차폐용 플레이트를 갖는 반도체소자 제조방법 |
US5534731A (en) * | 1994-10-28 | 1996-07-09 | Advanced Micro Devices, Incorporated | Layered low dielectric constant technology |
KR19980055721A (ko) * | 1996-12-28 | 1998-09-25 | 김영환 | 반도체 소자의 보호막 형성 방법 |
US5825068A (en) * | 1997-03-17 | 1998-10-20 | Integrated Device Technology, Inc. | Integrated circuits that include a barrier layer reducing hydrogen diffusion into a polysilicon resistor |
US6100572A (en) * | 1997-03-20 | 2000-08-08 | International Rectifier Corp. | Amorphous silicon combined with resurf region for termination for MOSgated device |
US6166428A (en) * | 1997-08-25 | 2000-12-26 | Advanced Micro Devices, Inc. | Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon |
US6376359B1 (en) * | 1998-03-18 | 2002-04-23 | United Microelectronics Corp. | Method of manufacturing metallic interconnect |
US8536659B2 (en) * | 2009-07-30 | 2013-09-17 | Polar Seminconductor, Inc. | Semiconductor device with integrated channel stop and body contact |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS497870B1 (ja) * | 1969-06-06 | 1974-02-22 | ||
JPS5819129B2 (ja) * | 1975-12-10 | 1983-04-16 | 株式会社東芝 | ハンドウタイソウチノ セイゾウホウホウ |
DE2932569C2 (de) * | 1979-08-10 | 1983-04-07 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen |
GB2071411B (en) * | 1980-03-07 | 1983-12-21 | Philips Electronic Associated | Passivating p-n junction devices |
JPS584948A (ja) * | 1981-06-30 | 1983-01-12 | Fujitsu Ltd | 半導体装置 |
US4688078A (en) * | 1982-09-30 | 1987-08-18 | Ning Hseih | Partially relaxable composite dielectric structure |
US4502202A (en) * | 1983-06-17 | 1985-03-05 | Texas Instruments Incorporated | Method for fabricating overlaid device in stacked CMOS |
JPS6030153A (ja) * | 1983-07-28 | 1985-02-15 | Toshiba Corp | 半導体装置 |
US4555300A (en) * | 1984-02-21 | 1985-11-26 | North American Philips Corporation | Method for producing single crystal layers on insulators |
CA1252372A (en) * | 1985-01-21 | 1989-04-11 | Joseph P. Ellul | Nitsinitride and oxidized nitsinitride dielectrics on silicon |
US4732801A (en) * | 1986-04-30 | 1988-03-22 | International Business Machines Corporation | Graded oxide/nitride via structure and method of fabrication therefor |
US4810673A (en) * | 1986-09-18 | 1989-03-07 | Texas Instruments Incorporated | Oxide deposition method |
US4972250A (en) * | 1987-03-02 | 1990-11-20 | Microwave Technology, Inc. | Protective coating useful as passivation layer for semiconductor devices |
KR920000077B1 (ko) * | 1987-07-28 | 1992-01-06 | 가부시키가이샤 도시바 | 반도체장치의 제조방법 |
US5366921A (en) * | 1987-11-13 | 1994-11-22 | Canon Kabushiki Kaisha | Process for fabricating an electronic circuit apparatus |
JPH01283838A (ja) * | 1988-05-10 | 1989-11-15 | Toshiba Corp | 半導体装置 |
US5272361A (en) * | 1989-06-30 | 1993-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Field effect semiconductor device with immunity to hot carrier effects |
US5047826A (en) * | 1989-06-30 | 1991-09-10 | Texas Instruments Incorporated | Gigaohm load resistor for BICMOS process |
JP3082923B2 (ja) * | 1989-12-26 | 2000-09-04 | ソニー株式会社 | 半導体装置の製法 |
US5128279A (en) * | 1990-03-05 | 1992-07-07 | Vlsi Technology, Inc. | Charge neutralization using silicon-enriched oxide layer |
US5057897A (en) * | 1990-03-05 | 1991-10-15 | Vlsi Technology, Inc. | Charge neutralization using silicon-enriched oxide layer |
US5290727A (en) * | 1990-03-05 | 1994-03-01 | Vlsi Technology, Inc. | Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors |
US5003062A (en) * | 1990-04-19 | 1991-03-26 | Taiwan Semiconductor Manufacturing Co. | Semiconductor planarization process for submicron devices |
US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
-
1991
- 1991-10-11 US US07/775,085 patent/US5374833A/en not_active Expired - Lifetime
-
1992
- 1992-10-09 WO PCT/US1992/008657 patent/WO1993007644A1/en active IP Right Grant
- 1992-10-09 JP JP50722293A patent/JP3678423B2/ja not_active Expired - Fee Related
- 1992-10-09 EP EP92921971A patent/EP0608335B1/en not_active Expired - Lifetime
- 1992-10-09 DE DE69233604T patent/DE69233604T2/de not_active Expired - Lifetime
-
1994
- 1994-09-28 US US08/314,425 patent/US5492865A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0608335A4 (en) | 1994-11-17 |
DE69233604D1 (de) | 2006-05-04 |
EP0608335A1 (en) | 1994-08-03 |
US5374833A (en) | 1994-12-20 |
US5492865A (en) | 1996-02-20 |
DE69233604T2 (de) | 2007-01-18 |
WO1993007644A1 (en) | 1993-04-15 |
JP3678423B2 (ja) | 2005-08-03 |
EP0608335B1 (en) | 2006-03-08 |
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