JPH0745834A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress hot carrier deterioration of a polysilicon thin film transistor to be used for an active matrix liquid crystal display. CONSTITUTION:A drain n<-> type region 8 10<18>/cm<3> less than 10<19>/cm<3> in concentration of is formed adjacently to a drain n<+> type region 3 10<19>/cm<3> or more in concentration for a polysilicon thin film transistor. As a result, an electric field at a drain end is alleviated, and deterioration by hot carrier is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in an active matrix liquid crystal display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, active matrix liquid crystal displays have been widely used in liquid crystal televisions, liquid crystal viewfinders for video movies, display devices for notebook personal computers and the like. Polysilicon thin film transistors have been widely applied to active matrix liquid crystal displays. The polysilicon thin film transistor is a MOS transistor formed by using a thin film on an insulating substrate.

FIG. 3 shows a cross section of a conventional polysilicon thin film transistor. 1 is an insulating glass substrate, 2 is a source n ⁺ formed by phosphorus ion implantation
Similarly to the source, the region 3 is a drain n ⁺ region formed by phosphorus ion implantation, 4 is a gate electrode, 5 is a gate oxide film, and 6 is a channel region. Channel area 6
Is usually undoped.

A conventional method of manufacturing a polysilicon thin film transistor will be described with reference to FIG. In the step of FIG. 4A, the SiO ₂ film 9 is formed on the glass substrate 1, and then the first polysilicon film 10 is formed. Then, the first polysilicon film 10 is patterned. In the step of FIG. 4B, the gate oxide film 5 is formed, and then the second polysilicon film 11 is formed. After that, the gate oxide film 5 and the second polysilicon film 11 are patterned. Figure 4
In the step (c), phosphorus ions 13 are implanted into the entire surface to dope the source n ⁺ region 2, the drain n ⁺ region 3 and the gate electrode 4. Then, the glass substrate 1 is annealed at a temperature that it can withstand, and the implanted phosphorus is electrically activated. Figure 4
In the step (d), the SiO ₂ passivation film 1
After depositing 4, contact holes 15 are formed. In the process of FIG. 4E, aluminum (hereinafter,
After depositing a film 16 (referred to as Al), Al wiring is formed.

[0005]

However, the above-described conventional method and structure for manufacturing a polysilicon thin film transistor has the following problems.

Since the polysilicon thin film transistor is applied to a peripheral circuit having a relatively high voltage, the reliability of the polysilicon thin film transistor becomes a major issue.

In the conventional method and structure for manufacturing a polysilicon thin film transistor, since the concentration of the drain n ⁺ region is high, the depletion layer at the drain junction does not spread in the drain direction, and a high electric field is generated near the drain. In a polysilicon thin film transistor, so-called hot carrier deterioration occurs in the polysilicon thin film transistor.
S.S.D.E.R.C.Tech.
Digest 1992 (L. Mariucci, A. Pecora,
G. Fortunato, C. Reita, and P. Migliorato, "Hot ca
rriers effects in concentrated silicon thin-fil
m transistors, "ESSDERC Technical Digest, 1992). This hot carrier degradation is the induction of a high electric field in the channel near the drain, resulting in the generation of high-energy electrons and holes. Energy electrons and holes are injected into the gate oxide film, resulting in MO
The characteristic of the S transistor is deteriorated.

Due to this hot carrier deterioration, the characteristics of the polysilicon thin film transistor are gradually deteriorated during the operation of the active matrix liquid crystal display. Therefore, hot carrier deterioration is a serious problem in terms of reliability of the active matrix liquid crystal display.

On the other hand, in order to widen the extension of the depletion layer to the drain n ⁺ region 3 and relax the electric field at the drain end, the drain n ^+
When the concentration of the ⁺ region 3 is lowered, the parasitic resistance of the drain n ⁺ region 3 increases, and the driving capability of the polysilicon thin film transistor decreases.

An object of the present invention is to realize a high-performance polysilicon thin film transistor having high reliability by simultaneously solving hot carrier deterioration due to generation of a high electric field at the drain edge and increase in parasitic resistance of the drain n ⁺ region. To do.

[0011]

In order to achieve the above object, a semiconductor device of the present invention comprises a polysilicon film formed on a predetermined region of a substrate and a gate insulating film on the predetermined region of the polysilicon film. And a high-concentration first drain region and a high-concentration first source region are formed in the polysilicon film outside both ends of the gate insulating film. A second drain region and a second source which are formed below in contact with the first drain region and the first source region, respectively, and have a concentration lower than that of the first drain region and the first source region. A region is formed.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a polysilicon film on a substrate, and a step of forming a gate electrode in a predetermined region of the polysilicon film via a gate insulating film. A step of forming, a step of thermally diffusing the first impurity into the polysilicon film, and thereafter,
A step of implanting the second impurity using ion implantation is provided.

[0013]

According to the structure of the present invention, since the depletion layer spreads in the n ⁻ region formed near the drain n ⁺ region in the drain junction, the electric field near the drain is relaxed,
Deterioration of the polysilicon thin film transistor due to hot carriers is suppressed.

Moreover, since the concentration of the drain n ⁺ region is the same as that of the conventional one, it is possible to avoid a decrease in the driving capability of the polysilicon thin film transistor due to an increase in the parasitic resistance at the drain end.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings by embodiments.

FIG. 1 shows a cross section of a polysilicon thin film transistor according to an embodiment of the present invention. In FIG. 1, 1 is an insulating glass substrate, 2 is a source n ⁺ region formed by ion implantation of phosphorus, 3 is a drain n ⁺ region formed by ion implantation of phosphorus similarly to the source,
4 is a gate electrode, 5 is a gate oxide film, 6 is a channel region, 7 is a source n ⁻ region formed by phosphorus vapor diffusion, and 8 is a drain n ⁻ formed by phosphorus vapor diffusion.
Area. The concentration of the source n ⁺ region 2 and the drain n ⁺ region 3 is 10 ¹⁹ / cm ³ or more, and the concentration of the source n ⁻ region 7 and the drain n ⁻ region 8 is 10 ¹⁸ / cm ³ or more, 10 ¹⁹ / cm 3.
It is less than ³ .

A method of manufacturing the polysilicon thin film transistor according to the present invention will be described with reference to FIG. Figure 2 (a)
In the step of, the SiO ₂ film 9 is formed on the glass substrate 1 at atmospheric pressure C
It is formed by VD. Next, a first polysilicon film 10 is formed by low pressure CVD, and the first polysilicon film 1 is formed.
Pattern 0.

In the step of FIG. 2B, the gate oxide film 5 is formed by atmospheric pressure CVD, and then the second polysilicon film 11 is formed. After that, the gate oxide film 5 and the second
The polysilicon film 11 is patterned.

In the step of FIG. 2C, phosphorus is diffused all over the surface in a phosphine (PH ₃ ) gas 12 atmosphere at a temperature of 625 ° C. to dope the source n ⁻ region 7, drain n ⁻ region 8 and gate electrode 4. To do. In this process, the source n ⁻ region 7 and the drain n ⁻ region 8 are extended below the gate electrode 4.

In the step of FIG. 2D, phosphorus ions 13
Is implanted into the entire surface, and the source n ⁺ region 2, the drain n ⁺ region 3 and the gate electrode 4 are doped. Then temperature 625
Annealed at ℃, the implanted phosphorus is electrically activated.

In the step of FIG. 2E, the SiO ₂ passivation film 14 is deposited, and then the contact hole 15 is formed.

In the step of FIG. 2F, the Al film 16 is deposited, and then Al wiring is formed.

The drain n ⁻ region 8 near the drain n ⁺ region 3 of the polysilicon thin film transistor formed in this embodiment suppresses the generation of a high electric field at the drain end and prevents hot carrier deterioration. At the same time, the drain n ⁺ region 3 reduces the parasitic resistance of the drain region and secures the driving capability of the polysilicon thin film transistor.

Further, the manufacturing process shown in this embodiment can realize the structure of the polysilicon thin film transistor according to the present invention at an annealing temperature that the glass substrate 1 can withstand.

Further, since the low cost vapor diffusion is used for forming the drain n ⁻ region, the cost increase in realizing the structure of the polysilicon thin film transistor of the present invention can be minimized.

[0026]

As described above, according to the present invention, the reliability of the polysilicon thin film transistor used in the active matrix liquid crystal display can be improved while ensuring the current driving capability. As a result, the reliability of the active matrix liquid crystal display can be guaranteed without impairing the performance. Moreover, the cost increase for the polysilicon thin film transistor according to the conventional structure and method is minimized.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

2A to 2C are cross-sectional views in order of steps, illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view of a conventional semiconductor device.

FIG. 4 is a cross-sectional view in order of the steps, illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 glass substrate 2 source n ⁺ region 3 drain n ⁺ region 4 gate electrode 5 gate oxide film 6 channel region 7 source n ⁻ region 8 drain n ⁻ region 9 SiO ₂ film 10, 11 polysilicon film 12 gas 13 phosphorus ion 14 passivation Film 15 Contact hole 16 Aluminum film

Claims (2)

[Claims] 1. A polysilicon film formed on a predetermined region of a substrate, and a gate electrode is formed on a predetermined region of the polysilicon film via a gate insulating film, and is located outside both ends of the gate insulating film. High-concentration first drain regions and high-concentration first source regions are formed in the polysilicon film, respectively, and are in contact with the first drain regions and the first source regions under the gate insulating film, respectively. A semiconductor device, wherein a second drain region and a second source region having a concentration lower than that of the formed first drain region and first source region are formed. 2. A step of forming a polysilicon film on a substrate, a step of forming a gate electrode in a predetermined region of the polysilicon film via a gate insulating film, and a step of forming a first impurity in the polysilicon film. A method of manufacturing a semiconductor device, comprising: a step of thermally diffusing and a step of implanting a second impurity by ion implantation thereafter.