JPH07131004A - Semiconductor device and preparation thereof - Google Patents

Abstract

PURPOSE:To improve the reliability of a semiconductor device by suppressing the occurrence of parasitic capacitance and further maintaining hot carrier reliability. CONSTITUTION:P<+> type impurity diffusion regions 5, 6, higher in impurity concentration than a substrate 1, are formed on n<->type low-concentration impurity diffusion regions 8, 9. Thus these impurity diffusion regions 5, 6 act as potential barriers, and prevent majority carriers from being attracted from the low- concentration impurity diffusion regions 8, 9 even when they are exposed to the fringing electric field from a gate electrode 3. Therefore, the impurity diffusion regions 5, 6 also prevent the occurrence of parasitic capacitance. Even if the field strength of source and drain is increased in proximity to the low- concentration diffusion regions, and thus hot carriers are produced, for example, by increasing the impurity concentration of the low-concentration impurity diffusion regions 8, 9, it is hard for the hot carriers to reach a gate oxide film 2 because of the presence of the p<+>-type impurity diffusion regions 5, 6.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LDD (Lightl)
The present invention relates to a semiconductor device having a y Doped Drain) structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art It is known that in the vicinity of the drain of a MOS transistor having a normal structure, electric field concentration becomes intense, a large amount of hot carriers are generated, and characteristics are easily deteriorated. In order to reduce the generation of this hot carrier,
It is effective to avoid electric field concentration by lowering the impurity concentration at the drain end and making the profile gentle.

As a structure for solving this problem, for example, Japanese Patent Application Laid-Open No. 64-37055 (H01L29 / 78).
A well-known LDD structure transistor as shown in FIG. That is, in FIG. 2, after forming the oxide film 2 and the gate electrode 3 made of polysilicon on the silicon substrate 1, phosphorus (P) as an n-type impurity is ion-implanted using the gate electrode as a mask (n ⁻ ). Forming a layer (a), C
A silicon oxide film (SiO 2) is formed on the substrate 1 by the VD method.
₂ ) 4 is deposited (b), the Si oxide film 4 is etched back to form sidewalls 4a (c), and arsenic is used as an n-type impurity by using the gate electrodes 3 and the sidewalls 4a as masks. (As) is ion-implanted to form an (n ⁺ ) layer (d).

In the above publication, a (p ⁺ ) layer having a higher concentration than the substrate is further formed under the (n ⁻ ) layer to prevent the short channel effect of the transistor.

[0005]

LDD as in the prior art
In a transistor having a structure, in order to improve the hot carrier reliability, the (n ⁻ ) layer and the gate electrode 3 are overlapped with each other and the impurity concentration of the (n ⁻ ) layer is increased as shown in FIG. The electric field strength in the vicinity of the low-concentration diffusion region in the drain or source is reduced, the impact ionization rate is reduced, and the generation of hot carriers can be reduced.

However, with such a structure, on the contrary, a parasitic capacitance is generated between the low-concentration diffusion region in the drain or source and the gate electrode, and there is a problem that characteristics of the transistor are deteriorated. The present invention relates to an improvement in a semiconductor device and a method of manufacturing the same, and an object thereof is to suppress the occurrence of parasitic capacitance while maintaining the hot carrier reliability, and to improve the reliability as a semiconductor device.

[0007]

A semiconductor device according to a first invention is a semiconductor substrate of one conductivity type, a gate insulating film formed on the substrate, and a gate electrode formed on the gate insulating film. A high-concentration impurity diffusion region of another conductivity type that is formed on both sides of the gate electrode in the substrate and serves as a source and drain region, and is formed so as to be adjacent to the high-concentration impurity diffusion region and located on the channel side. , A low-concentration impurity diffusion region of another conductivity type having an impurity concentration lower than that of the high-concentration impurity diffusion region, and one conductivity having an impurity concentration higher than that of the substrate and formed so as to be located above the low-concentration impurity diffusion region. Type impurity diffusion region.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the gate electrode formed on a semiconductor substrate of one conductivity type is used as a mask, and the impurity concentration on both sides of the gate electrode in the substrate is higher than that in the substrate. Forming a high conductivity type impurity diffusion region, and using the gate electrode as a mask, under the conductivity type impurity diffusion region,
Forming a low-concentration impurity diffusion region of another conductivity type, forming a sidewall on the side wall of the gate electrode, and using the gate electrode and the sidewall as a mask, a high-concentration impurity of another conductivity type on the substrate. And a step of forming a diffusion region.

In the method of manufacturing a semiconductor device according to the third aspect of the invention, the step of forming an impurity diffusion region of one conductivity type having an impurity concentration higher than that of the substrate is performed by an instantaneous vapor phase doping method.

[0010]

That is, since the one conductivity type impurity diffusion region having a higher impurity concentration than the substrate is provided above the other conductivity type low concentration impurity diffusion region, the one conductivity type impurity diffusion region serves as a potential barrier. Also, the majority carriers are difficult to be induced from the low-concentration impurity diffusion region by the fringing electric field from the gate electrode. Therefore, the generation of parasitic capacitance is also suppressed.

Further, even if the electric field strength in the vicinity of the low-concentration diffusion region in the drain or the source is increased by increasing the impurity concentration in the low-concentration impurity diffusion region, and hot carriers are generated, one conductivity type Hot carriers due to the presence of the impurity active region are less likely to reach the gate oxide film. Further, a shallow one conductivity type impurity diffusion region can be easily formed by the instantaneous vapor phase doping method.

[0012]

EXAMPLE An example of the present invention will be described with reference to FIG.
However, the same components as those in the conventional example are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1A, the gate electrode 3 is formed on the p-type Si substrate 1.
The steps up to the formation of are similar to those of the conventional example. After forming the gate electrode 3, by the instantaneous vapor phase doping method,
Shallow (p
⁺ Type impurity diffusion regions 5 and 6 (junction depth: 20 to 50)
0Å, impurity concentration: 10 ¹⁷ to 10 ¹⁸ cm ⁻³ ) are formed.

The process of the instantaneous vapor phase doping method is as follows. That is, first, after the substrate 1 is placed in the chamber, it is heated to 800 ° C. to 1050 ° C. in a hydrogen atmosphere to remove the natural oxide film. Then, the temperature in the chamber is lowered to 800 ° C. to 900 ° C., B ₂ H ₆ gas 7 is introduced, and the process is waited for 1 minute to 30 minutes. Then, using the gate electrode 3 as a mask, shallow (p ⁺ ) type impurity diffusion regions 5 and 6 are formed.

Next, in FIG. 1B, phosphorus (P) or arsenic (As) is implanted by an ion implantation method to obtain the shallow (p)
^{Under the +} ) type impurity diffusion regions 5 and 6, (n ⁻ ) type low concentration impurity diffusion regions 8 and 9 are formed. And the substrate 1
A Si oxide film is deposited on the upper surface by a low pressure CVD method and is etched back to form a sidewall 4a on the sidewall of the gate electrode 3.

Finally, in FIG. 1C, using the gate electrode 3 and the sidewall 4a as a mask, As is implanted by an ion implantation method to form (n ⁺ ) type high-concentration impurity diffusion regions 10 and 11, and a heat treatment is performed. Then, each region is activated. In order to prevent the short channel effect of the transistor, the shallow (p ⁺ ) type impurity diffusion regions 5 and 6 are used.
It is desirable that the junction depth of 1000 Å or less, especially 64M
It is desirable that the integration degree of the DRAM class is 500 Å or less.

In the present embodiment, in order to realize this numerical value, a relatively simple instantaneous vapor phase doping method was used, but the present invention is not limited to this, and there is no problem even if it is realized by a normal ion implantation method. There is no. Further, in this embodiment, p
Although the n-type Si substrate is used, it is needless to say that the conductivity types of p and n in each diffusion region are reversed when the n-type Si substrate is used.

[0017]

According to the semiconductor device and the method of manufacturing the same of the present invention, since the generation of parasitic capacitance can be suppressed and the hot carrier reliability can be maintained, the reliability of the semiconductor device can be improved. it can. Further, in the method of manufacturing a semiconductor device according to the third aspect, the shallow one conductivity type impurity active region can be easily formed by the instantaneous vapor phase doping method.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device in a conventional example.

[Explanation of symbols]

1 p-type Si substrate (one conductivity type semiconductor substrate) 2 gate insulating film 3 gate electrode 4a sidewalls 5, 6 (p ⁺ ) type impurity diffusion region (one conductivity type impurity diffusion region) 8, 9 (n ⁻ ) Type low concentration impurity diffusion region (other conductivity type low concentration impurity diffusion region) 10, 11 (n ⁺ ) type high concentration impurity diffusion region (other conductivity type high concentration impurity diffusion region)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/772

Claims (3)

[Claims] 1. A semiconductor substrate of one conductivity type, a gate insulating film formed on the substrate, a gate electrode formed on the gate insulating film, and formed on both sides of the gate electrode on the substrate. , Other-conductivity-type high-concentration impurity diffusion regions to be the source and drain regions, and adjacent to the high-concentration impurity diffusion regions and located on the channel side, and having a lower impurity concentration than the high-concentration impurity diffusion regions. A low-concentration impurity diffusion region of another conductivity type; and a single-conductivity-type impurity diffusion region formed above the low-concentration impurity diffusion region and having a higher impurity concentration than the substrate. Semiconductor device. 2. A step of forming an impurity diffusion region of one conductivity type having an impurity concentration higher than that of the substrate on both sides of the gate electrode in the substrate using the gate electrode formed on the semiconductor substrate of one conductivity type as a mask. A step of forming a low-concentration impurity diffusion region of another conductivity type under the impurity diffusion region of one conductivity type using the gate electrode as a mask; and a step of forming a sidewall on a sidewall of the gate electrode. And a step of forming a high-concentration impurity diffusion region of other conductivity type on the substrate using the gate electrode and the sidewall as a mask. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming the one conductivity type impurity diffusion region having an impurity concentration higher than that of the substrate is performed by an instantaneous vapor phase doping method.