JP3146045B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP3146045B2
JP3146045B2 JP00032492A JP32492A JP3146045B2 JP 3146045 B2 JP3146045 B2 JP 3146045B2 JP 00032492 A JP00032492 A JP 00032492A JP 32492 A JP32492 A JP 32492A JP 3146045 B2 JP3146045 B2 JP 3146045B2
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Prior art keywords
semiconductor
layer
base layer
semiconductor device
channel
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JP00032492A
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JPH05183154A (en
Inventor
葉 聡 稲
木 信 一 高
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株式会社東芝
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Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microminiature semiconductor device, and more particularly to a MIS type field effect transistor.

[0002]

2. Description of the Related Art A semiconductor device of this type includes a p-channel transistor using silicon. Since the mobility of holes serving as carriers is smaller than the mobility of electrons, the p-channel transistor is different from an n-channel transistor. It is known that the current driving force is small.

Therefore, in recent years, in order to improve the current driving force of a p-channel transistor, a channel layer is buried, and further, a semiconductor having a smaller forbidden band than silicon and having almost the same electron affinity as silicon. For example, attempts have been made to improve the current driving force by increasing the mobility and increasing the number of carriers by using an alloy (SiGe) layer of germanium and silicon for the channel layer.

[0004]

However, in the current prototype, the inversion layer is not formed only in the SiGe layer by applying the gate voltage, but the gate oxide film and the S
Since an inversion layer is also formed at the interface with the i-layer and holes serving as carriers are generated, the overall mobility is apparently
There is a disadvantage that the mobility is deteriorated from the mobility of the SiGe layer, and the characteristics of the SiGe channel transistor cannot be utilized to the maximum.

Further, the conventional SiGe channel transistor has a structure which can be applied to miniaturization as represented by a normal buried channel type transistor, that is, a structure in which the short channel effect is suppressed. Did not. Miniaturization of a semiconductor element, particularly, reduction of a channel length of a field effect transistor is an important technique for achieving high density and high performance of the entire element. However, in order to suppress the deterioration of transistor characteristics due to the shortened channel length, that is, the so-called short channel effect, the impurity concentration of the semiconductor substrate is increased,
In spite of the fact that it is inevitable to make the source / drain impurity diffusion layers shallow, no countermeasures have been taken for SiGe channel transistors.

The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object the advantage of a buried type channel layer formed of a semiconductor having a smaller forbidden band width than a substrate material. A semiconductor device as a MIS field effect transistor contributing to high-performance and high-density integration, which can be utilized without impairing as much as possible and can achieve a shallow source / drain impurity diffusion layer, and a method of manufacturing the same. Is to provide.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate, a semiconductor base layer, and a forbidden band, which are closer to the semiconductor base layer, than the material of the semiconductor base layer. A semiconductor channel layer formed of an alloy material of silicon and germanium having a small width and a semiconductor cap layer formed of a material whose forbidden band width is equal to or more than that of the material of the semiconductor base layer are stacked. An insulated gate transistor having a three-layered semiconductor region below its gate electrode and having a source region and a drain region on each side of the three-layered semiconductor region, and interposed between the semiconductor substrate and the insulated gate transistor And an interlayer insulating film layer that electrically insulates and separates the two from each other. The sum of the thicknesses of the three-layered semiconductor regions is determined by the impurity concentration of the semiconductor base layer. N, the dielectric constant of the semiconductor base layer is ε, the Boltzmann constant is KB, the impurity concentration of the intrinsic semiconductor is ni, and the electron charge is q, the maximum depletion layer width Wm immediately below the channel region is Wm = (4ε · KB · T・ Ln (N / ni) / (q 2 · N))
It is characterized by being smaller than 1/2 .

[0008]

[0009]

[0010]

[0011]

In the method of manufacturing a semiconductor device according to the present invention, the process for forming a semiconductor base layer on the interlayer insulating film layer in the semiconductor device includes a step of ion-implanting oxygen atoms into a deep portion of the semiconductor substrate. Heat-treating the semiconductor substrate to form an oxygen-implanted region only as the interlayer isolation insulating film layer while leaving an intrinsic semiconductor film as a material of the semiconductor base layer on the substrate surface. It is characterized by being.

Further, a method of manufacturing a semiconductor device according to the present invention
As a process for forming a semiconductor base layer on an interlayer isolation insulating film layer in the semiconductor device, a step of forming an insulating film on the surface of a semiconductor substrate, and forming a semiconductor film as a material of the semiconductor base layer on the insulating film And adhering step.

In the present invention, the method of manufacturing the semiconductor channel layer is not particularly limited. For example, the following two methods can be considered. First, a semiconductor film used as a material for a semiconductor base layer is etched to a thickness as the semiconductor base layer, and then a semiconductor film used as a material for a semiconductor channel layer is epitaxially grown on the semiconductor film. is there.

In addition, atoms for forming the same surface side region as a material of the semiconductor channel layer are ion-implanted so that the thickness of the semiconductor base layer in the semiconductor film used as the material of the semiconductor base layer is left deep. Then, heat treatment for recovering crystal defects in the surface side region of the semiconductor film is performed.

[0016]

According to the present invention, by employing the above-described structure, the formation of the inversion layer at the interface between the gate insulating film and the semiconductor cap layer can be suppressed even when the channel of the semiconductor channel layer is inverted. It is possible to reduce the apparent mobility deterioration due to the carrier mobility of the semiconductor cap layer having a larger forbidden band width than the semiconductor channel layer, and to realize a high performance with a high current driving force making the best use of the characteristics of the buried channel. A p-type field effect transistor can be formed.

The principle of the present invention will be briefly described below. FIG. 6 shows that when the thickness of the semiconductor channel layer (hereinafter, referred to as TSiGe) is 50 Å and the thickness of the semiconductor cap layer (hereinafter, referred to as TSi) is 40 Å, the impurity concentration Nsub of the semiconductor base layer is set. 1.
45 × 10 10 cm −3 (impurity concentration about the same as the carrier concentration of intrinsic Si) (FIG. 10A)
This is a comparison of the band structure calculated approximately when the band structure was set to 1 × 10 18 cm −3 ((b) in the same figure), and the state shown in this figure depends on the voltage applied to the gate electrode. The band is bent, and an inversion layer is formed in the semiconductor channel layer. Here, the increase dpSiGe of holes generated in the semiconductor channel layer is approximately 1 × 10 12
cm -2 is considered.

Here, comparing the two, the impurity concentration Nsub of the semiconductor base layer is 1.45 × 1 which is relatively lower.
In the case of 0 10 cm -3 , it can be seen that the number of holes generated in the semiconductor cap layer is small.

Therefore, an element is formed by using an undoped semiconductor layer in such a form, and at the same time, by forming a structure utilizing the characteristics of a so-called SOI structure, a field effect transistor using a SiGe channel can be formed. Achieve high carrier mobility and at the same time achieve shallower source and drain regions,
The short channel effect can be suppressed, and application to a fine semiconductor element can be realized.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a structure of a semiconductor device constituting a MIS field effect transistor according to one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate made of silicon (Si). On this semiconductor substrate 1, an interlayer isolation oxide film (SiO 2 film) 2 is formed over the entire surface thereof. An element isolation oxide film 10 is formed so as to surround the formation region.

An MIS field effect transistor is formed in this element formation region. That is, a three-layer semiconductor region is formed at the center thereof, and this region is formed by laminating a semiconductor base layer 3, a semiconductor channel layer 4, and a semiconductor cap layer 5 in order from the side closer to the semiconductor substrate 1. . That is, the semiconductor base layer 3 is formed on the interlayer isolation oxide film 2, the semiconductor channel layer 4 is formed on the semiconductor base layer 3, and the semiconductor cap layer 5 is formed on the semiconductor channel layer 4. I have. Here, Si
Is a basic semiconductor material constituting the semiconductor base layer 3 and the semiconductor cap layer 5, and an alloy of Si and Ge (SiG
e) The layer is a semiconductor material of the semiconductor channel layer 4. The SiGe has a narrower forbidden band width than Si and has the same electron affinity as Si. A gate oxide film 6 is formed on the Si cap layer 5, and a gate electrode 7 is formed on the gate oxide film 6. 3 above
On one side of the semiconductor region from layers 3 to 5 is a source region 8
However, a drain region 9 is formed on the other side.

This transistor is formed on the semiconductor substrate 1 via the interlayer insulating film 2 and has an SOI structure. The sum of the thicknesses from the semiconductor base layer 3 to the semiconductor cap layer 5 is made smaller than the maximum depletion layer width Wm immediately below the semiconductor channel region 4 formed when a voltage is applied to the gate electrode 7, so that the source The shallow region 8 and the drain region 9 can be realized, and the source region
The structure is such that punch-through between drains can be suppressed.

Further, as already described with reference to FIG.
It is preferable that the impurity concentration Nsub of the semiconductor base layer 3 is lower. Practically, as shown in FIG. 3, an undoped semiconductor (up to about Nsub <5 × 10 15 cm −3 ) can suppress formation of an inversion layer in the semiconductor cap layer 5. Can be The horizontal axis represents the impurity concentration Nsub of the semiconductor base layer 3, and the vertical axis represents the ratio (dpSi / dpSiGe) between the number dpSi of holes generated in the semiconductor channel layer 4 and the number dpSiGe of holes generated in the semiconductor cap layer. Is shown. As described above, it is possible to solve the problem that the short channel effect occurs when the element is miniaturized using the undoped semiconductor by adopting the so-called SOI structure.

FIG. 4 shows the thickness T of the semiconductor channel layer 4.
Using SiGe as a parameter, the ratio (dpSi / d) of the thickness TSi of the semiconductor cap layer 5 to the increase in the number of holes generated in the semiconductor cap layer 5 and the semiconductor channel layer 4 is the same as before.
pSiGe). Generally, it is considered that the lower limit of the thickness TSiGe of the semiconductor channel layer 4 is about 10 angstroms from the viewpoint of controlling the film thickness.
On the other hand, the upper limit of the thickness TSiGe of the semiconductor channel layer 4 is, for example, Si in the case of being formed by epitaxial growth due to the strain generated between Si and the underlying (semiconductor base layer 3).
It is experimentally known that the case of 0.5 Ge 0.5 is about 100 angstroms. It is known that this upper limit becomes smaller as the ratio of Ge increases,
In this case, it is appropriate to reduce the thickness to 100 angstroms or less. On the other hand, as the thickness TSi of the semiconductor cap layer 5 increases, the proportion of holes generated in the semiconductor cap layer 5 gradually increases. Considering the above range of TSiGe (10 Å ≦ TSiGe ≦ 100 Å), if a boundary line is to be drawn where the proportion of holes in the semiconductor cap layer 5 is about 1% of the semiconductor channel layer 3, for example, Below, it can be seen that the device operates well if the thickness TSi of the semiconductor cap layer 5 is about 40 Å. When the gate voltage is further increased and the number of carriers in the inversion layer is increased, the ratio of the number of carriers generated in the semiconductor cap layer 5 is larger than the estimated value.
Si needs to be at most about 40 angstroms or less.

Further, as shown in FIG. 5, when the thickness TSi of the semiconductor cap layer 5 increases, the proportion of holes generated in the semiconductor cap layer 5 becomes very sensitive to this TSi. If the number of carriers of the semiconductor cap layer 5 is to be within a certain range,
In other words, if an attempt is made to make the variation within a certain deviation, the margin of the TSi control cannot be taken. FIG.
The middle two rectangles represent the margin of TSi control for a certain variation range, and as indicated by the arrow, it can be seen that the smaller the thickness of the semiconductor cap layer 5, the better. For this reason, it is necessary to keep TSi within the above range.

Next, the manufacturing process of the semiconductor device shown in FIG. 1 will be specifically described with reference to FIG.

First, a semiconductor film 203 serving as a material of a semiconductor base layer is formed on a semiconductor substrate 201 via an interlayer isolation oxide film layer 202 (FIG. 2A). At this time, SiO 2
Since a semiconductor layer cannot be epitaxially grown thereon, for example, the following two methods are used.

In one method, oxygen atoms are ion-implanted into a deep portion of the semiconductor substrate 201 and then heated to leave only the oxygen-implanted region as an interlayer isolation oxide film layer 202 while leaving the undoped semiconductor film 203 on the surface. SIMO to form
It is based on the X method.

Another method is to form an interlayer isolation oxide film layer 202 by thermal oxidation of the semiconductor substrate 201, and to attach an undoped semiconductor film 203 on the interlayer isolation oxide film layer 202.

Next, after the semiconductor film 203 is etched to a desired thickness, a SiGe semiconductor film 204 is formed (FIG. 6B). For example, the following two methods can be used as the method.

One of them uses an epitaxial growth method such as the MBE method. First, when the semiconductor film 203 is etched, its thickness is reduced to a thickness as the semiconductor base layer, and thereafter, SiGe is epitaxially grown. That is.

In one method, first, the semiconductor film 203 is etched a little so as to secure at least the combined thickness of both the semiconductor base layer and the semiconductor channel layer. Ge ions are implanted into the surface region of the semiconductor film 203 so as to leave the undoped semiconductor by the thickness of the semiconductor film 203. Thereafter, an annealing step for recovering crystal defects in the implanted region is performed. The thickness of the substrate 204 is reduced by etching until the thickness of the substrate becomes the thickness of the semiconductor base layer.

Thereafter, S, which is a material of the semiconductor cap layer,
The i-semiconductor film 205 is formed using the MBE method or the like. In some cases, it is necessary to adjust the thickness by etching or the like. At this stage, the trench is
An inter-element isolation oxide film 206 is formed by filling the inside with an insulator such as SiO 2 . Then, an oxide film is formed over the entire surface, polysilicon is subsequently deposited, and impurities such as P
After (phosphorus) is diffused, patterning for the gate electrode is performed, and a gate oxide film 207 and a gate electrode 208 are formed by RIE or the like (FIG. 2C). For controlling the threshold, another impurity may be introduced into the gate electrode.

Next, B (boron) or BF 2 (boron fluoride) is ion-implanted and activation annealing is performed to form a three-layer structure including a semiconductor base layer 209, a semiconductor channel layer 210, and a semiconductor cap layer 211. Part of the structural semiconductor region is self-aligned with respect to the gate electrode,
12 and the drain region 213 are formed (FIG. 2
(D)).

Finally, an interlayer isolation oxide film 214 for electrical insulation between the element layer and the wiring layer is deposited by CVD or the like, and a contact hole is patterned and an opening is formed by RIE or the like, and W (tungsten) or the like is formed. Fill the contact hole,
Then, by bonding Al (aluminum) to the filler, each of the gate, source and drain 2
The element is completed by forming the layer electrodes 215 to 217 (FIG. 2E).

In the embodiment described above, the trench element isolation is used in the element isolation region. However, the present invention is not limited to this, and the use of a normal LOCOS process can be used. In addition, although an Si oxide film was used as an insulating film in various places,
Obviously, a Si nitride film or another insulating film may be used.

As the gate insulating film, an oxide film deposited by CVD or the like may be used other than the method of oxidizing silicon which is generally used. This is because in this structure, the poor quality of the oxide film interface near the gate is not essentially related to the behavior of carriers. of course,
An oxide film or a nitride film formed by another method may be used. In that case, a semiconductor material having the largest forbidden band width may be used for the semiconductor cap layer.

Further, the present invention can be applied to an n-channel field effect transistor in a similar combination.

[0041]

As described above, according to the present invention,
Even when the semiconductor channel layer is inverted, the formation of the inversion layer at the interface between the gate insulating film and the semiconductor cap layer is suppressed,
As a result, it is possible to reduce the apparent mobility deterioration due to the carrier mobility of the semiconductor cap layer having a larger forbidden band width than the semiconductor channel layer, and to have a high current driving force that makes full use of the characteristics of the buried channel. A p-type field effect transistor having high performance and suitable for miniaturization can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to one embodiment of the present invention.

FIG. 2 is an element sectional view for explaining a manufacturing process of the semiconductor device having the structure shown in FIG. 1;

FIG. 3 shows the impurity concentration Nsub of the semiconductor base layer on the horizontal axis and the ratio (dpSiGe) between the number dpSi of holes generated in the semiconductor channel layer and the number dpSiGe of holes generated in the semiconductor cap layer on the vertical axis.
(pSi / dpSiGe) is a graph for explaining the influence of the impurity concentration of the semiconductor base layer on the formation of the inversion layer in the semiconductor cap layer.

FIG. 4 is a graph in which the thickness TSiGe of the semiconductor channel layer is used as a parameter, the horizontal axis represents the thickness TSi of the semiconductor cap layer, and the vertical axis represents the ratio (dpSi / dpSiGe), and illustrates the effect of the thickness of the semiconductor channel layer and the cap layer on the formation of the inversion layer in the semiconductor cap layer.

5 shows the thickness TSi of the semiconductor cap layer on the horizontal axis, the ratio of the increase in holes generated in the semiconductor cap layer and the semiconductor channel layer (dpSi / dpSiGe) on the vertical axis, and the vertical axis from FIG. 4 is a graph illustrating the effect of the thickness of the semiconductor cap layer on the formation of the inversion layer in the semiconductor cap layer.

FIG. 6 is an energy band explanatory diagram showing a difference in band structure due to a difference in impurity concentration of a semiconductor base layer when a gate voltage is applied.

[Explanation of symbols]

 Reference Signs List 1,201 Semiconductor substrate 2,202 Interlayer isolation oxide film 3,209 Semiconductor base layer 4,210 Semiconductor channel layer 5,211 Semiconductor cap layer 6,207 Gate insulating film 7,208 Gate electrode 8,212 Source region 9,213 Drain region

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-3366 (JP, A) JP-A-2-100327 (JP, A) JP-A-3-165555 (JP, A) JP-A-1- 106466 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/78

Claims (6)

    (57) [Claims]
  1. A semiconductor substrate, a semiconductor base layer, a semiconductor channel layer formed of an alloy material of silicon and germanium having a smaller band gap than a material of the semiconductor base layer, and a material of the semiconductor base layer. A semiconductor cap layer formed of a material having the same or greater forbidden band width and having a three-layer structure semiconductor region, which is sequentially stacked from the side closer to the semiconductor substrate, under the gate electrode, and an insulated gate transistor having a source region and a drain region on each side, and an interlayer isolation insulating layer to electrically insulate separate them is interposed between the semiconductor substrate and the insulating gate type transistor, the 3 The sum of the thicknesses of the layered semiconductor regions is such that the impurity concentration of the semiconductor base layer is N,
    Dielectric constant ε, Boltzmann constant KB, intrinsic
    The impurity concentration of the semiconductor ni, maximum depletion layer width immediately below the channel region when the electron charge was q Wm = (4ε · KB · T · ln (N / ni) / (q 2 · N))
    A semiconductor device characterized by being smaller than 1/2 .
  2. 2. The semiconductor device according to claim 1 , wherein the semiconductor base layer is formed of an undoped semiconductor.
  3. 3. The semiconductor device according to claim 2 , wherein the thickness of the semiconductor channel layer is not more than 100 Å.
  4. 4. The semiconductor device according to claim 3 , wherein the thickness of the semiconductor cap layer is 40 angstroms or less.
  5. 5. As the process for forming a semiconductor base layer on the interlayer isolation insulating film layer in the semiconductor device according to any one of claims 1 to 4, an oxygen atom is ion-implanted into a deep portion of the semiconductor substrate Forming a semiconductor substrate surface by heating the semiconductor substrate, leaving an intrinsic semiconductor film as a material of the semiconductor base layer on the surface of the semiconductor substrate, and forming only the oxygen atom implanted region as the interlayer isolation insulating film layer. A method for manufacturing a semiconductor device, comprising:
  6. 6. A process for forming a semiconductor base layer on an interlayer isolation insulating film layer in the semiconductor device according to claim 1 , comprising: forming an insulating film on a surface of a semiconductor substrate. Attaching a semiconductor film to be a material of the semiconductor base layer on the insulating film.
JP00032492A 1992-01-06 1992-01-06 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3146045B2 (en)

Priority Applications (1)

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JP00032492A JP3146045B2 (en) 1992-01-06 1992-01-06 Semiconductor device and manufacturing method thereof

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JP00032492A JP3146045B2 (en) 1992-01-06 1992-01-06 Semiconductor device and manufacturing method thereof

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JP3146045B2 true JP3146045B2 (en) 2001-03-12

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Publication number Priority date Publication date Assignee Title
US9953977B1 (en) 2017-04-13 2018-04-24 International Business Machines Corporation FinFET semiconductor device

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Publication number Priority date Publication date Assignee Title
WO2002033759A1 (en) * 2000-10-19 2002-04-25 Matsushita Electric Industrial Co., Ltd. P-channel field-effect transistor
US6410371B1 (en) * 2001-02-26 2002-06-25 Advanced Micro Devices, Inc. Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
EP1265294A3 (en) 2001-06-07 2004-04-07 Matsushita Electric Industrial Co., Ltd. Heterojunction bipolar transistor
US7288448B2 (en) * 2004-08-24 2007-10-30 Orlowski Marius K Method and apparatus for mobility enhancement in a semiconductor device
JP4950810B2 (en) * 2007-08-28 2012-06-13 旭化成エレクトロニクス株式会社 Semiconductor device
JP2009182264A (en) 2008-01-31 2009-08-13 Toshiba Corp Semiconductor device and method of fabricating the same
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
KR101757007B1 (en) * 2009-09-30 2017-07-26 엠아이이 후지쯔 세미컨덕터 리미티드 Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US9276134B2 (en) * 2014-01-10 2016-03-01 Micron Technology, Inc. Field effect transistor constructions and memory arrays

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Publication number Priority date Publication date Assignee Title
US9953977B1 (en) 2017-04-13 2018-04-24 International Business Machines Corporation FinFET semiconductor device

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