JPH07336050A - Manufacture of multilayer printed circuit board - Google Patents

Manufacture of multilayer printed circuit board

Info

Publication number
JPH07336050A
JPH07336050A JP12622994A JP12622994A JPH07336050A JP H07336050 A JPH07336050 A JP H07336050A JP 12622994 A JP12622994 A JP 12622994A JP 12622994 A JP12622994 A JP 12622994A JP H07336050 A JPH07336050 A JP H07336050A
Authority
JP
Japan
Prior art keywords
substrate
metal layer
plating
circuit pattern
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12622994A
Other languages
Japanese (ja)
Other versions
JP3620065B2 (en
Inventor
Fujio Kojima
富士男 小島
Haruo Ogino
晴夫 荻野
Nobuyuki Minami
宜行 南
Kazuji Yamagishi
一次 山岸
Yoshihiro Tamura
義広 田村
Kenichi Kawada
健一 河田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP12622994A priority Critical patent/JP3620065B2/en
Publication of JPH07336050A publication Critical patent/JPH07336050A/en
Application granted granted Critical
Publication of JP3620065B2 publication Critical patent/JP3620065B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To easily manufacture a thin multilayer printed circuit board in which an interlayer connection is easy and which has excellent wiring density by using adhesive in a B-stage state. CONSTITUTION:A method for manufacturing a multilayer printed circuit board comprises the steps of plating a copper sulfate 2 on the surface of a stainless steel plate 1, then forming a resist pattern 3 on the surface of the sulfate 2, subsequently peeling the resist 3 to form a circuit pattern 4, then black oxidizing the plate 1, adhering an adhesive film 5 on the pattern 4 forming surface, pressurizing it, heating it to a B stage, then peeling the foil formed with the pattern 4 from the plate 1, subsequently opening a hole 6 at a connecting position to meet the pattern 4, then so laminating to integrate that other inner layer plate is brought into contact with the adhesive 5 layer side of the board opened with the hole 6, then opening a hole 9 penetrated through the entire laminated plate, copper-plating the entire surface, and then removing the copper 10 of the surface by etching until the gold-plating is exposed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、微細パターンを容易に
得ることができる多層プリント配線板の製造法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, which allows a fine pattern to be easily obtained.

【0002】[0002]

【従来の技術】プリント配線板の線幅、線間隔はLSI
の高集積化や部品実装の高密度化に伴いますます細線化
が進んできている。しかし、従来のプリント配線板の製
造方法──例えば、銅張り積層板をエッチングして回路
パターンを形成するサブトラクト法では、表面銅箔のへ
こみ、きず等が原因による断線やショートが発生し易
く、また表面の凹凸やうねりによる線幅精度が低下する
ため、線幅100μm以下が加工限界である。このこと
から、必要な部分にめっきして回路を形成するアディテ
ィブ法や厚み5〜9μmの銅箔を用いた銅張り積層板の
必要な部分にめっきを行いクイックエッチングにより回
路を形成するセミアディティブ法が微細パターンの形成
に適している。しかし、アディティブ法では基板表面の
粗度やめっきの銅フリ現象等から、またセミアディティ
ブ法では銅張り積層板自体の欠陥や特性により、80μ
m以下の微細パターンの形成は困難となっている。
2. Description of the Related Art The width and spacing of printed wiring boards are LSI
With higher integration and higher density of parts mounting, the line width is becoming thinner. However, the conventional method for manufacturing a printed wiring board--for example, in the subtract method of forming a circuit pattern by etching a copper-clad laminate, a dent on the surface copper foil, a disconnection or a short circuit due to a flaw is likely to occur, In addition, since the line width accuracy is reduced due to surface irregularities and waviness, the line width is 100 μm or less. From this, the additive method of plating a required portion to form a circuit or the semi-additive method of plating a required portion of a copper-clad laminate using a copper foil having a thickness of 5 to 9 μm and forming a circuit by quick etching Is suitable for forming a fine pattern. However, in the additive method, due to the roughness of the substrate surface and the copper-free phenomenon of plating, and in the semi-additive method, due to defects and characteristics of the copper-clad laminate itself, 80 μm
It is difficult to form a fine pattern of m or less.

【0003】そこで、微細パターン形成に適した配線板
の製造方法として、特公昭63−37515号公報や特
公平1−58878号公報に見られるように、導電性を
有する保持体にめっきレジストを形成し、該保持体の除
去方法と異なる金属層と他の金属層とからなる金属層を
めっきで形成し、前記めっきレジストを除去した後に前
記金属層の面に絶縁基材を接着積層し、前記金属層が露
出するまで前記保持体を除去するという導体回路を埋め
込む配線板の製造法が多用されている。この製造方法で
あれば、線幅、線間隔40μm程度の回路パターンを断
線、ショートの発生が少なく安定的に形成でき、且つ回
路パターンのサイドエッチもなく基板表面が平滑になる
という利点も得られる。
Therefore, as a method of manufacturing a wiring board suitable for forming a fine pattern, a plating resist is formed on a conductive support as disclosed in JP-B-63-37515 and JP-B-1-58878. Then, a metal layer consisting of a metal layer different from the method for removing the holder and another metal layer is formed by plating, and after removing the plating resist, an insulating base material is adhesively laminated on the surface of the metal layer, A method of manufacturing a wiring board in which a conductor circuit is embedded is often used in which the holding body is removed until the metal layer is exposed. According to this manufacturing method, it is possible to stably form a circuit pattern having a line width and a line spacing of about 40 μm with little occurrence of disconnection and short circuit, and to obtain a merit that the substrate surface is smooth without side etching of the circuit pattern. .

【0004】一方、部品実装の高密度化に伴って線幅、
線間隔の細線化ばかりでなく、導通穴の数も増加してい
る1つの配線層と他の配線層の電気的接続に使用される
導通穴は、従来配線層を多層積層した後に、全体を貫通
する穴をあけ、その穴内壁をめっきすることによって行
われている。しかし、この方法では全体を貫通する穴を
あけるため、接続と無関係な配線層ではその貫通穴を避
けて配線を行わなければならず、設計の自由度や配線の
高密度化の障害になっている。
On the other hand, as the density of components is increased, the line width,
Not only is the line spacing narrowed, but the number of conductive holes is increasing. The conductive holes used for electrical connection between one wiring layer and another wiring layer are This is done by forming a through hole and plating the inner wall of the hole. However, in this method, since a hole that penetrates the whole is opened, it is necessary to avoid the through hole in the wiring layer that is unrelated to the connection, and this is an obstacle to the degree of freedom in designing and increasing the density of the wiring. There is.

【0005】そこで、配線板全体に貫通する穴だけを使
用するのではなく、隣接する配線層のみの配線を行う、
いわゆるバイアホールを形成する方法が開発されてい
る。この方法は、現在、基本的に以下の2通りの方法が
知られている。
Therefore, instead of using only holes penetrating the entire wiring board, wiring is performed only in adjacent wiring layers.
Methods have been developed for forming so-called via holes. At present, the following two methods are basically known as this method.

【0006】第一の方法は、隣接する配線層を先に形成
し、接続穴を形成しておいて、多層化する方法である。
この方法の一例としては、両面銅張り積層板に穴をあ
け、穴内壁に無電解めっきあるいは必要な場合電解めっ
きを行って接続用導体を形成し、片面の銅箔の不要な箇
所のみをエッチング除去し、もう一方の面に銅箔を残し
ておき、他の基板と積層一体化した後、全体を貫通する
穴をあけて、穴内壁を金属化する方法や、絶縁基板の表
面に配線層を形成し、その配線層の表面に感光性絶縁材
料によって層を形成し、導通穴となる箇所のみを除去す
るように光を照射し現像して、この絶縁材料の表面を粗
化し、必要な回路導体を穴内壁とに無電解めっきを行っ
て導体を形成する方法等がある。これらの技術は、いず
れも、さらに必要な配線層を同じ技術で形成して多層化
するものである。
The first method is a method of forming adjacent wiring layers first, forming connection holes, and then forming multiple layers.
As an example of this method, a hole is made in a double-sided copper-clad laminate, electroless plating is performed on the inner wall of the hole, or electrolytic plating is performed if necessary to form a connecting conductor, and only unnecessary portions of the copper foil on one side are etched. After removing and leaving the copper foil on the other side, stacking and integrating with other board, make a hole that penetrates the whole and metallize the inner wall of the hole, or wiring layer on the surface of the insulating board Is formed, a layer is formed on the surface of the wiring layer with a photosensitive insulating material, and the surface of this insulating material is roughened by irradiating with light so as to remove only the portion that becomes the conduction hole and developing, There is a method of forming a conductor by electroless plating the circuit conductor on the inner wall of the hole. In all of these techniques, necessary wiring layers are further formed by the same technique to form a multilayer structure.

【0007】第二の方法は、先に配線層を形成した基板
を積層しておいて、表面層とその表面層と接続を行う層
の接続を行う方法であって、導通穴を接続を行う層まで
にしかあけないことが特徴となっている。この方法の具
体例としては、複数の配線層とそれらを支える絶縁層を
交互に積層しておき、表面には銅箔を残しておき、表面
の回路と接続する箇所に接続する層に達する深さまで、
ドリルで穴をあけ、穴内壁を金属化する方法や、穴をあ
けるのにレーザ光を用い、レーザ光が接続を必要としな
い層までに照射されないように、接続する層の箇所に銅
箔を残しておく方法等がある。
The second method is a method in which the substrates on which the wiring layers have been previously formed are laminated and then the surface layer and the layer for connecting to the surface layer are connected, and the conductive holes are connected. The feature is that it can be opened only up to the layer. As a specific example of this method, a plurality of wiring layers and insulating layers supporting them are alternately laminated, a copper foil is left on the surface, and a depth reaching a layer to be connected to a circuit on the surface is reached. Well,
How to make a hole with a drill and metallize the inner wall of the hole, or use laser light to make a hole, and place a copper foil on the layer to be connected so that the laser light does not reach the layer that does not require connection. There are ways to leave it.

【0008】[0008]

【発明が解決しようとする課題】ところで、これらバイ
アホールを形成する従来方法においては、以下のような
課題があった。前記第一の方法において両面銅張り積層
板を使用する場合、片面に回路を形成するので基板の寸
法変化が起こり易く、複数の基板を重ねて積層する時
に、各配線層間の位置精度に十分の注意を払わなければ
ならず、また導通穴内壁の接続のために行うめっきによ
って他方の導体厚さが厚くなり、多層化した時に全体の
厚さを小さくすることが困難になる。また、感光性材料
を各配線層間の絶縁層として用いる場合、めっきの密着
力を高める粗化処理と、貫通穴を設けるための感光性を
同時に満足できる材料が少なく、現存する材料ではめっ
き皮膜の密着力は十分ではない。
The conventional method for forming these via holes has the following problems. When a double-sided copper-clad laminate is used in the first method, since the circuit is formed on one side, the dimensional change of the substrate is likely to occur, and when laminating and stacking a plurality of substrates, the positional accuracy between the wiring layers is sufficient. Care must be taken and the thickness of the other conductor is increased by the plating performed for connecting the inner wall of the conduction hole, which makes it difficult to reduce the total thickness when the multilayer structure is used. In addition, when a photosensitive material is used as an insulating layer between each wiring layer, there are few materials that can simultaneously satisfy the roughening treatment that enhances the adhesion of plating and the photosensitivity for forming a through hole. Adhesion is not enough.

【0009】前記第二の方法においてドリルを用いる場
合、基板厚さのばらつきがあり、接続する箇所でドリル
の進行を止める位置精度を高くできない。また、レーザ
を用いる場合、装置が高価である。この方法では、穴を
あける箇所において表面層と接続層の間には、他の層に
は配線ができない。
When a drill is used in the second method, there is variation in the thickness of the substrate, and it is not possible to increase the positional accuracy of stopping the progress of the drill at the connecting point. Moreover, when a laser is used, the device is expensive. In this method, wiring cannot be formed in another layer between the surface layer and the connection layer at the place where a hole is to be formed.

【0010】本発明は、層間接続が容易で、配線の密度
に優れた多層プリント配線板の製造法を提供することを
目的とする。
It is an object of the present invention to provide a method for manufacturing a multilayer printed wiring board which facilitates interlayer connection and is excellent in wiring density.

【0011】[0011]

【課題を解決するための手段】本発明の多層プリント配
線板の製造法は、以下の工程を含むことを特徴とするも
のである。すなわち、 (a)導電性を有する保持体の表面に所望の形状にめっ
きレジストを形成し、該保持体の除去条件と異なる金属
層Aとこの金属層Aの除去条件と異なる金属層Bをめっ
きして所望の回路パターンを形成し、前記めっきレジス
トを除去する工程 (b)前記保持体の表面に回路パターンを形成した面に
接着剤層を設け、この接着剤層をBステージにする工程 (c)前記基板に穴をあける工程 (d)前記穴をあけた基板の接着剤層側に、他の基板が
接触するように重ね合わせ、加圧加熱して積層一体化す
る工程 (e)前記積層一体化した基板の必要な箇所に導体回路
を形成するとともに、前記めっきにより形成した回路パ
ターンが露出するまで前記保持体を除去する工程
The method for manufacturing a multilayer printed wiring board according to the present invention is characterized by including the following steps. That is, (a) a plating resist is formed in a desired shape on the surface of a carrier having conductivity, and a metal layer A different from the condition for removing the carrier and a metal layer B different from the condition for removing the metal layer A are plated. To form a desired circuit pattern and remove the plating resist. (B) A step of providing an adhesive layer on the surface of the holding body on which the circuit pattern is formed, and using this adhesive layer as a B stage. c) A step of making a hole in the substrate. (d) A step of superposing the board having the holes on the adhesive layer side so that another board may come into contact therewith, and heating and pressurizing to integrate the layers. A step of forming a conductor circuit on a necessary portion of the laminated and integrated substrate and removing the holder until the circuit pattern formed by the plating is exposed.

【0012】また、保持体に形成した回路パターンがよ
り微細化になり、安定した回路形成を実現するために
は、以下の工程を用いることもできる。 (a)保持体の表面に回路パターンを形成する工程にお
いて、保持体の表面に所望の形状にめっきレジストを形
成し、該保持体とともに除去できる第1の金属層Eをめ
っきにより形成し、該保持体の除去条件と異なる金属層
Fとこの金属層Fの除去条件と異なる金属層Gとからな
る第2の金属層をめっきにより形成し、前記めっきレジ
ストを除去する工程 (b)前記保持体の表面に回路パターンを形成した面に
接着剤層を設け、この接着剤層Bステージにする工程 (c)前記基板に穴をあける工程 (d)前記穴をあけた基板の接着剤層側に、他の基板が
接触するように重ね合わせ、加圧加熱して積層一体化す
る工程 (e)前記積層一体化した基板の必要な箇所に導体回路
を形成するとともに、前記めっきにより形成した回路パ
ターンが露出するまで前記保持体を除去する工程
Further, in order to make the circuit pattern formed on the holder finer and realize stable circuit formation, the following steps can be used. (A) In the step of forming a circuit pattern on the surface of the holder, a plating resist is formed in a desired shape on the surface of the holder, and a first metal layer E that can be removed together with the holder is formed by plating. A step of forming a second metal layer composed of a metal layer F different from the removal conditions of the holder and a metal layer G different from the removal conditions of the metal layer F by plating, and removing the plating resist (b) the holder A step of forming an adhesive layer on the surface having a circuit pattern formed on its surface and using this as an adhesive layer B stage (c) a step of making a hole in the substrate (d) an adhesive layer side of the board having the holes A step of stacking so that other boards are in contact with each other, and heating and pressurizing to stack and integrate them. (E) A circuit pattern formed by plating while forming a conductor circuit at a required portion of the board Exposed Until the holder is removed

【0013】このような技術を用いて多層化するために
は、上記工程に続いて、以下の工程を設けることにより
可能である。 (f)導電性を有する他の保持体の表面に所望の形状に
めっきレジストを形成し、この他の保持体の除去条件と
異なる金属層Cとこの金属層Cの除去条件と異なる金属
層Dをめっきして所望の回路パターンを形成し、前記め
っきレジストを除去する工程 (g)前記他の保持体の表面に回路パターンを形成した
面に接着剤層を設け、この接着剤層Bステージにする工
程 (h)前記他の基板に穴をあける工程 (i)前記穴をあけた他の基板の接着剤層側に、前記工
程(e)で作製した基板が接触するように重ね合わせ、
加圧加熱して積層一体化する工程 (j)必要に応じて、前記工程(f)〜(i)を繰り返
し、多層化する工程
In order to form a multilayer using such a technique, it is possible to provide the following steps after the above steps. (F) A plating resist is formed in a desired shape on the surface of another holder having conductivity, and a metal layer C different from the removal conditions of the other holder and a metal layer D different from the removal conditions of the metal layer C. To form a desired circuit pattern and remove the plating resist. (G) An adhesive layer is provided on the surface of the other holding body on which the circuit pattern is formed, and the adhesive layer B stage is formed. And (h) a step of making a hole in the other substrate (i) a substrate made in the step (e) is superposed so as to come into contact with the adhesive layer side of the other substrate having the hole formed,
Step of heating and pressurizing to laminate and integrate (j) Steps of repeating the above steps (f) to (i) to form multiple layers, if necessary

【0014】あるいは、 (f)保持体の表面に回路パターンを形成する工程にお
いて、保持体の表面に所望の形状にめっきレジストを形
成し、該保持体とともに除去できる第1の金属層Hをめ
っきにより形成し、該保持体の除去条件と異なる金属層
Iとこの金属層Iの除去条件と異なる金属層Jとからな
る第2の金属層をめっきにより形成し、前記めっきレジ
ストを除去する工程 (g)前記他の保持体の表面に回路パターンを形成した
面に接着剤層を設け、この接着剤層をBステージにする
工程 (h)前記他の基板に穴をあける工程 (i)前記穴をあけた他の基板の接着剤層側に、前記工
程(e)で製作した基板が接触するように重ね合わせ、
加圧加熱して積層一体化する工程 (j)必要に応じて、前記工程(f)〜(i)を繰り返
し、多層化する工程
Alternatively, (f) in the step of forming a circuit pattern on the surface of the holder, a plating resist is formed in a desired shape on the surface of the holder, and a first metal layer H that can be removed together with the holder is plated. A step of forming a second metal layer, which is formed by the method described above, including a metal layer I different from the removal condition of the holder and a metal layer J different from the removal condition of the metal layer I, and removing the plating resist. g) a step of providing an adhesive layer on the surface of the other holding body on which a circuit pattern is formed and using this adhesive layer as a B stage (h) a step of making a hole in the other substrate (i) the hole On the adhesive layer side of the other substrate where the holes were opened so that the substrate manufactured in the step (e) comes into contact with the adhesive layer side,
Step of heating and pressurizing to laminate and integrate (j) Steps of repeating the above steps (f) to (i) to form multiple layers, if necessary

【0015】本発明に用いる保持体はステンレス板等に
剥離可能なようにめっきした銅箔でも良く、また、すで
に引き裂かれた銅箔、あるいは圧延された銅箔を用いる
こともできる。また、該保持体の除去条件と異なる金属
層とこの金属層の除去条件と異なる他の金属層として
は、金、ニッケル、はんだ、あるいは金と銅、ニッケル
と銅等で、単独の場合はそれ自身、2種類以上の場合は
該保持体に面している金属の除去条件が、該保持体と異
なる必要がある。該保持体とともに除去できる金属層
は、保持体と同質の金属が好ましく、厚さとしては、保
持体のわずかなきずやへこみや埋めることができれば良
く、約3μm位である。
The holder used in the present invention may be a copper foil which is detachably plated on a stainless steel plate or the like, or a copper foil which has already been torn or a rolled copper foil may be used. Further, the metal layer different from the removal condition of the holder and the other metal layer different from the removal condition of the metal layer are gold, nickel, solder, gold and copper, nickel and copper, etc. In the case of two or more types, the removal condition of the metal facing the holder needs to be different from that of the holder. The metal layer that can be removed together with the holding body is preferably a metal of the same quality as the holding body, and the thickness is about 3 μm as long as it can fill a slight flaw, dent, or fill in the holding body.

【0016】接着剤としては、エポキシ樹脂系接着剤、
アクリル変性樹脂系、あるいはポリイミド樹脂系接着剤
等が使用でき、これらをロールコーティング、ディップ
コーティングあるいはカーテンコーティング法等によっ
て塗布することができる。また、さらにこれらの接着剤
をフィルム化したものも使用でき、G604(日立化成
工業株式会社製、商品名)等のエポキシ接着フィルム、
パイララックス(デュポン社製、商品名)等のアクリル
変性樹脂フィルム、あるいはAS−2210(日立化成
工業株式会社製、商品名)等のポリイミド接着フィルム
等が使用できる。これらの接着フィルムを、めっきで回
路パターンを形成した導電性を有する保持体の回路形成
面に貼り合わせるのであるが、貼り合わせた後には、B
ステージの状態となっている必要がある。本発明でいう
Bステージとは、保持体の回路パターンを形成した面に
貼り合わせた状態で、40℃以下では粘着性を持たず、
その後の多層化接着によって、接着強度が0.8kgf/cm
2以上を与えることができる半硬化状態をいう。このよ
うなBステージ状態にする方法は、通常の樹脂のよう
に、完全には硬化しない温度と時間、加熱して行う。こ
の程度は、実験的に求めるのが通常である。また、加圧
加熱して積層一体化する工程において、このBステージ
の接着剤層の流動量は、基板の表面方向に対して200
μm未満であることが好ましい。この流動量が大きい
と、加圧加熱した時に、他の配線板の配線導体上に拡が
り、めっきによって接続される面積が小さくなり、接続
信頼性を低下させる。
As the adhesive, an epoxy resin adhesive,
Acrylic-modified resin-based or polyimide resin-based adhesives can be used, and these can be applied by roll coating, dip coating, curtain coating, or the like. Further, those obtained by film-forming these adhesives can also be used, and epoxy adhesive films such as G604 (trade name, manufactured by Hitachi Chemical Co., Ltd.),
An acrylic-modified resin film such as Pyrarax (manufactured by DuPont, trade name) or a polyimide adhesive film such as AS-2210 (manufactured by Hitachi Chemical Co., Ltd.) can be used. These adhesive films are adhered to the circuit-formed surface of a conductive support having a circuit pattern formed by plating.
Must be on stage. The B stage in the present invention is a state in which it is attached to the surface of the holding body on which the circuit pattern is formed, and it has no adhesiveness at 40 ° C. or lower,
Adhesive strength of 0.8 kgf / cm due to the subsequent multi-layered adhesion
A semi-cured state that can give 2 or more. Such a B-stage state method is carried out by heating at a temperature and for a time at which the resin does not completely cure like ordinary resins. This degree is usually obtained experimentally. Further, in the step of heating and pressurizing to laminate and integrate, the flow rate of the adhesive layer of the B stage is 200 with respect to the surface direction of the substrate.
It is preferably less than μm. When this flow amount is large, it spreads on the wiring conductor of another wiring board when it is pressurized and heated, and the area to be connected by plating becomes small, thus lowering the connection reliability.

【0017】[0017]

【作用】本発明による方法では、接着剤をBステージの
状態で用いるので穴あけ加工が容易であり、また、続く
加圧加熱によって他の配線板との接着が可能となる。さ
らに、表面パターンとなる導体回路を絶縁材料中に埋め
込む製造法によって微細配線パターンを形成することが
できるため、2次元的な高密度化も達成でき配線収容量
も大幅に向上させることができる。
In the method according to the present invention, since the adhesive is used in the state of B stage, it is easy to make a hole, and it is possible to adhere it to another wiring board by subsequent pressurizing and heating. Furthermore, since a fine wiring pattern can be formed by a manufacturing method in which a conductor circuit to be a surface pattern is embedded in an insulating material, it is possible to achieve a two-dimensional high density and significantly improve the wiring accommodation amount.

【0018】[0018]

【実施例】【Example】

実施例1 図1(a)に示すように、ステンレス表面を研磨後、全
面に20μm厚の硫酸銅めっきを行った(図1(b)に
示す。)。次に銅表面をサンドペーパーで研磨後、フォ
トレジストをロールラミネータによりラミネートし、ポ
ジマスクを当て紫外線を照射し、現像液で現像して、図
1(c)に示すように、めっき銅表面にレジストパター
ンを形成した。続いて、銅めっきを3μmの厚さで行
い、研磨でついたきずを埋め、金めっきを1μmの厚さ
で行い、さらに硫酸銅めっきを30μm行い、レジスト
剥離液でレジストを剥離して回路パターンを形成した
(図1(d)に示す。)。次に、前記ステンレス板を黒
色酸化処理を行い、回路パターン形成面に接着剤フィル
ムであるG604(日立化成工業株式会社製、商品名)
を貼り、圧力10kgf/cm2 、150℃で7分間加熱して
Bステージにした(図1(e)に示す。) 後、回路パターンの形成された銅箔をステンレス板より
剥がし取った(図1(f)に示す。)。続いて、図1
(g)に示すように、数値制御されたドリルマシンによ
り、回路パターンに合わせて接続箇所に穴をあける。こ
の時に、最も小さい穴径は、0.25mmであった。続い
て、前記穴をあけた基板の接着剤層側に、図1(h)に
示すような他の内層板が接触するように重ね合わせ、圧
力40kgf/cm2 、170℃で45分間加圧加熱して積層
一体化した(図1(i)示す。)。続いて、この積層し
た板全体を貫通する穴をあけ(図1(j)に示す。)、
全面に銅めっきを行った(図1(k)に示す。)。続い
て、必要な箇所にエッチングレジストを形成し、内蔵さ
れた金めっきが露出するまで表面の銅をエッチング除去
して、図1(l)に示すような所望の配線パターンが基
板に埋め込まれた多層プリント配線板を製作した。
Example 1 As shown in FIG. 1 (a), after polishing a stainless steel surface, copper sulfate plating with a thickness of 20 μm was performed on the entire surface (shown in FIG. 1 (b)). Next, after polishing the copper surface with sandpaper, a photoresist is laminated with a roll laminator, a positive mask is applied, ultraviolet rays are irradiated, and the film is developed with a developing solution. As shown in FIG. A pattern was formed. Subsequently, copper plating is performed to a thickness of 3 μm, flaws formed by polishing are filled, gold plating is performed to a thickness of 1 μm, copper sulfate plating is performed to 30 μm, and the resist is removed with a resist remover to remove the circuit pattern. Was formed (as shown in FIG. 1 (d)). Next, the stainless steel plate is subjected to black oxidation treatment, and G604 (manufactured by Hitachi Chemical Co., Ltd.), which is an adhesive film on the circuit pattern forming surface.
Paste, pressure 10kgf / cm 2 After heating for 7 minutes at 150 ° C. for B stage (shown in FIG. 1E), the copper foil having the circuit pattern formed thereon was peeled off from the stainless steel plate (shown in FIG. 1F). . Then, Fig. 1
As shown in (g), a numerically controlled drill machine is used to make holes at the connection points according to the circuit pattern. At this time, the smallest hole diameter was 0.25 mm. Subsequently, the substrate having the holes is overlaid on the adhesive layer side so that another inner layer plate as shown in FIG. 1 (h) is in contact, and the pressure is 40 kgf / cm 2 Then, the layers were integrated by heating under pressure at 170 ° C. for 45 minutes (shown in FIG. 1 (i)). Then, a hole is formed through the laminated plates (shown in FIG. 1 (j)),
Copper plating was performed on the entire surface (shown in FIG. 1 (k)). Subsequently, an etching resist was formed at a required position, the surface copper was removed by etching until the embedded gold plating was exposed, and a desired wiring pattern as shown in FIG. 1L was embedded in the substrate. A multilayer printed wiring board was manufactured.

【0019】実施例2 図2(a)に示すように、ステンレス表面を研磨後、全
面に20μm厚の硫酸銅めっきを行った(図2(b)に
示す。)。次に銅表面をサンドペーパーで研磨後、フォ
トレジストをロールラミネータによりラミネートし、ポ
ジマスクを当て紫外線を照射し、現像液で現像して、図
2(c)に示すように、めっき銅表面にレジストパター
ンを形成した。続いて、金めっきを1μmの厚さで行
い、さらに硫酸銅めっきを30μm行い、レジスト剥離
液でレジストを剥離し回路パターンを形成した(図2
(d)に示す。)。次に、前記ステンレス板を黒色酸化
処理を行い、回路パターン形成面に接着剤フィルムであ
るG604(日立化成工業株式会社製、商品名)層を設
け、圧力10kgf/cm2、150℃で7分間加熱してBス
テージにした(図2(e)に示す。)後、回路パターン
の形成された銅箔をステンレス板より剥がし取った(図
2(f)に示す。)。続いて、図2(g)に示すよう
に、数値制御されたドリルマシンにより、回路パターン
に合わせて接続箇所に穴をあける。この時に、最も小さ
い穴径は、0.25mmであった。続いて、前記穴をあけ
た基板の接着剤層側に、図2(h)に示すような他の内
層板が接触するように重ね合わせ、加圧加熱して積層一
体化した(図2(i)に示す。)。この時の積層条件
は、圧力40kgf/cm2、170℃で45分間行った。続
いて、この積層した板の表面に厚さ15μmの銅めっき
を行った(図2(j)に示す。)。次に、必要な箇所に
エッチングレジストを形成し、内蔵された金めっきが露
出するまで表面の銅をエッチング除去して、回路導体を
形成した(図2(k)に示す。)。このようにして作製
した配線板を、別に図2(a)〜(g)と同じ工程で作
製した基板の接着剤層側に接触するように重ね合わせ、
加圧加熱して積層一体化した(図2(l)に示す。)。
この時の積層条件は、圧力40kgf/cm2 、170℃で4
5分間であった。このような多層化を繰り返し、最終の
積層化の後に、エッチングレジストを形成し、内蔵され
た金めっき回路パターンが露出するまで表面の銅をエッ
チング除去して、図2(m)に示すような所望の配線パ
ターンが基板に埋め込まれた多層プリント配線板を製作
した。
Example 2 As shown in FIG. 2 (a), after polishing the stainless steel surface, copper sulfate plating with a thickness of 20 μm was performed on the entire surface (shown in FIG. 2 (b)). Next, after polishing the copper surface with sandpaper, a photoresist is laminated by a roll laminator, a positive mask is applied, and ultraviolet rays are radiated, followed by development with a developing solution. As shown in FIG. A pattern was formed. Subsequently, gold plating was performed to a thickness of 1 μm, copper sulfate plating was further performed to 30 μm, and the resist was removed with a resist remover to form a circuit pattern (FIG. 2).
It shows in (d). ). Next, the stainless plate is subjected to black oxidation treatment, a G604 (Hitachi Chemical Co., Ltd., trade name) layer, which is an adhesive film, is provided on the circuit pattern forming surface, and the pressure is 10 kgf / cm 2 at 150 ° C. for 7 minutes. After heating to the B stage (shown in FIG. 2E), the copper foil having the circuit pattern formed thereon was peeled off from the stainless steel plate (shown in FIG. 2F). Subsequently, as shown in FIG. 2G, a numerically controlled drill machine is used to make holes at the connection points in accordance with the circuit pattern. At this time, the smallest hole diameter was 0.25 mm. Subsequently, the substrate having the holes is laminated on the adhesive layer side so that another inner layer plate as shown in FIG. i)). The lamination conditions at this time were such that the pressure was 40 kgf / cm 2 and 170 ° C. for 45 minutes. Subsequently, the surface of this laminated plate was plated with copper having a thickness of 15 μm (shown in FIG. 2 (j)). Next, an etching resist was formed in a required portion, and copper on the surface was removed by etching until the built-in gold plating was exposed to form a circuit conductor (shown in FIG. 2 (k)). The wiring board manufactured in this manner is separately superposed so as to come into contact with the adhesive layer side of the substrate manufactured in the same step as in FIGS. 2A to 2G,
The layers were integrated by heating under pressure (shown in FIG. 2 (l)).
The lamination conditions at this time are pressure 40kgf / cm 2 , At 170 ° C 4
It was 5 minutes. Such multilayering is repeated, and after the final lamination, an etching resist is formed, and the copper on the surface is removed by etching until the embedded gold-plated circuit pattern is exposed, as shown in FIG. 2 (m). A multilayer printed wiring board in which a desired wiring pattern was embedded in a substrate was manufactured.

【0020】[0020]

【発明の効果】以上に説明したように、本発明によって
配線密度に優れ且つ簡便な多層プリント配線板の製造法
を提供することができ、次のような利点が達成される。 (1)予め微細回路パターンを形成した後に積層するの
で、積層前に検査でき歩留りが向上するとともに、積層
前に回路パターンに合わせてバイアホール穴あけをする
ので、表面層回路パターンと穴間の位置精度が向上す
る。 (2)多層化接着する前にバイアホール穴あけをするの
で、穴あけした穴から内層基板の回路パターンを確認で
き、層間位置精度が向上する。 (3)薄物対応の多層プリント配線板を製造した場合、
表面回路パターンは基板に埋め込まれエッチング液に耐
食性のある金属層に保護されているので、基板の凹凸や
うねりに関係なく、線幅精度が高い。
As described above, according to the present invention, it is possible to provide a simple method for producing a multilayer printed wiring board which is excellent in wiring density and achieves the following advantages. (1) Since a fine circuit pattern is formed in advance and then laminated, an inspection can be performed before lamination to improve the yield, and a via hole is drilled according to the circuit pattern before lamination, so that the position between the surface layer circuit pattern and the hole is determined. Accuracy is improved. (2) Since the via holes are drilled before the multi-layered bonding, the circuit pattern of the inner layer substrate can be confirmed from the drilled holes, and the interlayer position accuracy is improved. (3) When manufacturing a multilayer printed wiring board for thin products,
Since the surface circuit pattern is embedded in the substrate and protected by the metal layer that is corrosion resistant to the etching solution, the line width accuracy is high regardless of the irregularities and undulations of the substrate.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(l)は、本発明の一実施例を説明す
るための各工程における断面図である。
1A to 1L are cross-sectional views in each step for explaining an embodiment of the present invention.

【図2】(a)〜(m)は、本発明の他の実施例を説明
するための各工程における断面図である。
2A to 2M are cross-sectional views in each step for explaining another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1.ステンレス板 2.硫酸銅めっき 3.レジストパターン 4.めっき回路パ
ターン 5.接着剤 6.非貫通穴とな
る穴 7.内層板 8.非貫通穴 9.貫通穴 10.めっき銅 11.エッチングレジストにより形成した回路導体 12.内蔵された回路パターン
1. Stainless plate 2. Copper sulfate plating 3. Resist pattern 4. Plating circuit pattern 5. Adhesive 6. Holes that are non-through holes 7. Inner layer plate 8. Non-through hole 9. Through hole 10. Plated copper 11. Circuit conductor formed by etching resist 12. Built-in circuit pattern

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山岸 一次 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館工場内 (72)発明者 田村 義広 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館工場内 (72)発明者 河田 健一 茨城県下館市大字小川1500番地 日立化成 工業株式会社下館工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazushi Yamagishi 1500 Ogawa, Shimodate City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Shimodate factory (72) Inventor Yoshihiro Tamura 1500 Ogawa, Shimodate City, Ibaraki Hitachi Chemical Co., Ltd. Shimodate Factory (72) Inventor Kenichi Kawata 1500 Ogawa, Shimodate City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Shimodate Factory

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】以下の工程を含むことを特徴とする多層プ
リント配線板の製造法。 (a)導電性を有する保持体の表面に所望の形状にめっ
きレジストを形成し、該保持体の除去条件と異なる金属
層Aとこの金属層Aの除去条件と異なる金属層Bをめっ
きして所望の回路パターンを形成し、前記めっきレジス
トを除去する工程 (b)前記保持体の表面に回路パターンを形成した面に
接着剤層を設け、この接着剤層Bステージにする工程 (c)前記基板に穴をあける工程 (d)前記穴をあけた基板の接着剤層側に、他の基板が
接触するように重ね合わせ、加圧加熱して積層一体化す
る工程 (e)前記積層一体化した基板の必要な箇所に導体回路
を形成するとともに、前記めっきにより形成した回路パ
ターンが露出するまで前記保持体を除去する工程
1. A method for manufacturing a multilayer printed wiring board, comprising the following steps. (A) A plating resist is formed in a desired shape on the surface of a conductive support, and a metal layer A different from the removal condition of the support and a metal layer B different from the removal condition of the metal layer A are plated. Forming a desired circuit pattern and removing the plating resist; (b) providing an adhesive layer on the surface of the holding body on which the circuit pattern is formed, and using this as an adhesive layer B stage (c) Step of forming a hole in the substrate (d) Step of stacking the holed substrate on the adhesive layer side so that another substrate is in contact with the substrate, pressurizing and heating to integrate the layers (e) The integrated layers Forming a conductor circuit on a required portion of the formed substrate and removing the holder until the circuit pattern formed by the plating is exposed.
【請求項2】以下の工程を含むことを特徴とする多層プ
リント配線板の製造法。 (a)導電性を有する保持体の表面に所望の形状にめっ
きレジストを形成し、該保持体の除去条件と異なる金属
層Aとこの金属層Aの除去条件と異なる金属層Bをめっ
きして所望の回路パターンを形成し、前記めっきレジス
トを除去する工程 (b)前記保持体の表面に回路パターンを形成した面に
接着剤層を設け、この接着剤層Bステージにする工程 (c)前記基板に穴をあける工程 (d)前記穴をあけた基板の接着剤層側に、他の基板が
接触するように重ね合わせ、加圧加熱して積層一体化す
る工程 (e)前記積層一体化した基板の必要な箇所に導体回路
を形成するとともに、前記めっきにより形成した回路パ
ターンが露出するまで前記保持体を除去する工程 (f)導電性を有する他の保持体の表面に所望の形状に
めっきレジストを形成し、この他の保持体の除去条件と
異なる金属層Cとこの金属層Cの除去条件と異なる金属
層Dをめっきして所望の回路パターンを形成し、前記め
っきレジストを除去する工程 (g)前記他の保持体の表面に回路パターンを形成した
面に接着剤層を設け、この接着剤層をBステージにする
工程 (h)前記他の基板に穴をあける工程 (i)前記穴をあけた他の基板の接着剤層側に、前記工
程(e)で製作した基板が接触するように重ね合わせ、
加圧加熱して積層一体化する工程 (j)必要に応じて、前記工程(f)〜(i)を繰り返
し、多層化する工程
2. A method for manufacturing a multilayer printed wiring board, comprising the following steps. (A) A plating resist is formed in a desired shape on the surface of a conductive support, and a metal layer A different from the removal condition of the support and a metal layer B different from the removal condition of the metal layer A are plated. Forming a desired circuit pattern and removing the plating resist; (b) providing an adhesive layer on the surface of the holding body on which the circuit pattern is formed, and using this as an adhesive layer B stage (c) Step of forming a hole in the substrate (d) Step of stacking the holed substrate on the adhesive layer side so that another substrate is in contact with the substrate, pressurizing and heating to integrate the layers (e) The integrated layers Forming a conductor circuit on a necessary portion of the formed substrate and removing the holding body until the circuit pattern formed by the plating is exposed. (F) Forming a desired shape on the surface of another holding body having conductivity. Shape plating resist A step of forming a desired circuit pattern by plating a metal layer C different from the removal conditions of the other holders and a metal layer D different from the removal conditions of the metal layer C, and removing the plating resist (g) A step of providing an adhesive layer on the surface of the other holding body on which a circuit pattern is formed and using this adhesive layer as a B stage (h) making a hole in the other substrate (i) making the hole The other substrate is superposed on the adhesive layer side so that the substrate manufactured in the step (e) comes into contact with the adhesive layer side,
Step of heating and pressurizing to laminate and integrate (j) Steps of repeating the above steps (f) to (i) to form multiple layers, if necessary
【請求項3】保持体の表面に回路パターンを形成する工
程において、保持体の表面に所望の形状にめっきレジス
トを形成し、該保持体とともに除去できる第1の金属層
Eをめっきにより形成し、該保持体の除去条件と異なる
金属層Fとこの金属層Fの除去条件と異なる金属層Gと
からなる第2の金属層をめっきにより形成し、前記めっ
きレジストを除去することを特徴とする請求項1または
2に記載の多層プリント配線板の製造法
3. In the step of forming a circuit pattern on the surface of a holder, a plating resist is formed in a desired shape on the surface of the holder, and a first metal layer E that can be removed together with the holder is formed by plating. A second metal layer comprising a metal layer F different from the removal condition of the holder and a metal layer G different from the removal condition of the metal layer F is formed by plating, and the plating resist is removed. The method for manufacturing a multilayer printed wiring board according to claim 1 or 2.
【請求項4】加圧加熱して積層一体化する工程におい
て、Bステージの接着剤層の流動量が基板の表面方向に
対して200μm未満である接着剤を用いることを特徴
とする請求項1〜3のうちいずれかに記載の多層プリン
ト配線板の製造法。
4. An adhesive having a flow rate of the adhesive layer of B stage of less than 200 μm with respect to the surface direction of the substrate is used in the step of laminating and integrating by heating under pressure. 4. The method for manufacturing a multilayer printed wiring board according to any one of 3 to 3.
JP12622994A 1994-06-08 1994-06-08 Manufacturing method of multilayer printed wiring board Expired - Fee Related JP3620065B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12622994A JP3620065B2 (en) 1994-06-08 1994-06-08 Manufacturing method of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12622994A JP3620065B2 (en) 1994-06-08 1994-06-08 Manufacturing method of multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH07336050A true JPH07336050A (en) 1995-12-22
JP3620065B2 JP3620065B2 (en) 2005-02-16

Family

ID=14929973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12622994A Expired - Fee Related JP3620065B2 (en) 1994-06-08 1994-06-08 Manufacturing method of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP3620065B2 (en)

Also Published As

Publication number Publication date
JP3620065B2 (en) 2005-02-16

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