JPH07335779A - Multi-chip module - Google Patents

Multi-chip module

Info

Publication number
JPH07335779A
JPH07335779A JP6126299A JP12629994A JPH07335779A JP H07335779 A JPH07335779 A JP H07335779A JP 6126299 A JP6126299 A JP 6126299A JP 12629994 A JP12629994 A JP 12629994A JP H07335779 A JPH07335779 A JP H07335779A
Authority
JP
Japan
Prior art keywords
layer
dielectric
insulating layer
insulating
chip module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6126299A
Other languages
Japanese (ja)
Inventor
Kenzo Doi
謙三 土居
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6126299A priority Critical patent/JPH07335779A/en
Publication of JPH07335779A publication Critical patent/JPH07335779A/en
Withdrawn legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To provide a multi-chip module board provided with a prescribed electrostatic capacity between a power source layer and a grounding layer. CONSTITUTION:On an insulating substrate 2, a grounding layer 3, a first insulating layer, a power source,layer 5, a second insulating layer 6, a first signal layer 7 and a third insulating layer 8 are successively laminated, and a microwave circuit is formed. A multi-chip module is provided by mounting a semiconductor integrated circuit chip on the third insulating layer 8, which is the topmost layer. The first insulating layer between the grounding layer 3 and the power source layer 5 is formed of the composite dielectric layer 13, which is composed of the two layers, which are a dielectric with a high dielectric constant and an organic or inorganic dielectric with excellent electric characteristics.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は特性を向上したマルチチ
ップモジュール(Multi Chip Module 略称MCM)に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi chip module (abbreviated as MCM) having improved characteristics.

【0002】大量の情報を迅速に処理する必要から、情
報処理装置の主体を構成する半導体装置は単位素子の小
型化による大容量化が進んでLSIやVLSIが実用化
されており、更にULSIの実用化が進められている
が、これと共に実装法も進歩し、複数のフリップ・チッ
プ・タイプの半導体素子をシリコン(Si)基板に形成した
多層回路基板上に搭載し、これを取り替え単位とするM
CMが実用化されつゝある。
Since it is necessary to process a large amount of information quickly, the semiconductor device that constitutes the main body of an information processing device has a large capacity due to the miniaturization of unit elements, and LSI and VLSI have been put into practical use. Although it is being put to practical use, the mounting method is also advancing along with this, and multiple flip-chip type semiconductor elements are mounted on a multilayer circuit board formed on a silicon (Si) substrate, and this is used as a replacement unit. M
Commercialization is in full swing.

【0003】[0003]

【従来の技術】MCM用基板については現在までに各種
のものが提案されているが、それぞれ長所と短所があ
り、未だ決定的なものは存在しない。
2. Description of the Related Art Various types of MCM substrates have been proposed to date, but each has its advantages and disadvantages, and there is no definitive one yet.

【0004】図2は代表的なMCM用基板の構成を示す
もので、二酸化シリコン(SiO2)層1を被覆して電気的
に絶縁したシリコン(Si) 基板2の上に、接地層3,第
1の絶縁層4,電源層5,第2の絶縁層6,第1の信号
層7,第3の絶縁層8と順次積層し、回路が複雑な場合
は更に、この上に第2の信号層, 絶縁層と順次に積層し
てMCM基板が形成されており、この上に複数の半導体
集積回路(略してIC)9がマトリックス状に配列して
搭載されている。
FIG. 2 shows the structure of a typical MCM substrate, in which a ground layer 3, a silicon (Si) substrate 2 covered with a silicon dioxide (SiO 2 ) layer 1 and electrically insulated. The first insulating layer 4, the power supply layer 5, the second insulating layer 6, the first signal layer 7, and the third insulating layer 8 are sequentially stacked, and when the circuit is complicated, the second insulating layer is further formed on the second insulating layer. An MCM substrate is formed by sequentially stacking a signal layer and an insulating layer, and a plurality of semiconductor integrated circuits (abbreviated as ICs) 9 are arranged and mounted in a matrix on the MCM substrate.

【0005】そして、IC9と信号層7,電源層5,接
地層3はそれぞれ図示を省略したビア(Via )により回
路接続されている。なお、この図2は理解を容易にする
ために信号層が一層のみの最も簡単な構成を示してい
る。
The IC 9, the signal layer 7, the power supply layer 5, and the ground layer 3 are circuit-connected by vias (not shown). Note that FIG. 2 shows the simplest configuration with only one signal layer for easy understanding.

【0006】このように、MCMは接地層3/電源層5
/信号層7と導電層が絶縁層を介して積層して形成され
ているが、動作に当たって多数のIC9が同時スイッチ
ングを行なう場合は、多量の電流が一時に流れることか
ら電源電圧が降下する結果として電源ノイズが発生する
と云う問題があり、この電源ノイズを除去する方法とし
て電源層5と接地層3との間にコンデンサを介在させて
いる。
As described above, the MCM has the ground layer 3 / power source layer 5
/ The signal layer 7 and the conductive layer are formed by laminating via an insulating layer. However, when a large number of ICs 9 simultaneously switch during operation, a large amount of current flows at a time, resulting in a drop in the power supply voltage. However, there is a problem that power supply noise is generated. As a method of removing this power supply noise, a capacitor is interposed between the power supply layer 5 and the ground layer 3.

【0007】すなわち、その方法として、IC9を搭載
する第3の絶縁層8の上にセラミックのチップコンデン
サを搭載し、電源層5と接地層3とをビアにより回路接
続する方法が採られているが、線路のインダクタンスが
大きくなることから、適当ではない。
That is, as a method therefor, there is adopted a method in which a ceramic chip capacitor is mounted on the third insulating layer 8 on which the IC 9 is mounted and the power supply layer 5 and the ground layer 3 are circuit-connected by vias. However, this is not suitable because the line inductance increases.

【0008】また、第1の絶縁層4の構成材料として一
般にはポリイミドなどの樹脂が使用されているが、この
代わりに接地層3をアルミニウム(Al)で形成し、これ
を陽極酸化して形成した酸化アルミニウムを誘電体とし
て使用することが提案されている。
A resin such as polyimide is generally used as a constituent material of the first insulating layer 4. Instead of this, the ground layer 3 is formed of aluminum (Al) and anodized to form it. It has been proposed to use the above mentioned aluminum oxide as a dielectric.

【0009】然し、陽極酸化により生じた酸化アルミニ
ウムは誘電特性の優れたアルミナ(Al2O3)とは結晶構造
が異なっており、また、不純物元素の存在によるピンホ
ールがあり、また、厚さが1μm 以下と薄くしかできな
いことから、短絡が発生し易い。
However, aluminum oxide produced by anodic oxidation has a different crystal structure from alumina (Al 2 O 3 ) which has excellent dielectric properties, has pinholes due to the presence of impurity elements, and has a thickness Since it can be made as thin as 1 μm or less, a short circuit easily occurs.

【0010】これらのことから、別の方法で電源層5と
接地層3の間にコンデンサを形成し、電源層5に生ずる
電源ノイズを除去する構成が求められている。
Therefore, there is a demand for a structure in which a capacitor is formed between the power supply layer 5 and the ground layer 3 by another method to remove power supply noise generated in the power supply layer 5.

【0011】[0011]

【発明が解決しようとする課題】MCMはSi基板上に接
地層/電源層/信号層と多層構造をとって形成されてい
るが、マトリックス状に配列しているICが同時スイッ
チングを行なう場合などに電源ノイズを生ずることか
ら、このノイズを容量接続により除きたい。そこで電源
層と接地層との間に必要とする静電容量を形成すること
が課題である。
The MCM is formed on the Si substrate in a multilayer structure of a ground layer / power source layer / signal layer. When the ICs arranged in a matrix form simultaneous switching, etc. Since power supply noise is generated in, we want to remove this noise by capacitive connection. Therefore, it is a problem to form a necessary capacitance between the power supply layer and the ground layer.

【0012】[0012]

【課題を解決するための手段】上記の課題は絶縁基板上
に接地層,第1の絶縁層,電源層,第2の絶縁層,信号
層,第3の絶縁層と順次に積層して立体回路を形成する
と共に、最上層の第3の絶縁層にチップ状の半導体集積
回路を搭載してなるマルチチップモジュールにおいて、
接地層と電源層との間の第1の絶縁層を高誘電率誘電体
と電気的特性の優れた有機または無機誘電体の二層から
なる複合誘電体層で形成することにより解決することが
できる。
[Means for Solving the Problems] The above problems are three-dimensionally formed by sequentially laminating a ground layer, a first insulating layer, a power source layer, a second insulating layer, a signal layer, and a third insulating layer on an insulating substrate. In a multi-chip module in which a circuit is formed and a chip-shaped semiconductor integrated circuit is mounted on the uppermost third insulating layer,
The problem can be solved by forming the first insulating layer between the ground layer and the power supply layer with a composite dielectric layer composed of two layers of a high dielectric constant dielectric and an organic or inorganic dielectric having excellent electrical characteristics. it can.

【0013】[0013]

【作用】MCM用基板の電源層と接地層との間にコンデ
ンサを形成方法として、この間に存在する絶縁層を高誘
電率誘電体で形成することが考えられる。すなわち、チ
タン酸ストロンチウム(SrTiO3),チタン酸バリウム(Ba
TiO3),チタン酸ジルコン酸鉛(略称PZT)などペロブ
スカイト(Perovskite)型構造をとるセラミックスをス
パッタ法などでMCM基板を構成する接地層の上に形成
し、この上に必要とする配線面積を備えた電源層をパタ
ーン形成すれば必要とする静電容量を形成できる筈であ
る。
As a method of forming a capacitor between the power supply layer and the ground layer of the MCM substrate, it is conceivable to form the insulating layer existing between them with a high dielectric constant dielectric. That is, strontium titanate (SrTiO 3 ), barium titanate (Ba
TiO 3 ), lead zirconate titanate (abbreviated as PZT) and other ceramics having a perovskite structure are formed on the ground layer constituting the MCM substrate by a sputtering method or the like, and a required wiring area is formed on the ground layer. The required capacitance should be able to be formed by patterning the provided power supply layer.

【0014】然し、このようにして膜形成される高誘電
率誘電体は高温焼成ができないために安定した構造をと
ることができず、そのため絶縁抵抗値が低く、漏洩電流
が大きいと云う問題があり、そのためにMCM基板には
使われていない。
However, since the high dielectric constant dielectric film thus formed cannot be fired at a high temperature, a stable structure cannot be obtained, and therefore, there are problems that the insulation resistance value is low and the leakage current is large. Yes, and for that reason it is not used in MCM substrates.

【0015】然し、発明者はこれらペルブスカイト型構
造をとるセラミックスの誘電率が大きいことに着目し
た。そして、かゝる高誘電率誘電体層を電気的特性の優
れた誘電体層と積層することにより、絶縁抵抗を増加さ
せ、絶縁層として使用可能とするものである。
However, the inventor has paid attention to the fact that the ceramic having such a perovskite structure has a large dielectric constant. Then, by laminating such a high-dielectric-constant dielectric layer with a dielectric layer having excellent electrical characteristics, the insulation resistance is increased and the dielectric layer can be used as an insulating layer.

【0016】なお、このように二つの誘電体層を積層し
て複合誘電体とすると、電気的特性は改良されるもの
ゝ、複合誘電率は低誘電率材料により支配されることか
ら、特性の優れた低誘電率材料はなるべく薄く形成する
必要がある。
When the two dielectric layers are laminated to form a composite dielectric as described above, the electrical characteristics are improved. However, the composite dielectric constant is dominated by the low dielectric constant material. An excellent low dielectric constant material needs to be formed as thin as possible.

【0017】発明者は、このような構成をとる場合は大
きな静電容量値は期待できないものゝ、MCMの信号周
波数は数百MHzと高く、また、必要とする静電容量は数
〜数10 nFの大きさであることからして、かゝる構造で
必要とする静電容量を得ることができることを見出し
た。
The inventor cannot expect a large capacitance value when such a configuration is adopted. The signal frequency of the MCM is as high as several hundreds MHz, and the required capacitance is several to several tens. From the size of nF, it was found that the required capacitance can be obtained with such a structure.

【0018】なお、ペロブスカイト型構造をとる高誘電
率誘電体としては、SrTiO3,BaTiO3,PZT,(Sr1-x
Bax )TiO3 などがあり、一方、電気的特性の優れた誘電
体としては二酸化シリコン(SiO2),スピン・オン・グ
ラス(略称SOG)などの酸化硅素化合物やポリイミド
などの樹脂がある。
As the high dielectric constant dielectric material having the perovskite structure, SrTiO 3 , BaTiO 3 , PZT, (Sr 1-x
Ba x ) TiO 3 and the like. On the other hand, examples of dielectrics having excellent electric characteristics include silicon dioxide (SiO 2 ), spin-on-glass (abbreviated as SOG) and other silicon oxide compounds, and resins such as polyimide.

【0019】こゝで、ペロブスカイト型構造をとる高誘
電率誘電体としてSrTiO3を用い、これをSiO2,SOGお
よびポリイミドと組合せたときの複合誘電率を示すと次
のようになる。
Here, the composite permittivity when SrTiO 3 is used as a high-permittivity dielectric having a perovskite structure and is combined with SiO 2 , SOG and polyimide is as follows.

【0020】[0020]

【表1】 本発明を実施するにはMCM基板の形成に先立って電源
層と接地層との間の第1の絶縁層を構成する高誘電率誘
電体と特性の優れた誘電体との組合せと厚さを予め決め
て複合誘電率を求め、これにより電源層を形成する線路
をパターン設計し、必要とする静電容量を得るものであ
る。
[Table 1] In order to carry out the present invention, a combination and a thickness of a high dielectric constant dielectric material forming a first insulating layer between a power supply layer and a ground layer and a dielectric material having excellent characteristics are formed prior to formation of an MCM substrate. The composite permittivity is determined in advance and the line forming the power supply layer is pattern-designed to obtain the required capacitance.

【0021】[0021]

【実施例】【Example】

実施例1:(図1関連) 熱処理により表面にSiO2層1を設けて絶縁処理したSi基
板2の上にスパッタ法を用いてクロム(Cr) /銅(Cu)
/Crの三層構造をとる接地層3を形成した。
Example 1: (Refer to FIG. 1) Chromium (Cr) / copper (Cu) was formed on a Si substrate 2 which was subjected to an insulation treatment by providing a SiO 2 layer 1 on the surface by heat treatment by a sputtering method.
A ground layer 3 having a three-layer structure of / Cr was formed.

【0022】こゝで、Crは基板との接着性を向上するた
めで、厚さは約1000Åであり、また、Cuの厚さは2μm
である。次に、Si基板2を再びスパッタ装置にセット
し、基板温度を400 ℃に保ちながらSrTiO3を0.8 μm の
厚さになるまでスパッタして、SrTiO3層11を形成した。
Here, Cr is for improving the adhesion to the substrate, the thickness is about 1000Å, and the thickness of Cu is 2 μm.
Is. Then, it sets again a sputtering apparatus, the Si substrate 2, while keeping the substrate temperature at 400 ° C. by sputtering until the SrTiO 3 in a thickness of 0.8 [mu] m, to form a SrTiO 3 layer 11.

【0023】次に、N-メチルピロリドンで粘度調整した
ポリアミック酸をキュア後の厚さが0.2 μm となるよう
に塗布し、乾燥させた後、350 ℃で3時間加熱してキュ
アを行い、ポリイミド層12を形成した。
Next, a polyamic acid whose viscosity was adjusted with N-methylpyrrolidone was applied so that the thickness after curing would be 0.2 μm, dried, and then heated at 350 ° C. for 3 hours to be cured to obtain a polyimide. Layer 12 was formed.

【0024】このようにして形成したSrTiO3層11とポリ
イミド層12よりなる複合誘電体層13の複合誘電率は約16
であり、1μm の厚さの複合誘電体層13から14.1 nF/c
m2の静電容量を得ることができる。
The composite dielectric constant of the composite dielectric layer 13 composed of the SrTiO 3 layer 11 and the polyimide layer 12 thus formed is about 16
From 1 μm thick composite dielectric layer 13 to 14.1 nF / c
Capacitance of m 2 can be obtained.

【0025】次に、この複合誘電体層13の上に先と同様
にスパッタ法を用いてCr/Cu/Crの三層構造をとる電源層
5を形成し、写真蝕刻技術(ホトリソグラフィ)を用い
て、選択エッチングし、必要とする静電容量をもつ電源
配線をパターン形成した。
Next, the power source layer 5 having a three-layer structure of Cr / Cu / Cr is formed on the composite dielectric layer 13 by the sputtering method as described above, and the photolithography technique (photolithography) is applied. It was selectively etched to form a power supply wiring having a required capacitance.

【0026】次に、この上に先と同様にN-メチルピロリ
ドンで粘度調整したポリアミック酸をキュア後の厚さが
5μm となるように塗布し、乾燥させた後、350 ℃で3
時間加熱してキュアを行い、ポリイミドよりなる第2の
絶縁層6を形成した。
Then, a polyamic acid, the viscosity of which was adjusted with N-methylpyrrolidone in the same manner as above, was applied thereon so that the thickness after curing would be 5 μm, and after drying, it was dried at 350 ° C. for 3 hours.
The second insulating layer 6 made of polyimide was formed by heating for curing for a time.

【0027】次に、この上に従来と同様にCr/Cu/Crの膜
形成を行なった後、選択エッチングして第1の信号層7
を作り、更にこの上にポリイミドよりなり、厚さが5μ
m の第3の絶縁層8を形成することによりMCM基板が
完成した。
Next, a Cr / Cu / Cr film is formed on this layer in the same manner as in the prior art, and then selective etching is performed to form the first signal layer 7.
Made of polyimide, and the thickness is 5μ.
An MCM substrate was completed by forming m 3rd insulating layer 8.

【0028】[0028]

【発明の効果】本発明の実施によりMCM基板を構成す
る電源層と接地層との間に必要とする静電容量を介在さ
せることができ、これにより電源ノイズを除去すること
ができる。
By implementing the present invention, a required capacitance can be interposed between the power supply layer and the ground layer which form the MCM substrate, and thereby the power supply noise can be removed.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明を実施したMCM基板の断面図であ
る。
FIG. 1 is a cross-sectional view of an MCM substrate embodying the present invention.

【図2】 MCMの構成を示す断面図である。FIG. 2 is a cross-sectional view showing the structure of an MCM.

【符号の説明】[Explanation of symbols]

1 SiO2層 2 Si基板 3 接地層 4 第1の絶縁層 5 電源層 6 第2の絶縁層 7 第1の信号層 8 第3の絶縁層 13 複合誘電体層1 SiO 2 Layer 2 Si Substrate 3 Ground Layer 4 First Insulating Layer 5 Power Supply Layer 6 Second Insulating Layer 7 First Signal Layer 8 Third Insulating Layer 13 Composite Dielectric Layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/14 R 23/52 B ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 23/14 R 23/52 B

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板(2)上に接地層(3),第1
の絶縁層(4),電源層(5),第2の絶縁層(6),
第1の信号層(7),第3の絶縁層(8)と順次に積層
して立体回路を形成すると共に、最上層にある第3の絶
縁層(8)にチップ状の半導体集積回路(9)を搭載し
てなるマルチチップモジュールにおいて、 前記第1の絶縁層(4)を高誘電率誘電体と、有機また
は無機誘電体との二層からなる複合誘電体層(13)で形
成してなることを特徴とするマルチチップモジュール。
1. A ground layer (3), a first layer on an insulating substrate (2).
Insulation layer (4), power supply layer (5), second insulation layer (6),
The first signal layer (7) and the third insulating layer (8) are sequentially laminated to form a three-dimensional circuit, and the third insulating layer (8), which is the uppermost layer, has a chip-shaped semiconductor integrated circuit ( 9) In a multi-chip module equipped with the same, the first insulating layer (4) is formed of a composite dielectric layer (13) composed of two layers of a high dielectric constant dielectric and an organic or inorganic dielectric. Multi-chip module characterized by the following.
【請求項2】 前記高誘電率誘電体がペロブスカイト系
酸化物であり、有機または無機誘電体がポリイミドまた
は酸化硅素化合物よりなることを特徴とする請求項1記
載のマルチチップモジュール。
2. The multi-chip module according to claim 1, wherein the high dielectric constant dielectric is a perovskite oxide, and the organic or inorganic dielectric is a polyimide or a silicon oxide compound.
JP6126299A 1994-06-08 1994-06-08 Multi-chip module Withdrawn JPH07335779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6126299A JPH07335779A (en) 1994-06-08 1994-06-08 Multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6126299A JPH07335779A (en) 1994-06-08 1994-06-08 Multi-chip module

Publications (1)

Publication Number Publication Date
JPH07335779A true JPH07335779A (en) 1995-12-22

Family

ID=14931773

Family Applications (1)

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JP6126299A Withdrawn JPH07335779A (en) 1994-06-08 1994-06-08 Multi-chip module

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100308872B1 (en) * 2000-02-23 2001-11-03 이상헌 Multi-Layered Multi-chip Module
KR100618788B1 (en) * 1999-07-22 2006-09-06 삼성전자주식회사 Print Circuit Board for preventing a Electrostatic discharge damage
US7816768B2 (en) 2007-01-19 2010-10-19 Elpida Memory, Inc. Semiconductor device including ground and power-supply planes and a dielectric layer between the ground and power-supply planes
US10573835B2 (en) 2014-12-22 2020-02-25 Nokia Technologies Oy Modular electronics apparatuses and methods

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618788B1 (en) * 1999-07-22 2006-09-06 삼성전자주식회사 Print Circuit Board for preventing a Electrostatic discharge damage
KR100308872B1 (en) * 2000-02-23 2001-11-03 이상헌 Multi-Layered Multi-chip Module
US7816768B2 (en) 2007-01-19 2010-10-19 Elpida Memory, Inc. Semiconductor device including ground and power-supply planes and a dielectric layer between the ground and power-supply planes
US10573835B2 (en) 2014-12-22 2020-02-25 Nokia Technologies Oy Modular electronics apparatuses and methods

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