US4439813A - Thin film discrete decoupling capacitor - Google Patents
Thin film discrete decoupling capacitor Download PDFInfo
- Publication number
- US4439813A US4439813A US06/285,650 US28565081A US4439813A US 4439813 A US4439813 A US 4439813A US 28565081 A US28565081 A US 28565081A US 4439813 A US4439813 A US 4439813A
- Authority
- US
- United States
- Prior art keywords
- layer
- conductive layer
- capacitor
- dielectric
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 51
- 239000010409 thin film Substances 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005272 metallurgy Methods 0.000 claims abstract description 27
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- 239000000919 ceramic Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 3
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 230000001737 promoting effect Effects 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 description 11
- 230000008021 deposition Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000002241 glass-ceramic Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
- H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/43—Electric condenser making
- Y10T29/435—Solid dielectric type
Definitions
- This invention relates to discrete decoupling capacitors utilized as components attached to the surface of a substrate for semi-conductors.
- Multi-layer ceramic VLSI chip packaging substrates are formed by having a multiple number of flexible unfired sheets of soft ceramic material. These sheets, generally known as greenhseets, have holes or vias punched into them in a known pattern. An electrically conductive paste is then screened through a metal mask to form personalized wiring patterns on the greensheet and to fill its via holes. A completed substrate is fabricated by stacking multiple greensheet layers that are pressed together to form a semi-hard stack or laminate which is then fired. The result is a substrate for VLSI chips.
- each chip site is composed of an array of chip contact vias (C4 pads or microsockets). Disposed around each chip site is an area on the substrate for engineering changes, i.e., for wire connections to cure correctable defects in the chip or substrate.
- Advanced semiconductor circuits employ decoupling capacitors.
- the decoupling capacitors are charged independent of circuit operation and are discharged to deliver via the substrate redistribution layer a current that enables fast transition circuit switching with a minimum noise.
- the elements are conventionally mounted on a circuit board, some distance away from the chip.
- One desired technique would be the use of a decoupling capacitor as a discrete component that is attached to the surface of the substrate. Closer physical location allows for and is essential for higher switching speeds of the chip. If utilized in that manner, not only is the capacitance of the component important, but additionally, its inductance is crucial to overall performance.
- the inductance of a discrete capacitor is directly proportional to the number of interconnections between it and the chip-carrying substrate. The larger number of bonds is desirable and results in a lower inductance. Moreover, the closer to the logic chip the capacitor is placed, the lower the inductance.
- a further object of this invention is to define a capacitor design offering low inductance, simplicity, and dimensional compatibility with VLSI packaging techniques.
- Yet another object of this invention is to define a discrete component capacitor of extreme small size dimensionally applicable for mounting on integrated circuit substrates.
- a further object of this invention is to provide a decoupling capacitor utilized on ceramic and other suitable substrates (e.g. alumina, glass-ceramic, etc.).
- a bottom electrode layer is formed by evaporation or sputtering onto the carrier surface.
- a dielectric layer is then formed by sputtering directly onto the bottom conductive layer.
- a typical dielectric material is lead lanthanium zirconate titanate (PLZT).
- a top conductive layer is then deposited onto the dielectric layer followed by an insulating layer such as sputtered quartz, polyimide, etc.
- Ball limiting metalization (BLM) is then used to limit the spread of the conductive solder ball.
- An array of solder balls is used to establish multiple contact to the mounting pad thereby lowering the inductance of the capacitor.
- the discrete capacitor itself utilizes two sets of via holes, the first set extending through the insulating layer to expose the top conductive layer and, a second set extending through the insulating layer, the top conductive layer, and the dielectric layer to expose the bottom conductive layer.
- the isolated solder mounds are deposited on the insulating layer over each via hole to provide electrical continuity between the capacitor mounting location at the chip site and the conductive layers.
- FIG. 1 is a cutaway view of a discrete capacitor made in accordance with the present invention
- FIG. 1A is a cut away perspective view of the capacitor of FIG. 1;
- FIG. 2 is a cross-section of the capacitor of FIG. 1 showing a through-via coupling to the bottom metallurgy;
- FIGS. 3A to 3E are schematic drawings showing the steps
- FIGS. 4A to 4C are schematic drawings showing the process.
- FIG. 1A a cutaway perspective view of the discrete capacitor in accordance with the present invention is shown.
- the capacitor is mounted on a silicon carrier since this material is amenable to thin film processing.
- the carrier is electrically inactive and accordingly, wafers not meeting electrical specifications for normal Si chips can be used as carriers for the capacitor in accordance with this invention. It is apparent, however, that glass, glass-ceramic or ceramic carriers having proper surface preparation can also be used for the base of the present capacitor.
- the capacitor can be built by layering directly on a bottom metallurgy without any support or carrier structure.
- FIGS. 1 and 1A show successive layers forming this invention.
- Deposited on a silicon carrier is the bottom metallurgy forming the bottom electrode.
- This layer is evaporated or sputtered onto the carrier surface with the choice of material being dependent on the type of material used to form the next layer, the dielectric layer.
- a high temperature metallurgy such as Ti/W or Ta is used to form the bottom metallurgy layer.
- conventional bottom metallurgy such as Cu or Al may be utilized.
- a typical material satisfying this requirement is lead lanthanum zirconate titanate (PLZT) in the amorphous or as-sputtered state. If a film of this material is properly heat-treated in the range of 600°-700° C., or, is hot sputtered, its K can reach values in the order of 500. It is apparent that with so high a value of K, the thickness of the dielectric film can be substantially increased to improve its reliability and voltage breakdown.
- Another material that can be employed for the dielectric layer is BaTiO 3 .
- the upper metallurgy which is evaporated onto the surface after heat treatment, if required.
- Choices of metal include Al or Cu. It is apparent that any other suitable material known in the technology may be used.
- An insulating layer such as quartz (SiO 2 ) is then sputtered on top of the upper metallurgy to isolate the top plate from the bottom electrode.
- ball limiting metallurgy pads BLM are positioned in a regular array to limit the spread of each solder ball.
- Materials common to Si chip fabrication such as Cr/Cu/Au may be utilized and as will be delineated, BLM techniques are well established in the art.
- An important aspect of this invention is the facet of utilizing a through via to provide a hole for establishing electrical contact from the top surface having the BLM pad to the bottom metallurgy layer. Accordingly, by subsequent placement of solder balls on the BLM pads, electrical contact with the top and bottom metallurgy is established.
- the solder balls mount to a similar footprint on the substrate establishing a very low inductance coupling.
- FIGS. 2 and 3 the steps of fabrication to establish a through-via to the bottom metallurgy are shown together with the resulting structure having a solder ball placed over the through-via.
- FIG. 3A shows the initial deposition of top and bottom metallurgy separated by the dielectric material. Typical dimensions are 3 ⁇ m for the bottom metallurgy, 2 ⁇ m for the top metallurgy, and, dielectric layer in the range of 0.5-1.0 ⁇ m. Half of the couplings must be to the bottom electrode and these are achieved by means of etching shown in FIGS. 3B-3D to achieve a through-via.
- FIG. 3B shows the first step of etching away the top metallurgy and the dielectric utilizing photolithographic techniques.
- etchants are utilized. These process techniques are well known in the technology.
- FIG. 3B the bottom electrode is exposed by this etching step.
- An electrically insulting material such as quartz is then applied over the entire capacitor surface as shown in FIG. 3C.
- deposition achieves a layer in the range of 3 ⁇ m.
- FIG. 3D again utilizing photolithographic techniques and a proper selective etchant, the bottom electrode is again exposed by etching the insulation. This etching step isolates the top electrode from the bottom electrode utilizing the insulation as the isolating layer.
- the final step shown in FIG. 3E is the deposition of the BLM metallurgy utilizing conventional materials and techniques as defined herein.
- a typical layer of BLM is in the range of 1 ⁇ m.
- a solder ball is placed on top of the BLM. Accordingly, electrical continuity is achieved to the bottom metallurgy.
- the use of solder pads employing the solder ball shown in FIG. 2 has been the subject of investigations to achieve reliable connections of optimum geometric shape. Reference is made to "Reliability of Controlled Collapse Interconnections", K. C. Norris et al, IBM J. Res. Develop., May, 1969, pages 266-271; "Controlled Collapse Reflow Chip Joining", L. F. Miller, IBM J. Res.
- the ultimate through-via connection may have typically a diameter in the range of 36 ⁇ m with the solder ball having a diameter across the BLM in the range of 74 ⁇ m.
- the BLM controls solder ball size such that it is compatible with footprint connections.
- FIG. 4 the steps of forming the top surface connections are shown.
- the top layer, dielectric layer, and bottom metallurgy layer are first deposited onto the carrier.
- FIG. 4A the next step, deposition of the insulation is shown. This is the same step as shown in FIG. 3C.
- FIG. 4B shows etching of the insulation in a manner compatible with that shown in FIG. 3D.
- the subsequent step, deposition of the BLM is also compatible with that shown in FIG. 3E. It is apparent that etching of the insulating layer in FIG. 4B exposes only the top electrode.
- a border is provided about the capacitor structure BLM pad area to prevent smearing of the top and bottom metallurgy layers during dicing.
- the capacitors are formed on a large wafer and when all process steps are complete, the structure is cut or "diced" to provide for individual elements.
- the border establishes the area for cutting without slicing into the substantive layers.
- a discrete capacitor utilized on very thin carriers is defined by this invention.
- Mounting directly on the surface of a multi-layer ceramic substrate e.g. alumina, glass-ceramic, etc.
- a discrete decoupling capacitor is used in conjunction with integrated circuitry provided on the substrate.
- the capacitor is mounted with the solder balls face down, in contact with a compatible pad footprint at a location on the substrate surface.
- the capacitor is mounted as electronically close as possible to the chip.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (13)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/285,650 US4439813A (en) | 1981-07-21 | 1981-07-21 | Thin film discrete decoupling capacitor |
JP57081726A JPS5815219A (en) | 1981-07-21 | 1982-05-17 | Chip capacitor |
CA000404031A CA1182583A (en) | 1981-07-21 | 1982-05-28 | Thin film discrete decoupling capacitor |
DE8282104815T DE3273531D1 (en) | 1981-07-21 | 1982-06-02 | Discrete thin film capacitor |
EP82104815A EP0070380B1 (en) | 1981-07-21 | 1982-06-02 | Discrete thin film capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/285,650 US4439813A (en) | 1981-07-21 | 1981-07-21 | Thin film discrete decoupling capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
US4439813A true US4439813A (en) | 1984-03-27 |
Family
ID=23095143
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/285,650 Expired - Lifetime US4439813A (en) | 1981-07-21 | 1981-07-21 | Thin film discrete decoupling capacitor |
Country Status (5)
Country | Link |
---|---|
US (1) | US4439813A (en) |
EP (1) | EP0070380B1 (en) |
JP (1) | JPS5815219A (en) |
CA (1) | CA1182583A (en) |
DE (1) | DE3273531D1 (en) |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3936579A1 (en) * | 1989-04-04 | 1990-10-11 | Avx Corp | METHOD FOR FORMING THIN FILM TERMINALS FOR CERAMIC CAPACITORS OF LOW INDUCTIVITY AND ITEM PRODUCED THEREOF |
WO1996007196A1 (en) * | 1994-08-31 | 1996-03-07 | Cornell Research Foundation, Inc. | Tiled panel display assembly |
US5731960A (en) * | 1996-09-19 | 1998-03-24 | Bay Networks, Inc. | Low inductance decoupling capacitor arrangement |
US5872697A (en) * | 1996-02-13 | 1999-02-16 | International Business Machines Corporation | Integrated circuit having integral decoupling capacitor |
US6165814A (en) * | 1997-05-23 | 2000-12-26 | Micron Technology, Inc. | Thin film capacitor coupons for memory modules and multi-chip modules |
US6324048B1 (en) | 1998-03-04 | 2001-11-27 | Avx Corporation | Ultra-small capacitor array |
US6366443B1 (en) * | 1997-12-09 | 2002-04-02 | Daniel Devoe | Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely-spaced interior conductive planes reliably connecting to positionally-tolerant exterior pads through multiple redundant vias |
US6477032B2 (en) * | 2001-01-31 | 2002-11-05 | Avx Corporation | Low inductance chip with center via contact |
US6516504B2 (en) * | 1996-04-09 | 2003-02-11 | The Board Of Trustees Of The University Of Arkansas | Method of making capacitor with extremely wide band low impedance |
US6542352B1 (en) | 1997-12-09 | 2003-04-01 | Daniel Devoe | Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias |
US6555912B1 (en) | 2001-10-23 | 2003-04-29 | International Business Machines Corporation | Corrosion-resistant electrode structure for integrated circuit decoupling capacitors |
US6624500B2 (en) | 2000-11-30 | 2003-09-23 | Kyocera Corporation | Thin-film electronic component and motherboard |
US6661639B1 (en) | 2002-07-02 | 2003-12-09 | Presidio Components, Inc. | Single layer capacitor |
US20040057192A1 (en) * | 2001-09-05 | 2004-03-25 | Galvagni John L. | Cascade capacitor |
US20040108596A1 (en) * | 2001-02-23 | 2004-06-10 | Intel Corporation | Selectable decoupling capacitors for integrated circuit and methods of use |
US20040221083A1 (en) * | 1997-09-26 | 2004-11-04 | Rambus Inc. | High frequency bus system |
US6885539B1 (en) | 2003-12-02 | 2005-04-26 | Presidio Components, Inc. | Single layer capacitor |
US6917509B1 (en) | 2002-11-21 | 2005-07-12 | Daniel F. Devoe | Single layer capacitor with dissimilar metallizations |
US6964087B1 (en) * | 2004-05-12 | 2005-11-15 | Lei-Ya Wang | Method for manufacturing dielectric ceramic layer and internal polar layer of multiple layer ceramic capacitors (MLCC) by vacuum sputtering |
US7016175B2 (en) | 2002-10-03 | 2006-03-21 | Avx Corporation | Window via capacitor |
US20070035911A1 (en) * | 2002-10-03 | 2007-02-15 | Avx Corporation | Window via capacitors |
US20100240249A1 (en) * | 2002-05-07 | 2010-09-23 | Applied Technology And Solutions | Electrical wiring system |
US20140264741A1 (en) * | 2013-03-15 | 2014-09-18 | International Business Machines Corporation | Capacitor using barrier layer metallurgy |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6188904A (en) * | 1984-10-09 | 1986-05-07 | Kawasaki Steel Corp | Manufacture of quenched fine crystalline thin-strip and its device |
JPH03110861A (en) * | 1989-09-26 | 1991-05-10 | Matsushita Electric Ind Co Ltd | Manufacture of ferroelectric thin film |
DE4300808C1 (en) * | 1993-01-14 | 1994-03-17 | Siemens Ag | Film capacitor prodn. from 2 types of conductive films and dielectric - using selective under-etching of one type of conductive film in each contact hole to increase capacity e.g. for passive device or IC |
US7666010B2 (en) | 2006-10-27 | 2010-02-23 | Leviton Manufacturing Company, Inc. | Modular wiring system with locking elements |
US7955096B2 (en) | 2006-10-27 | 2011-06-07 | Leviton Manufacturing Company, Inc. | Modular wiring system with locking elements |
US8371863B1 (en) | 2011-07-29 | 2013-02-12 | Leviton Manufacturing Company, Inc. | Modular wiring system |
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US3021589A (en) * | 1958-06-05 | 1962-02-20 | Vitramon Inc | Methods for installing terminal leads in composite electrical components and resulting products |
US3278815A (en) * | 1961-01-11 | 1966-10-11 | Mallory & Co Inc P R | Electrical capacitor with a boron nitride dielectric |
US3292240A (en) * | 1963-08-08 | 1966-12-20 | Ibm | Method of fabricating microminiature functional components |
US3303393A (en) * | 1963-12-27 | 1967-02-07 | Ibm | Terminals for microminiaturized devices and methods of connecting same to circuit panels |
US3638085A (en) * | 1970-11-13 | 1972-01-25 | Sprague Electric Co | Thin film capacitor and method of making same |
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US4071878A (en) * | 1975-02-18 | 1978-01-31 | N L Industries, Inc. | Method for producing capacitors and ceramic body therefore |
US4104697A (en) * | 1975-06-02 | 1978-08-01 | Texas Instruments Incorporated | Discrete, fixed-value capacitor |
Family Cites Families (5)
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US3324362A (en) * | 1961-12-21 | 1967-06-06 | Tassara Luigi | Electrical components formed by thin metallic form on solid substrates |
US3491275A (en) * | 1967-05-02 | 1970-01-20 | Sprague Electric Co | Flat capacitor |
US3745430A (en) * | 1971-12-21 | 1973-07-10 | Motorola Inc | Thick film feed-through capacitor |
US3811186A (en) * | 1972-12-11 | 1974-05-21 | Ibm | Method of aligning and attaching circuit devices on a substrate |
JPS49121957A (en) * | 1973-03-31 | 1974-11-21 |
-
1981
- 1981-07-21 US US06/285,650 patent/US4439813A/en not_active Expired - Lifetime
-
1982
- 1982-05-17 JP JP57081726A patent/JPS5815219A/en active Granted
- 1982-05-28 CA CA000404031A patent/CA1182583A/en not_active Expired
- 1982-06-02 DE DE8282104815T patent/DE3273531D1/en not_active Expired
- 1982-06-02 EP EP82104815A patent/EP0070380B1/en not_active Expired
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US3021589A (en) * | 1958-06-05 | 1962-02-20 | Vitramon Inc | Methods for installing terminal leads in composite electrical components and resulting products |
US3278815A (en) * | 1961-01-11 | 1966-10-11 | Mallory & Co Inc P R | Electrical capacitor with a boron nitride dielectric |
US3292240A (en) * | 1963-08-08 | 1966-12-20 | Ibm | Method of fabricating microminiature functional components |
US3303393A (en) * | 1963-12-27 | 1967-02-07 | Ibm | Terminals for microminiaturized devices and methods of connecting same to circuit panels |
US3638085A (en) * | 1970-11-13 | 1972-01-25 | Sprague Electric Co | Thin film capacitor and method of making same |
US3897074A (en) * | 1974-02-22 | 1975-07-29 | Karhu Titan Oy | Ski with microporous bottom surface |
US4071878A (en) * | 1975-02-18 | 1978-01-31 | N L Industries, Inc. | Method for producing capacitors and ceramic body therefore |
US4104697A (en) * | 1975-06-02 | 1978-08-01 | Texas Instruments Incorporated | Discrete, fixed-value capacitor |
Cited By (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3936579A1 (en) * | 1989-04-04 | 1990-10-11 | Avx Corp | METHOD FOR FORMING THIN FILM TERMINALS FOR CERAMIC CAPACITORS OF LOW INDUCTIVITY AND ITEM PRODUCED THEREOF |
WO1996007196A1 (en) * | 1994-08-31 | 1996-03-07 | Cornell Research Foundation, Inc. | Tiled panel display assembly |
US5563470A (en) * | 1994-08-31 | 1996-10-08 | Cornell Research Foundation, Inc. | Tiled panel display assembly |
US5693170A (en) * | 1994-08-31 | 1997-12-02 | Cornell Research Foundation, Inc. | Tiled panel display assembly |
US5872697A (en) * | 1996-02-13 | 1999-02-16 | International Business Machines Corporation | Integrated circuit having integral decoupling capacitor |
US6303457B1 (en) | 1996-02-13 | 2001-10-16 | Todd Alan Christensen | Integrated circuit having integral decoupling capacitor |
US6516504B2 (en) * | 1996-04-09 | 2003-02-11 | The Board Of Trustees Of The University Of Arkansas | Method of making capacitor with extremely wide band low impedance |
US5731960A (en) * | 1996-09-19 | 1998-03-24 | Bay Networks, Inc. | Low inductance decoupling capacitor arrangement |
US6165814A (en) * | 1997-05-23 | 2000-12-26 | Micron Technology, Inc. | Thin film capacitor coupons for memory modules and multi-chip modules |
US6342724B1 (en) | 1997-05-23 | 2002-01-29 | Micron Technology, Inc. | Thin film capacitor coupons for memory modules and multi-chip modules |
US8214575B2 (en) | 1997-09-26 | 2012-07-03 | Rambus Inc. | Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices |
US20110090727A1 (en) * | 1997-09-26 | 2011-04-21 | Haw-Jyh Liaw | Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at Synchronous Memory Devices |
US20060277345A1 (en) * | 1997-09-26 | 2006-12-07 | Haw-Jyh Liaw | High Frequency Bus System |
US20070150636A1 (en) * | 1997-09-26 | 2007-06-28 | Haw-Jyh Liaw | Memory Module Having a Clock Line and Termination |
US8364878B2 (en) | 1997-09-26 | 2013-01-29 | Rambus Inc. | Memory module having signal lines configured for sequential arrival of signals at a plurality of memory devices |
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Also Published As
Publication number | Publication date |
---|---|
JPS5815219A (en) | 1983-01-28 |
CA1182583A (en) | 1985-02-12 |
DE3273531D1 (en) | 1986-11-06 |
EP0070380A2 (en) | 1983-01-26 |
EP0070380A3 (en) | 1984-04-25 |
EP0070380B1 (en) | 1986-10-01 |
JPS6348417B2 (en) | 1988-09-29 |
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