JPH0731528B2 - Programmable controller - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an improvement in a high-speed processing type programmable controller having both a bit processor and a general-purpose processor.

<< Summary of the Invention >> In the present invention, a memory is pre-stored corresponding to each application instruction in accordance with the execution condition, the code of the instruction group to which the application instruction belongs, and the bit processor reads each instruction,
When the basic instruction is read, the operation of the basic instruction is executed, while when the application instruction is read, the instruction group code corresponding to the application instruction is read from the memory,
Based on the instruction group code and the operation result of the basic instruction, it is determined whether or not the execution condition of the application instruction is satisfied, and when the execution condition of the application instruction is satisfied, the application instruction is executed by the general-purpose processor side. When the execution condition of the application instruction is not satisfied, the application instruction is skipped on the bit processor side.

<< Prior art and its problems >> In this type of high-speed programmable controller, there are a bit processor that executes basic instructions such as LD and AND, and a general-purpose processor that executes application instructions such as MOV and ADD. The bit processor always holds the control right to read and decode the user instruction. When the basic instruction is decoded, the instruction circuit processes the instruction, while the application instruction is decoded, the control right is used for general purpose. It is configured to be delivered to the processor side and to be processed by the general-purpose processor side.

However, in such a conventional high-speed programmable programmable controller, when the application instruction is decoded, the control right is unconditionally transferred to the general-purpose processor side, so the execution condition is defined. In the case of the application instruction, if the condition is not satisfied, the transfer of control right from the bit processor side to the general-purpose processor side is wasted, and there is a problem that the processing speed is reduced accordingly.

«Object of the Invention» An object of the present invention is to further reduce the dead time by minimizing the transfer of the control right from the bit processor side to the general-purpose processor side in the high-speed programmable controller of this type. It is to achieve high-speed processing.

<< Configuration and Effect of the Invention >> In order to achieve the above-mentioned object, the present invention is a programmable controller having both a bit processor for executing a basic instruction and a general-purpose processor for executing an application instruction. A memory is provided in which the codes of the instruction group to which the instruction belongs is stored in advance corresponding to each application instruction, and the bit processor includes an instruction reading unit for reading each instruction and a basic instruction when the basic instruction is read by the instruction reading unit. Is a bit operation means for executing an operation of the basic instruction, and, when the application instruction is read by the instruction reading means, reads an instruction group code corresponding to the application instruction from the memory and outputs the instruction group code. And whether or not the execution condition of the application instruction is satisfied based on the operation result of the bit operation means and the application instruction. When the execution condition of is satisfied, the application instruction is executed by the general-purpose processor side, and when the execution condition of the application instruction is not satisfied, the application instruction is skipped by the bit processor side. It is a feature.

With such a configuration, even if the application instruction is decoded on the bit processor side, it is desired to pass the control right from the bit processor side to the general-purpose processor side unless the determination circuit determines that the instruction execution condition is satisfied. Therefore, the processing speed can be increased accordingly.

Further, according to the present invention, the operation control of the general-purpose processor that executes the application instruction is performed by the memory in which the execution condition of the application instruction is recorded in advance and the determination means other than the bit operation means, and the basic instruction by the bit operation means is performed. Since it does not affect the execution of, there is no increase in the number of arithmetic programs consisting of basic instructions, and the bit arithmetic processing becomes faster.

<< Description of Embodiments >> FIG. 1 is a block diagram showing the electrical hardware configuration of a high-speed processing programmable controller to which the present invention is applied.

As shown in the figure, this programmable controller is composed of two processors 1, 2, an I / O memory 3, a user memory 4, and a bit processor (hereinafter referred to as BPU) and a general-purpose processor (hereinafter referred to as MPU). Operates flag memory 5, system memory 6, work memory 7, peripheral interface supporting peripheral devices 8, input / output devices
It is equipped with an I / O interface 9 and the like.

The MPU 2 has the initiative of the entire programmable controller and operates according to the program written in the system memory 6. Further, the I / O memory 3, the user memory 4, and the flag memory 5 can be accessed through the BPU 2.

By this, 1) Writing and reading user program from peripheral device 2) Creation of flag memory 3) I / O refresh, control of high-performance I / O 4) BPU start / stop 5) Execution of application instruction 6) Creation of internal reference clock 7) It is designed to execute interrupt processing.

On the other hand, the BPU1 operates by starting up the MPU2, and by the program counter as the instruction reading means inside the BPU1, the bit operation unit as the bit operation means, the determination circuit as the determination means, etc., 1) reading of the user program 2 ) Execution of basic instruction 3) Reading of flag memory 4) Skip processing when application instruction is not executed 5) Execution of differential flag writing, etc.

As shown in FIG. 2, the flag memory 5 has a 4-bit area corresponding to 1 word (16 bits) of the user program. Of these, 1-bit FD ₃ is called a differential flag, and the remaining 3-bits FD ₀ , FD ₁ and FD ₂ indicate the instruction group type code.

The differential flag FD ₃ is the operation result of the bit operation unit, that is, the rising edge of the power flow (hereinafter referred to as PF) (“0”, →
This is a flag for detecting "1") and falling ("1" → "0"). When the application instruction is read, the PF value at that time is input for each scan.

FIG. 3 shows the type of instruction group stored in the flag memory 5 and the contents of the operation, and FIG. 4 shows a determination circuit for determining the type.

Instruction group 0 indicates a basic instruction group and is always executed by BPU1. Instruction group 1 is a group of instructions that are always processed by MPU2.
D command etc. correspond to this. When the instruction belongs to group 1, BPU1 unconditionally stops and passes the initiative to MPU2.

Instruction group 2 is a group of instructions executed at the rise of PF. This is the PF value from the previous scan (hereinafter PPF
Is read from the differential flag FD ₃ and is compared with the current value of PF to detect the rise of PF. Then, at the start-up, BPU1 is stopped and the initiative is handed over to MPU2.

When not rising, a skip circuit (not shown) in BPU1 operates to skip to the beginning of the next instruction word.

Instruction group 3 is a group of instructions executed at the rise of PF. As with instruction group 2, the previous PF and the current PF
The falling edge is detected by comparing with
Pass control to U2, skip others.

Instruction group 4 is an instruction group that is executed only when PF = "1", and instruction group 5 is an instruction group that is executed only when PF = "0". Each is passed to MPU2 when the execution condition is satisfied, and skipped when it is not satisfied. .

The instruction group 7 indicates the second and subsequent words of the instruction word, and is used for searching the beginning of the next instruction word when skipping.

The above instruction group codes are shown in FIG.
Decoded by 8 decoders. The decode output 1 becomes the BPU processing command signal S ₁ , and the decode output 2 unconditionally becomes the MPU processing command signal S ₂ . Further, the decode output 7 becomes the skip processing command signal S ₃ unconditionally. Regarding the decode outputs 2 to 5, the AND gates 10a to 10d serve as the MPU processing signal S ₂ only when the logical condition is satisfied, and the AND gate 10e serves as the skip processing command signal S ₃ when the logical condition is not satisfied.

Next, FIG. 5 is a general flow chart schematically showing the control contents executed by the MPU, and the operation of the MPU will be systematically described below with reference to this flow chart.

When the program is started by turning on the power, first, the initial process is executed to initialize various flags and registers. In particular, in the present invention, the user memory shown in FIG. 2 is searched from the beginning. An automatic process for analyzing which naming group each instruction word belongs to and sequentially registering the analysis result in the flag memory is performed (step 501).

In the subsequent system service processing, known programming processing, monitor processing, etc. are performed to detect key operations from the programming tool (step 502).

In the subsequent input update processing, input data is fetched from the input / output device via the I / O interface 9 and written in the input area of the I / O memory 3 (step 503).

After that, until the operation of the RUN key is confirmed in the system service processing (No at step 504), all outputs are forcibly set to the OFF state via the I / O interface 9 (step 505).

In this state, when a RUN operation is performed with a programming tool (not shown) (Yes in step 504), the execution process of the user program is started.

In this instruction execution processing, the BPU1 and MPU2 are appropriately used to execute the user instruction execution processing according to the flowcharts of FIGS. 6 and 7 described later, and finally wait until the END instruction is detected (step 507 affirmative), and shifts to output update processing.

In this output update process, the rewriting is completed with the result of command execution.
The output data of the I / O memory is sent to the output device via the I / O interface 9.

Then, the processes of steps 501 to 508 are repeated as long as the RUN mode continues.

Next, the main part of the present invention will be described with reference to FIGS. 6 and 7.

As described above, the group type code obtained by analyzing the user program according to the table prepared in advance is registered in the flag memory 5 before entering the RUN mode.

At this time, the initial value of group 2 is “1” in the fine powder flag FD _3.
Group 3 stores the initial value “0”.

Here, the user program written in the user memory 4 is compatible with the conventional model and the commonality of the peripheral device.
The same instruction code as the conventional one is used.

Execution of the user program is performed in the procedure shown by the operation flow of the MPU of FIG. 6 and the operation flow of the BPU of FIG.

That is, first, the MPU2 sets the program counter of the BPU1 at the head of the user program and activates the BPU1 (step 601). After that, MPU2 waits until BPU1 stops (No at step 602).

On the other hand, the BPU 1 reads the user instruction (step 701) and first determines whether it is a basic instruction (step 702). If it is a basic instruction (Yes at Step 702), the instruction is executed as it is by its own bit operation unit (Step 703), and the next user instruction is read (Step 701).

If it is not a basic instruction, that is, if it is an application instruction (No at step 702), then the group type code is read from the flag memory (step 704).

Next, it is judged from the output of the judgment circuit shown in FIG. 4 whether or not the execution condition of the application instruction is satisfied (step 705), and if the condition is not satisfied (step 705 negative), a skip circuit (not shown). ) To skip to the beginning of the next instruction.

If the application instruction execution condition is satisfied (Yes at Step 705), the BPU1 is stopped and the initiative is transferred to MPU2 (Step S705).
706).

The MPU2 detects that the BPU1 has stopped (Yes at Step 602), and determines the cause of the stop. If the BPU1 stops due to a command other than the application command (No at step 603), it is considered to be abnormal and abnormal processing is performed.

If stopped by an application command (Yes at step 603), firstly E
Whether it is the ND instruction or not is judged (step 604), and if it is the END instruction (step 604: Yes), the execution of one scan of the user program is ended.

If it is an application command other than the END command (No at step 604),
The command word is executed (step 605), and B is read from the next command word.
Start the PU and continue executing the user program.

As described above, MPU2 and BPU1 during user program execution
It is possible to minimize unnecessary delivery between the two and to speed up the process.

Further, since the flag memory 4 is composed of RAM, the group type can be changed as needed. For example, for an instruction that you want to execute at both rising and falling edges of PF, position it in group 2 at the beginning,
The flag memory is rewritten in group 3 at the time of rising.
If it is returned to group 2 at the next fall, the instruction will be executed at both the rise and fall. By changing the group by the user command itself in this way, more appropriate execution conditions can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical hardware configuration of a high-speed processing type programmable controller to which the present invention is applied, FIG. 2 is a memory map showing contents of a flag memory and a user memory, and FIG. 3 is each instruction. A memory map showing the contents of a table showing the relationship between group codes and instruction execution conditions, FIG. 4 is a block diagram showing a condition satisfaction determination circuit provided in the BPU, and FIG. 5 is a general flowchart showing the configuration of the control program of the MPU. FIG. 6 is a flowchart showing the operation of the MPU in the instruction execution process, and FIG. 7 is a flowchart showing the operation of the BPU in the instruction execution process. 1 …… BPU 2 …… MPU 4 …… User memory 5 …… Flag memory 13 …… Judgment circuit

Claims (3)

[Claims] 1. A bit processor for executing basic instructions,
In a programmable controller that also includes a general-purpose processor that executes application instructions, a memory that prestores codes of an instruction group to which each application instruction belongs based on execution conditions is provided corresponding to each application instruction. An instruction reading unit for reading an instruction; a bit operation unit for executing an operation of the basic instruction when the basic instruction is read by the instruction reading unit; and an application instruction for reading the application instruction by the instruction reading unit. Reads the instruction group code corresponding to the application instruction from the memory, determines whether the execution condition of the application instruction is satisfied based on the instruction group code and the operation result of the bit operation means, When the execution condition of the application instruction is satisfied, the application instruction is executed by the general-purpose processor side, and the execution condition of the application instruction is executed. There programmable controller characterized by comprising: a determination means for skipping the application instructions at the bit processor side when not satisfied. 2. The instruction group code is written to the memory by analyzing which instruction group each instruction word in the user program belongs to before starting execution of the user program, and writing the analysis result. The programmable controller according to claim 1, which is performed by automatic processing. 3. An instruction group code is written to the memory by an automatic process of writing a specified instruction group code to a specified address when a specific instruction word is read from a user program. The programmable controller according to claim 1.