JPH0729636Y2 - Semiconductor wafer inspection system - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor wafer inspection apparatus capable of performing a debugging work together with a characteristic inspection of an IC chip. More specifically, for debugging directly from a performance board or the like. The present invention relates to a semiconductor wafer inspection device provided with a contact ring capable of obtaining the electric signal of

<Prior Art> A semiconductor wafer inspection apparatus measures electrical characteristics by bringing a large number of probes derived from the inspection apparatus into contact with an electrode pad for each unit chip completed on one wafer.

The electrical signal from the prober is guided to the test head and analyzed, but the inspection items of the IC vary depending on the purpose and function of the IC, and therefore, on the performance board between the prober and the test head. A circuit with the inspection function required for ICs is provided to support various inspection items.

In the debugging work in such a semiconductor wafer inspection apparatus, it is necessary to obtain a signal for debugging at a position close to the IC in order to obtain a good signal waveform. For this reason, the conventional inspection apparatus is configured to obtain a signal for debugging by connecting the measurement cable to the electric wiring on the performance board.

<Problems to be Solved by the Invention> However, the conventional device having such a configuration has the following problems.

1) When changing the measurement point, the test head must be removed from the performance board and the measurement cable must be reconnected to the desired measurement point.

2) The performance board must be replaced every time the type of IC chip changes, so it is necessary to reconnect the performance board and the measurement cable for debugging.

3) It is necessary to pull out the measurement cable, which is separately wired from the performance board for debugging, to the outside of the test head and then connect it to the test point. Therefore, the signal transmission distance becomes long and the signal waveform collapses, resulting in poor quality. It is difficult to obtain a good signal waveform.

4) Since the signal for debugging is obtained only from the performance board, it is difficult to determine the abnormal portion of the electric circuit of the wafer inspection device.

The present invention has been made in view of such a point, and it is possible to easily debug with high sensitivity without degrading the quality of the measurement signal from the IC chip, and to identify the abnormal portion of the electric circuit. It is an object of the present invention to provide a semiconductor wafer inspection device that can be manufactured.

<Means for Solving the Problems> In order to achieve such an object, the present invention is provided with a removable test head electrically connected to a performance board mounted on a prober, and includes a prober and a test head. In the semiconductor wafer inspection device provided with a microscope peephole in, the insertion into the peephole of the microscope, having a contact pin for exchanging input and output signals with the IC chip on the bottom surface facing the performance board, the top surface of the It is characterized in that a contact ring having a test point connected to the contact pin via a coaxial cable is provided.

Further, a contact ring having a contact pin for transmitting / receiving an electric signal to / from a relay board to which an electric signal of the performance board is connected and a printed circuit board in the test head is mounted may be provided.

<Operation> The IC wafer mounted on the stage comes into contact with the probe pins of the prober to exchange electric signals. This electrical signal is analyzed by the test head through the performance board mounted on the prober. The electrical signal for debugging the IC circuit is connected from the land of the performance board to the contact pin of the contact ring provided in the observation hole of the microscope of the test head, and is characterized at the test point. The electrical characteristics in the test head are measured by connecting and receiving an electrical signal by connecting a contact pin provided in the middle of the contact ring to a relay board in the test head on which a plurality of printed circuit boards are mounted.

<Embodiment> An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 1 is a block diagram of a semiconductor wafer inspection apparatus according to an embodiment of the present invention, (A) is a sectional view, (B) is B-B in order to explain the electrical connection ^- as seen from the section It is a principal part top view. In the figure, 10 is a stage on which the IC wafer 11 is mounted.
It is possible to move in the XY axis direction, and IC
The probe pins 12 are configured to be aligned with the pads of the IC chip formed in the wafer 11. After the alignment of the IC chip and the probe pin is completed, the stage 10 is moved up in the direction of the arrow U so that many pads formed on the IC chip can come into contact with the probe pin 12. Reference numeral 13 is a circular probe card in which a plurality of probe pins 12 are radially provided in the center direction, and the center portion is provided with a peep hole 14 for aligning the IC chip and the probe pin 12 when viewed through a microscope from above. ing. A frog ring 15 is provided on the upper part of the probe card 13, and the contact pins 151 (arrows ↑ ↓ indicate the contact pins) are electrically connected to the probe card 13, and a screw (not shown) is used. The mechanical connection is made in. In addition, this flob ring 15 is a contact pin
It is electrically connected to the performance board 16 via 152.

The electric wiring 161 of the performance board 16 is wired inside the test head 17 side and the performance board 16 through through holes (not shown) (The electric wiring 161 of the performance board is wired inside the laminated printed circuit board. , Indicated by dashed lines in the figure). Electronic components 162 such as a relay, an amplifier and a signal source are combined and mounted on the electric wiring 161 so that various kinds of tests can be performed according to the difference of the IC chips, and the functional test of the IC chips is performed. It constitutes an electric circuit. 163 test head with signals tested on performance board 16
The contact pin 171 provided on the test head 17 is pressed by the land for connecting to the.

18 is a substantially cylindrical contact ring installed on the inner wall of the microscope peep hole 172 of the test head 17, and is inserted from the upper part of the test head 17 along the inner wall of the microscope peep hole 172 of the test head 17 so that it can be attached and detached. Has become. For this reason, the contact ring 18 can be attached in a state in which the test head 17 is mounted on the performance board 16 at the time of measurement.

Reference numeral 181 denotes a contact pin provided on the test head 17 for debugging, which is pressed against a land 164 provided around a through hole (not shown) and an electric signal from the IC chip is provided above the contact ring 18. Test point 18
Up to 2 can be taken out in the shortest distance. The contact pin 181 originally has the number of pins corresponding to the maximum number of pads of the IC to be measured, and debugging work can be performed on all the IC chips.

Reference numeral 183 denotes a positioning guide pin provided on the contact ring 18, which fits into a substantially concave guide groove 173 provided on the test head 17 side so that the contact pin 181 can press the land 164 accurately. ing. 174 is a stopper for fixing the contact ring 18 to the test head 17, which is movable in the arrow S direction and engages with a stopper groove 183 provided in the contact ring 18 to press and fix the contact ring 18 in the arrow D direction. .

Although not shown, between the contact ring 18 and the performance board 16, in order to maintain a constant pressing force of the contact pin 181 that presses the land 164 and makes an electrical connection, the contact ring 18 has a certain amount or more. Contact ring to prevent the performance board 16 from being pressed by
A pedestal that supports 18 is provided.

FIG. 2 is an explanatory view of the state before and after attaching the contact ring to the test head, (A) before attachment, (B)
In the middle of mounting, (C) shows the state after the completion of mounting.

FIG. 2 (A) shows the original state of use of the semiconductor wafer inspection apparatus when the test head 17 is mounted on the performance board 16 during measurement. In this case, only the function for inspecting the characteristics of the IC is provided, and the function for debugging is not included.

FIG. 2B shows a state in which the contact ring 18 having the debug function is being inserted along the inspection hole 172 of the microscope of the test head 17. Since it is not necessary to separately connect a signal cable for debugging to the performance board 16, the contact ring 18 can be inserted while maintaining the measurement state of FIG. 2 (A).

In FIG. 2 (C), the contact ring 18 is attached to the test head 17.
The contact pin 181 of the contact ring 18 and the land 1 on the performance board 16
It shows a state where 64 electrical connections are taken. In this state, IC measurement and debugging work can be performed.

FIG. 3 is a sectional view showing the construction of a semiconductor wafer inspection apparatus according to another embodiment of the present invention, and FIG. 4 is a perspective view showing the construction of a contact ring.

In the figure, components having the same functions as those in FIG. Reference numeral 20 is a contact ring that is cut so as to include the central axis and has a substantially inverted convex cross-sectional shape. As in the first embodiment, the guide pin 201 for positioning is provided on the test head 21 side. The groove 211 is fitted and aligned. After alignment, stopper 212 will be in stopper groove 2
02, so that the contact ring 20 is completely fixed and locked to the test head 21.

203 is the first probe pin that directly receives the electric signal of the IC from the performance board 16, and is the IC circuit and probe pin.
It works to check for abnormalities in the circuit between 12 and the frog ring 15 (P region). The first contact pin 203 meets the coaxial cable 204 laid inside the contact ring 20 and is guided through the contact ring 20 to the test point 205 provided on the contact ring 20 at the shortest distance. The signal picked up by the contact pin 203 is analyzed by an oscilloscope or the like.

Reference numeral 206 denotes a second contact pin that receives an electric signal in the test head 21 directly from the relay board 213 in the test head 21, and detects an abnormality in a circuit formed by a plurality of printed circuit boards mounted in the test head 21. It works to measure (H area). This second contact pin 206 is also the first
Similarly to the contact pin 203, the coaxial cable 204 is connected to the test point 207 on the contact ring 20 to analyze the signal characteristics.

As described above, since it is possible to measure the quality of the circuit in the P region with the first contact pin 203 and the circuit in the H region with the second contact pin 206, it is possible to block the circuit abnormality of the semiconductor wafer inspection apparatus in a block manner. It is possible to tick and it is easy to find an abnormal point in the circuit. For example, when the performance board 16 has a failure point and the semiconductor wafer inspection apparatus shows an abnormality, the first and second contact pins 20
3, 206 confirms that the measurement of the P area and the H area is normal, and the abnormality of the performance board 16 is determined.

FIG. 5 is a block diagram showing a signal flow of the semiconductor wafer inspection apparatus shown in FIG. In the figure, the arrow shown by the solid line shows the signal flow of the semiconductor wafer inspection device using the conventional HF type (high frequency measurement type) test head.

The input signal from the controller of the device body goes through the test head 21 and the probe pin 12 for input of the probe card 13
Input to the IC chip. The signal thus input is taken out as an output signal from the other output probe pin 12 and is transmitted to the controller through a path completely opposite to the input path, where the characteristic analysis of the IC chip is performed.

Next, the flow at the time of debugging will be described. The arrow shown by a broken line is a path through which an output signal is taken out during debugging. The input signal from the controller is input to the IC chip as in the conventional inspection. The signal output from the IC chip is taken out from the performance board 16 to the test point 205 on the contact ring 20 by the first contact pin 203 provided under the test head 21, and the signal characteristic in the P region is analyzed by an oscilloscope or the like. To be done.

On the other hand, the second contact pin 206 provided in the middle of the test head 21 takes out the electric signal in the test head 21 to the test point 207 on the contact ring 20 and analyzes the characteristic of the H region.

<Effect of Device> As described in detail above, the semiconductor wafer inspection apparatus of the present invention is provided with the contact ring having the contact pin that can directly obtain the electric signal for debugging from the performance board and the relay ring. This has the following effects.

1) With the test head on the performance board
Since the IC chip debug work can be performed, the IC chip debug work can be easily performed.

2) Since the maximum number of contact pins is provided on the relay ring from the beginning, so as to be compatible with all IC types,
It is not necessary to connect the connection cable for debugging to the performance board one by one.

3) Since the electric signal from the IC chip can be obtained from the performance board at the shortest distance, the signal waveform can be obtained with good quality.

4) Since the measurement signal can be obtained from the relay ring, the abnormal portion of the semiconductor wafer inspection device can be determined in a block manner from the IC portion, performance board portion, and test head portion.

[Brief description of drawings]

Figure 1 is a block diagram of a semiconductor wafer inspection apparatus according to an embodiment of the present invention, (A) is a sectional view, (B) is B-B ^- fragmentary plan view as seen from the section, Fig. 2 Test FIGS. 3A and 3B are explanatory views of a state before and after attaching a contact ring to a head. FIG. 3A is a state before attachment, FIG. FIG. 4 is a configuration sectional view of the wafer inspection apparatus, FIG. 4 is a configuration perspective view of the contact ring, and FIG. 5 is a block diagram showing a signal flow of the semiconductor wafer inspection apparatus shown in FIG. 16 ... Performance board, 164 ... Land, 17, 21 ... Test head, 172 ... Microscope peephole, 173, 211 ... Guide groove, 174, 212 ... Stopper, 18, 20 ... Contact ring, 181, ... Contact pin, 183, 201 ... Guide pin, 203
... first contact pin, 206 ... second contact pin, 213 ... relay board.

Claims (2)

[Scope of utility model registration request] 1. A semiconductor wafer inspection apparatus comprising a removable test head electrically connected to a performance board mounted on a prober, wherein the prober and the test head are provided with microscope inspection holes. A contact ring that is inserted into the hole and has a contact pin that exchanges input / output signals with the IC chip on the bottom surface facing the performance board, and a test point that is connected to the contact pin via a coaxial cable on the top surface. A semiconductor wafer inspection apparatus characterized by being provided with. 2. A contact ring having a contact pin for transmitting and receiving an electric signal to and from a relay board, to which an electric signal of the performance board is connected, and a printed circuit board in the test head is mounted. Semiconductor wafer inspection equipment.