JPH07283310A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the formation of a circular hole in the gap between an oxide film and SOG film even when wet etching is performed to form an opening in the films so that the yield of a semiconductor device can be improved by performing high-temperature annealing followed by oxidation on the SOG film after applying an SOG to the surface of the oxide film and performing low-temperature annealing on the SOG film. CONSTITUTION:After forming a gate oxide film 7 on the surface of a semiconductor substrate 1, first-layer polysilicon 2 is formed on the film 7 and oxide films 8 which become side spacers are formed on the side walls of the polysilicon 2. Then a CVD oxide film 3 is deposited on the entire surface of the substrate 1 including the polysilicon 2 and oxide films 8 and a flattened layer (SOG film) 4 is formed on the surface of the oxide film 3. After forming the SOG film 4, the film 4 is heat-treated in an oxidizing atmosphere. Namely, high-temperature annealing followed by oxidation is performed on the SOG film 4 after the SOG film 4 is formed and annealed at a low temperature. Therefore, the yield of a semiconductor device can be improved, because no circular hole is formed even when improper etching is performed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to SOG as a flattening layer.
The present invention relates to a method for manufacturing a semiconductor device using (Spin on glass).

[0002]

2. Description of the Related Art A conventional manufacturing method will be described with reference to FIGS. As shown in FIG. 2, after depositing a CVD oxide film 3 as an insulating film on the surface of the first-layer polysilicon 2
G4 is applied, and low temperature annealing and high temperature annealing are performed.
The high temperature annealing at this time is performed in nitrogen. Next SOG
And a part of the CVD oxide film is opened. Next, as shown in FIG. 3, after depositing a second layer polysilicon 5 as an adhesion layer,
The refractory metal 6 is deposited.

[0003]

However, according to the above structure method, the second layer polysilicon 5 which is the adhesion layer is formed by CVD.
The thick SOG 4 on the side surface of the window opening 8 is abnormally rapidly etched by dilute hydrofluoric acid as a pretreatment at the time of deposition, and a hole 5b is generated around the first layer polysilicon 2. When the second-layer polysilicon 5 is subsequently deposited, the polysilicon 5a, which is a part of the second-layer polysilicon 5, enters the holes 5b.
Then, the conductive polysilicon 5a causes a short circuit with another wiring or the like not shown in the drawing, which lowers the yield.

[0004]

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device with high yield and high reliability. It is in.

It is characterized in that high temperature annealing accompanied by oxidation is performed after SOG coating and low temperature annealing, and after the CVD oxide film 3 and the SOG film 4 are opened by a predetermined patterning,
This is intended to improve the yield because no holes are generated due to abnormal etching by dilute hydrofluoric acid pretreatment which is pretreatment before the second polysilicon 5 is deposited.

[0006]

The high temperature anneal accompanied by oxidation promotes the curing of SOG even inside, and makes it difficult for abnormal etching to occur due to the pretreatment process with dilute hydrofluoric acid before the deposition of the second polysilicon 5, thereby preventing the formation of vacancies. Further, this annealing has the same effect at a low temperature as compared with the case of the nitrogen atmosphere, and is therefore advantageous for a shallow junction device.

[0007]

EXAMPLES The present invention will be specifically described below with reference to examples. FIG. 1 shows a sectional view of a semiconductor device according to this embodiment. The difference from the conventional one (FIG. 3) is that there is no hole 5b, and this is because the high temperature annealing accompanied with oxidation is used.

Next, the above-mentioned annealing method will be described in detail. As shown in FIG. 1, the gate insulating film 7 is formed on the semiconductor substrate 1, and the first-layer polysilicon 2 is formed on the gate insulating film 7. An oxide film 8 serving as a spacer is formed on the side wall of the first-layer polysilicon 2.

CV is formed on the entire surface of the semiconductor substrate 1, the first-layer polysilicon 2 and the oxide film 8 by the CVD method.
The D oxide film 3 is deposited. In order to further flatten the stepped portion on the surface of the CVD oxide film 3, SOG is spin-coated over the entire surface of the CVD oxide film 3.

Here, the product name OCD of Tokyo Ohka Kogyo Co., Ltd. was used as the SOG. The composition of the OCD is obtained by dissolving a silicon compound _{(R n Si (OH) 4} -n) and additives in an organic solvent (alcohol main component, esters, ketones). The composition of the additive is composed of diffusion impurities, a vitreous former and an organic binder.

The SOG film 4 thus coated has a thickness of 40
It is annealed stepwise to about 0 ° C. For example, this stepwise anneal is performed in a nitrogen gas mist atmosphere at 150 ° C. for 30 minutes, then 300 ° C. for 30 minutes, and then 40 times.
Annealing treatment is performed at 0 ° C. for 30 minutes. After the stepwise annealing treatment, the SOG film 4 is heat-treated in water vapor at 850 ° C. to be oxidized.

By the annealing process and the thermal oxidation process described above, curing is promoted to the inside of the SOG film 4.
The film quality of the OG film 4 becomes fine. Therefore, according to the process of the present invention, even if the pretreatment process before forming the second-layer polysilicon 5 is performed with dilute hydrofluoric acid, the holes 5b are not formed inside the SOG film 4.

Although the thermal oxidation process of the SOG film 4 is described as a thermal oxidation process in steam here, a thermal oxidation process under dry oxygen can be used as another method.
However, compared with the case where dry oxygen is used as the mist atmosphere in the furnace, the case where steam is used has an advantage that the thermal oxidation treatment process can be performed at a lower temperature.

In summary, the use of steam produces the same effect as dry oxygen at lower temperatures. Further, as a method of producing water vapor, there is also a method of combusting H ₂ and O ₂ into a gaseous state. Next, the window opening 9 is formed in a part of the SOG film 4 and the CVD oxide film 3.

The window opening 9 is formed by dry etching such as plasma etching after patterning the SOG film 4. In order to remove the native oxide film existing on the surface of the semiconductor substrate 1 exposed by the window opening 9, the window opening 9 of the semiconductor substrate 1 is treated with dilute hydrofluoric acid.

This dilute hydrofluoric acid treatment process is performed at room temperature for 5 hours.
~ 30 seconds. During the treatment process with this dilute hydrofluoric acid, the SO of the SOG film 4 exposed in the window opening 9 is
The G thick film portion 4a is not abnormally etched and no void is generated. The reason for this is that the SOG film 4 according to the present invention undergoes an annealing treatment step and a thermal oxidation step, whereby the quality of the SOG film 4 becomes dense, and in the dilute hydrofluoric acid treatment,
This is because it is difficult to etch.

After the window opening 9 is treated with dilute hydrofluoric acid, the second layer polysilicon 5 is deposited in the window opening 9. This second layer polysilicon 5 is cleaned by a predetermined method,
A refractory metal 6 is deposited on the layer polysilicon 5.

Since the subsequent steps are not directly related to the present invention, description thereof will be omitted.

[0019]

According to the present invention, since SOG is applied on the insulating film and high temperature annealing accompanied by oxidation is performed after low temperature annealing, after forming an opening in the insulating film and the SOG film, wet etching is performed on this opening. Even if it is applied, no void is generated in the gap between the insulating film and SOG. Even if a polysilicon wiring is provided in this opening, it is possible to prevent short circuit with other wiring. Therefore, the present invention has a remarkable effect in improving the reliability and the yield of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device to which a manufacturing method of the present invention is applied.

FIG. 2 is a cross-sectional view of a semiconductor device to which a conventional manufacturing method is applied.

FIG. 3 is a cross-sectional view of a semiconductor device to which a conventional manufacturing method is applied.

[Explanation of symbols]

 1 Semiconductor Substrate 2 First Layer Polysilicon 3 CVD Oxide Film 4 SOG Film 4a SOG Thick Film Part 5 Second Layer Polysilicon 5a Polysilicon in Hole 5b Hole 6 Refractory Metal 7 Gate Insulating Film 8 Oxide Film 9 Window opening

Claims (6)

[Claims] 1. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, a step of forming a side spacer on a side wall of the gate electrode, and forming an insulating film on the gate electrode. A method of manufacturing a semiconductor device, comprising: a step of forming a flattening layer on the insulating film; and a step of heat-treating the flattening layer in an oxidizing atmosphere. 2. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, a step of forming side spacers on the sidewalls of the gate electrode, and an insulating film on the gate electrode. A method of manufacturing a semiconductor device, comprising: a step of forming a planarization layer on the insulating film; and a step of subjecting the planarization layer to an oxidization heat treatment. 3. The flattening layer is SOG (spin on glass).
3. The method for manufacturing a semiconductor device according to claim 1, wherein: 4. The method for manufacturing a semiconductor device according to claim 2, wherein the heat treatment step is performed at 400 ° C. or lower. 5. The oxidation heat treatment step is performed under an oxidizing atmosphere at 85.
3. The method according to claim 1, wherein the temperature is 0 ° C. or higher.
A method for manufacturing a semiconductor device as described above. 6. A combustion gas in which the oxidizing atmosphere is H ₂ and O ₂ ,
The method of manufacturing a semiconductor device according to claim 5, wherein the vapor is steam or dry oxygen.